From owner-freebsd-mips@FreeBSD.ORG Mon Feb 20 11:07:10 2012 Return-Path: Delivered-To: freebsd-mips@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 63F15106567A for ; Mon, 20 Feb 2012 11:07:10 +0000 (UTC) (envelope-from owner-bugmaster@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:4f8:fff6::28]) by mx1.freebsd.org (Postfix) with ESMTP id 391158FC08 for ; Mon, 20 Feb 2012 11:07:10 +0000 (UTC) Received: from freefall.freebsd.org (localhost [127.0.0.1]) by freefall.freebsd.org (8.14.5/8.14.5) with ESMTP id q1KB7Ans090175 for ; Mon, 20 Feb 2012 11:07:10 GMT (envelope-from owner-bugmaster@FreeBSD.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.14.5/8.14.5/Submit) id q1KB79HK090173 for freebsd-mips@FreeBSD.org; Mon, 20 Feb 2012 11:07:09 GMT (envelope-from owner-bugmaster@FreeBSD.org) Date: Mon, 20 Feb 2012 11:07:09 GMT Message-Id: <201202201107.q1KB79HK090173@freefall.freebsd.org> X-Authentication-Warning: freefall.freebsd.org: gnats set sender to owner-bugmaster@FreeBSD.org using -f From: FreeBSD bugmaster To: freebsd-mips@FreeBSD.org Cc: Subject: Current problem reports assigned to freebsd-mips@FreeBSD.org X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Feb 2012 11:07:10 -0000 Note: to view an individual PR, use: http://www.freebsd.org/cgi/query-pr.cgi?pr=(number). The following is a listing of current problems submitted by FreeBSD users. These represent problem reports covering all versions including experimental development code and obsolete releases. S Tracker Resp. Description -------------------------------------------------------------------------------- o kern/163670 mips [mips][arge] arge can't allocate ring buffer on multip 1 problem total. From owner-freebsd-mips@FreeBSD.ORG Tue Feb 21 22:51:41 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 68850106566C for ; Tue, 21 Feb 2012 22:51:41 +0000 (UTC) (envelope-from pkelsey@gmail.com) Received: from mail-vx0-f182.google.com (mail-vx0-f182.google.com [209.85.220.182]) by mx1.freebsd.org (Postfix) with ESMTP id F32B38FC0C for ; Tue, 21 Feb 2012 22:51:40 +0000 (UTC) Received: by vcmm1 with SMTP id m1so6654151vcm.13 for ; Tue, 21 Feb 2012 14:51:40 -0800 (PST) Received-SPF: pass (google.com: domain of pkelsey@gmail.com designates 10.220.107.212 as permitted sender) client-ip=10.220.107.212; Authentication-Results: mr.google.com; spf=pass (google.com: domain of pkelsey@gmail.com designates 10.220.107.212 as permitted sender) smtp.mail=pkelsey@gmail.com; dkim=pass header.i=pkelsey@gmail.com Received: from mr.google.com ([10.220.107.212]) by 10.220.107.212 with SMTP id c20mr16803534vcp.26.1329864700320 (num_hops = 1); Tue, 21 Feb 2012 14:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:date:x-google-sender-auth:message-id:subject :from:to:content-type; bh=McF6fD0IJUQ2Xo0Z+sonh13KxOTeAbq85qiyYZGpjPQ=; b=VMFTxFYfODhmolP6B7i1dxb4sTr2RMsT5mpoUUzXxNypnvHGse5PeYO3PVHEPiPtqW Z4nUJHuMG+KwrbbKzRHHuwLIuZ+pVQxcjxUFcDTPG2Bb/VzlfYbxmLu86oozGT0xVYyk 6Tq1o/sDNJ9FK+eWM2P/hipw80O3to+GDkJKk= MIME-Version: 1.0 Received: by 10.220.107.212 with SMTP id c20mr13547181vcp.26.1329862946518; Tue, 21 Feb 2012 14:22:26 -0800 (PST) Sender: pkelsey@gmail.com Received: by 10.220.188.7 with HTTP; Tue, 21 Feb 2012 14:22:26 -0800 (PST) Date: Tue, 21 Feb 2012 17:22:26 -0500 X-Google-Sender-Auth: SVhAljisDkHd_Df4SLLq8uOOoiA Message-ID: From: Patrick Kelsey To: freebsd-mips@freebsd.org Content-Type: text/plain; charset=ISO-8859-1 X-Content-Filtered-By: Mailman/MimeDel 2.1.5 Subject: ar71xx SPI speed X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Feb 2012 22:51:41 -0000 Hi, I've been doing some SPI-related work on an AR7161-based board (MikroTik Routerboard RB450G, CPU @ 680 MHz, DDR @ 340 MHz, AHB @ 170 MHz), and I've noticed, via both software cyclecount and logic analyzer traces, that the SPI bus clock tops out in the neighborhood of 7 MHz or so. I can get a little more performance out of it if I manually unroll/debranch the loop in ar71xx_spi_txrx, but not terribly much. The (closed source) boot loader for this board manages something in the neighborhood of 8.5 MHz (perhaps due to not going through a bus abstraction layer in its code). 8MHz-ish does seem a bit lethargic for an SoC with otherwise fast moving parts, but I don't have any technical documentation on which to base a meaningful expectation. I'm wondering if anyone has had any experience with this SPI controller that either corroborates or contradicts this apparent speed limit. Thanks, Patrick From owner-freebsd-mips@FreeBSD.ORG Thu Feb 23 18:57:42 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 38A201065670 for ; Thu, 23 Feb 2012 18:57:42 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-we0-f182.google.com (mail-we0-f182.google.com [74.125.82.182]) by mx1.freebsd.org (Postfix) with ESMTP id AEC808FC18 for ; Thu, 23 Feb 2012 18:57:41 +0000 (UTC) Received: by werm13 with SMTP id m13so1471637wer.13 for ; Thu, 23 Feb 2012 10:57:40 -0800 (PST) Received-SPF: pass (google.com: domain of adrian.chadd@gmail.com designates 10.216.82.201 as permitted sender) client-ip=10.216.82.201; Authentication-Results: mr.google.com; spf=pass (google.com: domain of adrian.chadd@gmail.com designates 10.216.82.201 as permitted sender) smtp.mail=adrian.chadd@gmail.com; dkim=pass header.i=adrian.chadd@gmail.com Received: from mr.google.com ([10.216.82.201]) by 10.216.82.201 with SMTP id o51mr1568309wee.6.1330023460747 (num_hops = 1); Thu, 23 Feb 2012 10:57:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=c7Np4gG6jdTZzlKGm9bxse6Z74fh56cE/ABuXLKOFak=; b=SNRCqacupVvmert10aD7mLTiVlhHbQe4vKqM07TxDBzrOmEAvT+CnSmJ/0yXIUSR/X oV4ttrGXdA1fWpULWfxWWrbDMOQ46JMK14mTRCPTzMCY81WeopeHc8CDfMlm+APGqseP d07ljvxD189NM52fnsb5eMPsv0UlBDFfM8USg= MIME-Version: 1.0 Received: by 10.216.82.201 with SMTP id o51mr1281872wee.6.1330023460651; Thu, 23 Feb 2012 10:57:40 -0800 (PST) Sender: adrian.chadd@gmail.com Received: by 10.216.154.199 with HTTP; Thu, 23 Feb 2012 10:57:40 -0800 (PST) In-Reply-To: References: Date: Thu, 23 Feb 2012 10:57:40 -0800 X-Google-Sender-Auth: Wvc97hu-7r9TPEv1DP9j021Dd78 Message-ID: From: Adrian Chadd To: Patrick Kelsey Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-mips@freebsd.org Subject: Re: ar71xx SPI speed X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Feb 2012 18:57:42 -0000 Hi, If you take a look at the source code, IIRC reads are done via the hardware but the writes are done via bit banging. Are you looking at SPI read, SPI write, or a mix of both? You can increase the hardware SPI clock by correct fondling of the right registers but I haven't got any spare cycles to go grovelling through the AR7100 datasheet at the moment. Sorry. Poke me in a few days. Adrian On 21 February 2012 14:22, Patrick Kelsey wrote: > Hi, > > I've been doing some SPI-related work on an AR7161-based board (MikroTik > Routerboard RB450G, CPU @ 680 MHz, DDR @ 340 MHz, AHB @ 170 MHz), and I'v= e > noticed, via both software cyclecount and logic analyzer traces, that the > SPI bus clock tops out in the neighborhood of 7 MHz or so. =A0I can get a > little more performance out of it if I manually unroll/debranch the loop = in > ar71xx_spi_txrx, but not terribly much. =A0The (closed source) boot loade= r > for this board manages something in the neighborhood of 8.5 MHz (perhaps > due to not going through a bus abstraction layer in its code). =A08MHz-is= h > does seem a bit lethargic for an SoC with otherwise fast moving parts, bu= t > I don't have any technical documentation on which to base a meaningful > expectation. > > I'm wondering if anyone has had any experience with this SPI controller > that either corroborates or contradicts this apparent speed limit. > > Thanks, > Patrick > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to "freebsd-mips-unsubscribe@freebsd.org" From owner-freebsd-mips@FreeBSD.ORG Thu Feb 23 20:16:03 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B453E106567A for ; Thu, 23 Feb 2012 20:16:03 +0000 (UTC) (envelope-from pkelsey@gmail.com) Received: from mail-vw0-f54.google.com (mail-vw0-f54.google.com [209.85.212.54]) by mx1.freebsd.org (Postfix) with ESMTP id 51A028FC23 for ; Thu, 23 Feb 2012 20:16:02 +0000 (UTC) Received: by vbbfa15 with SMTP id fa15so1570859vbb.13 for ; Thu, 23 Feb 2012 12:16:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=TlA0vCumqSPuwUhK1k8yaxZfg7UazG2CB5weQ8hYodM=; b=q/5SPC/TnFy3u1+R3J96zh1Hp74OxdB2FnuhT/0O+sOgS3rvers2wtrTMfnBEQ1LSF uPn0N7E8KfUnwIhSbSby4pJA8lp47q7pQX+PsD55GdVegLNmYavtCBoj97A+fhVPleZ5 71aVgmZg1IjU1qopqyCVc1mqYg4sg2HO/QmoQ= MIME-Version: 1.0 Received: by 10.220.151.5 with SMTP id a5mr1644627vcw.8.1330028162487; Thu, 23 Feb 2012 12:16:02 -0800 (PST) Sender: pkelsey@gmail.com Received: by 10.220.188.7 with HTTP; Thu, 23 Feb 2012 12:16:02 -0800 (PST) In-Reply-To: References: Date: Thu, 23 Feb 2012 15:16:02 -0500 X-Google-Sender-Auth: _4jUvq8SgDIAjRVi_eu4IFGZWyM Message-ID: From: Patrick Kelsey To: Adrian Chadd Content-Type: text/plain; charset=ISO-8859-1 X-Content-Filtered-By: Mailman/MimeDel 2.1.5 Cc: freebsd-mips@freebsd.org Subject: Re: ar71xx SPI speed X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Feb 2012 20:16:03 -0000 On Thu, Feb 23, 2012 at 1:57 PM, Adrian Chadd wrote: > > If you take a look at the source code, IIRC reads are done via the > hardware but the writes are done via bit banging. > > Are you looking at SPI read, SPI write, or a mix of both? > > Yes, the writes are bitbanged out, and on each clock that is generated on the bus by a bit write, a read bit is clocked in. At the end of bitbanging a byte out, the accumulated read bits are retrieved from a register with one operation. I'm looking at the SPI bus itself and measuring the clock, which appears to be limited by the rate at which one can do the series of register writes involved in bitbanging each byte out. > You can increase the hardware SPI clock by correct fondling of the > right registers but I haven't got any spare cycles to go grovelling > through the AR7100 datasheet at the moment. Sorry. Poke me in a few > days. > > I have working code that correctly programs the clock divider in AR71XX_SPI_CTRL. When programmed for clock rates below about 7 MHz or so, the observed clock on the bus tracks with what I program in that register. Divider values that should result in something faster than about 7 MHz don't actually, I suppose because the SPI unit itself is on some slow secondary bus, or has internals running on a relatively slow derivative of the system clock. Not having a datasheet, one thing I'm wondering is if there is something configurable in the SoC clock tree that would allow the SPI unit register accesses to complete more quickly if they are in fact the limiting factor here. Thanks, Patrick