From owner-freebsd-mips@FreeBSD.ORG Sun Apr 15 22:32:58 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 717DE1065673 for ; Sun, 15 Apr 2012 22:32:58 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-pz0-f44.google.com (mail-pz0-f44.google.com [209.85.210.44]) by mx1.freebsd.org (Postfix) with ESMTP id 403008FC17 for ; Sun, 15 Apr 2012 22:32:58 +0000 (UTC) Received: by dadz14 with SMTP id z14so21184304dad.17 for ; Sun, 15 Apr 2012 15:32:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=TEvJ39gcasyyLYy27Mtnv+pwx4v+BiIVnStXWLUyls4=; b=q8KrfMUlfNKsHa32oczgrSdgezKxNhTmKPEHyqnYfMaC6yb+IJZMSp4wtUG0U8tig8 yR437Jr6qDYqgE5Ja88tl5LPN4XyBiF5Cll++MKtCSaaHm81u/sXmT6vvK5g96bJsSWR koccPMRknDR2AjpzxEzQg6fh7G2DUB26XlEAqmyQlsWeCeG/uHI4uHfBA7NTk2D0rRYG 9nSpTrB5pRg38mf3AsxQVp/60YoZ+DInHHDmJuccPPPkX92QUPM/wZ6Z4amTUmIo/6in Hq8pOGSfN1DB+/XCSFLKNjN9qCymTGuvPj4VxeK6Dj23CA7BfbeTvpqNCF9V6K9ULYKv 4BLw== MIME-Version: 1.0 Received: by 10.68.204.228 with SMTP id lb4mr22880041pbc.37.1334529177789; Sun, 15 Apr 2012 15:32:57 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.142.101.9 with HTTP; Sun, 15 Apr 2012 15:32:57 -0700 (PDT) In-Reply-To: References: Date: Sun, 15 Apr 2012 15:32:57 -0700 X-Google-Sender-Auth: 9TDySkkPsvNg1Jr6Rxi5UjbjIIM Message-ID: From: Adrian Chadd To: Patrick Kelsey Content-Type: text/plain; charset=ISO-8859-1 Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] MikroTik RB450G support X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Apr 2012 22:32:58 -0000 On 17 March 2012 00:28, Adrian Chadd wrote: > Hiya, > > I've added a new chip routine to set the MII clock. Chances are it > doesn't change between chipset revisions and if that's the case, I'll > go and update the ar724x/ar913x chipsets to do the same. > > Please use what I have and update your patch. let me know how it works > and we'll work on merging in some more stuff for you. :) Hi! The AR913x shares the same MII configuration as the AR71xx. However, the AR724x MII configuration is entirely different. I'll have to check each of the three chips. There's also the requirement to set the MII type rather than just the speed. It's easy for the AR71xx/AR913x, but the AR724x MII configuration is quite a bit different. There's also(!) PLL configuration stuff to sort out. Argh. Adrian