Date: Sun, 20 May 2012 03:23:35 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 211405 for review Message-ID: <201205200323.q4K3NZZh030445@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@211405?ac=10 Change 211405 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/05/20 03:23:02 Apply GNU assembler (gas) changes for CHERI instructions to the FreeBSD/cheri development tree -- obtained from Steven Murdoch. Both world and kernel appear to build just fine with this (not particularly surprising). Affected files ... .. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/gas/config/tc-mips.c#2 edit .. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/include/opcode/mips.h#2 edit .. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-dis.c#2 edit .. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-opc.c#2 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/gas/config/tc-mips.c#2 (text+ko) ==== @@ -1483,6 +1483,7 @@ #define RTYPE_PC 0x04000 #define RTYPE_ACC 0x08000 #define RTYPE_CCC 0x10000 +#define RTYPE_CAP 0x20000 #define RNUM_MASK 0x000ff #define RWARN 0x80000 @@ -1574,6 +1575,42 @@ {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} +#define CAPABILITY_REGISTER_NUMBERS \ + {"$c0", RTYPE_CAP | 0}, \ + {"$c1", RTYPE_CAP | 1}, \ + {"$c2", RTYPE_CAP | 2}, \ + {"$c3", RTYPE_CAP | 3}, \ + {"$c4", RTYPE_CAP | 4}, \ + {"$c5", RTYPE_CAP | 5}, \ + {"$c6", RTYPE_CAP | 6}, \ + {"$c7", RTYPE_CAP | 7}, \ + {"$c8", RTYPE_CAP | 8}, \ + {"$c9", RTYPE_CAP | 9}, \ + {"$c10", RTYPE_CAP | 10}, \ + {"$c11", RTYPE_CAP | 11}, \ + {"$c12", RTYPE_CAP | 12}, \ + {"$c13", RTYPE_CAP | 13}, \ + {"$c14", RTYPE_CAP | 14}, \ + {"$c15", RTYPE_CAP | 15}, \ + {"$c16", RTYPE_CAP | 16}, \ + {"$c17", RTYPE_CAP | 17}, \ + {"$c18", RTYPE_CAP | 18}, \ + {"$c19", RTYPE_CAP | 19}, \ + {"$c20", RTYPE_CAP | 20}, \ + {"$c21", RTYPE_CAP | 21}, \ + {"$c22", RTYPE_CAP | 22}, \ + {"$c23", RTYPE_CAP | 23}, \ + {"$c24", RTYPE_CAP | 24}, \ + {"$c25", RTYPE_CAP | 25}, \ + {"$c26", RTYPE_CAP | 26}, \ + {"$c27", RTYPE_CAP | 27}, \ + {"$c28", RTYPE_CAP | 28}, \ + {"$c29", RTYPE_CAP | 29}, \ + {"$c30", RTYPE_CAP | 30}, \ + {"$c31", RTYPE_CAP | 31} + +/* TODO: Add symbolic names */ + #define N32N64_SYMBOLIC_REGISTER_NAMES \ {"$a4", RTYPE_GP | 8}, \ {"$a5", RTYPE_GP | 9}, \ @@ -1681,13 +1718,14 @@ FPU_REGISTER_NAMES, FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES, + /* The $txx registers depends on the abi, these will be added later into the symbol table from one of the tables below once mips_abi is set after parsing of arguments from the command line. */ SYMBOLIC_REGISTER_NAMES, - + CAPABILITY_REGISTER_NUMBERS, MIPS16_SPECIAL_REGISTER_NAMES, MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, @@ -8376,6 +8414,7 @@ case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; + case 'b': USE_BITS (OP_MASK_RD, OP_SH_RD); break; case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; @@ -8384,9 +8423,12 @@ case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; case 'I': break; + case 'o': USE_BITS (OP_MASK_CDELTA, OP_SH_CDELTA); break; case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; + case 'v': USE_BITS (OP_MASK_FD, OP_SH_FD); break; + case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; default: as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), c, opc->name, opc->args); @@ -8430,6 +8472,7 @@ case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; case 'l': break; + case 'm': USE_BITS (OP_MASK_FD, OP_SH_FD); break; case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; @@ -8743,6 +8786,7 @@ } } + /* Parse argument list */ create_insn (ip, insn); insn_error = NULL; argnum = 1; @@ -9159,10 +9203,57 @@ s = expr_end; continue; + case 'o': + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + INSERT_OPERAND (CDELTA, *ip, imm_expr.X_add_number); + imm_expr.X_op = O_absent; + s = expr_end; + continue; + case 'T': /* Coprocessor register. */ /* +T is for disassembly only; never match. */ break; + /* Capability register number. */ + case 'w': + case 'b': + case 'v': + if (s[0] == '$' && s[1] == 'c' && ISDIGIT (s[2])) + { + c = *args; + ++s; + ++s; + regno = 0; + do + { + regno *= 10; + regno += *s - '0'; + ++s; + } + while (ISDIGIT (*s)); + if (regno > 31) + as_bad (_("Invalid register number (%d)"), regno); + else if (c == 'w') + { + INSERT_OPERAND (RT, *ip, regno); + continue; + } + else if (c == 'b') + { + INSERT_OPERAND (RD, *ip, regno); + continue; + } + else if (c == 'v') + { + INSERT_OPERAND (FD, *ip, regno); + continue; + } + } + else + as_bad (_("Invalid capability register number")); + break; + case 't': /* Coprocessor register number. */ if (s[0] == '$' && ISDIGIT (s[1])) { @@ -9377,6 +9468,7 @@ case 'd': /* destination register */ case 's': /* source register */ case 't': /* target register */ + case 'm': /* target register */ case 'r': /* both target and source */ case 'v': /* both dest and source */ case 'w': /* both dest and target */ @@ -9438,6 +9530,9 @@ case 'E': INSERT_OPERAND (RT, *ip, regno); break; + case 'm': + INSERT_OPERAND (FD, *ip, regno); + break; case 'x': /* This case exists because on the r3000 trunc expands into a macro which requires a gp ==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/include/opcode/mips.h#2 (text+ko) ==== @@ -102,6 +102,8 @@ #define OP_SH_IMMEDIATE 0 #define OP_MASK_DELTA 0xffff #define OP_SH_DELTA 0 +#define OP_MASK_CDELTA 0x7ff +#define OP_SH_CDELTA 0 #define OP_MASK_FUNCT 0x3f #define OP_SH_FUNCT 0 #define OP_MASK_SPEC 0x3f @@ -267,6 +269,7 @@ "j" 16 bit signed immediate (OP_*_DELTA) "k" 5 bit cache opcode in target register position (OP_*_CACHE) Also used for immediate operands in vr5400 vector insns. + "m" 5 bit target register (OP_*_FD) "o" 16 bit signed offset (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA) "q" 10 bit extra breakpoint code (OP_*_CODE2) @@ -307,6 +310,10 @@ "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). Requires that "+A" or "+E" occur first to set position. Enforces: 32 < (pos+size) <= 64. + "+w" 5 bit source or destination capability register (OP_*_RT) + "+b" 5 bit source or target capability register (OP_*_RD) + "+v" 5 bit target capability register (OP_*_FD) + "+o" 11 bit unsigned offset (OP_*_CDELTA) Floating point instructions: "D" 5 bit destination register (OP_*_FD) @@ -385,7 +392,7 @@ "234567890" "%[]<>(),+:'@!$*&^~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" - "abcdefghijklopqrstuvwxyz" + "abcdefghijklmopqrstuvwxyz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: ==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-dis.c#2 (text+ko) ==== @@ -899,6 +899,26 @@ break; } + case 'w': + (*info->fprintf_func) (info->stream, "c%d", (l >> OP_SH_RT) & + OP_MASK_RT); + break; + + case 'b': + (*info->fprintf_func) (info->stream, "c%d", (l >> OP_SH_RD) & + OP_MASK_RD); + break; + + case 'v': + (*info->fprintf_func) (info->stream, "c%d", (l >> OP_SH_FD) & + OP_MASK_FD); + break; + + case 'o': + delta = ((l >> OP_SH_CDELTA) & OP_MASK_CDELTA); + (*info->fprintf_func) (info->stream, "%d", delta); + break; + default: /* xgettext:c-format */ (*info->fprintf_func) (info->stream, @@ -1014,6 +1034,11 @@ mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); break; + case 'm': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); + break; + case 'i': case 'u': (*info->fprintf_func) (info->stream, "0x%lx", ==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-opc.c#2 (text+ko) ==== @@ -188,6 +188,43 @@ {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ +{"cgetbase","t,+b", 0x48000001, 0xffe007ff, 0, 0, I1 }, +{"cgetlen", "t,+b", 0x48000000, 0xffe007ff, 0, 0, I1 }, +{"cgetleng","t,+b", 0x48000000, 0xffe007ff, 0, 0, I1 }, +{"cgetperm","t,+b", 0x48000006, 0xffe007ff, 0, 0, I1 }, +{"cgettype","t,+b", 0x48000002, 0xffe007ff, 0, 0, I1 }, +{"csettype","+w,+b,m", 0x48800002, 0xffe0003f, 0, 0, I1 }, +{"cincbase","+w,+b,m", 0x48800001, 0xffe0003f, 0, 0, I1 }, +{"cmove", "+w,+b", 0x48800001, 0xffe007ff, 0, 0, I1 }, +{"csetlen", "+w,+b,m", 0x48800000, 0xffe0003f, 0, 0, I1 }, +{"cdeclen", "+w,+b,m", 0x48800000, 0xffe0003f, 0, 0, I1 }, /* DEPRECATED */ +{"cdecleng","+w,+b,m", 0x48800000, 0xffe0003f, 0, 0, I1 }, /* DEPRECATED */ +{"candperm","+w,+b,m", 0x48800006, 0xffe0003f, 0, 0, I1 }, +{"cscr", "+w,+b,m", 0x49200000, 0xffe0003f, 0, 0, I1 }, +{"clcr", "+w,+b,m", 0x49400000, 0xffe0003f, 0, 0, I1 }, +{"clb", "t,+b,+o", 0x4a000000, 0xffe00000, 0, 0, I1 }, +{"clh", "t,+b,+o", 0x4a200000, 0xffe00000, 0, 0, I1 }, +{"clw", "t,+b,+o", 0x4a400000, 0xffe00000, 0, 0, I1 }, +{"cld", "t,+b,+o", 0x4a600000, 0xffe00000, 0, 0, I1 }, +{"clbr", "t,+b,m", 0x4a800000, 0xffe0003f, 0, 0, I1 }, +{"clhr", "t,+b,m", 0x4aa00000, 0xffe0003f, 0, 0, I1 }, +{"clwr", "t,+b,m", 0x4ac00000, 0xffe0003f, 0, 0, I1 }, +{"cldr", "t,+b,m", 0x4ae00000, 0xffe0003f, 0, 0, I1 }, +{"csb", "t,+b,+o", 0x4b000000, 0xffe00000, 0, 0, I1 }, +{"csh", "t,+b,+o", 0x4b200000, 0xffe00000, 0, 0, I1 }, +{"csw", "t,+b,+o", 0x4b400000, 0xffe00000, 0, 0, I1 }, +{"csd", "t,+b,+o", 0x4b600000, 0xffe00000, 0, 0, I1 }, +{"csbr", "t,+b,m", 0x4b800000, 0xffe0003f, 0, 0, I1 }, +{"cshr", "t,+b,m", 0x4ba00000, 0xffe0003f, 0, 0, I1 }, +{"cswr", "t,+b,m", 0x4bc00000, 0xffe0003f, 0, 0, I1 }, +{"csdr", "t,+b,m", 0x4be00000, 0xffe0003f, 0, 0, I1 }, +{"cjr", "+b,m", 0x49000000, 0xffff003f, 0, 0, I1 }, +{"cjalr", "+b,m", 0x48e00000, 0xffff003f, 0, 0, I1 }, +{"csealcode","+w,+b", 0x48200000, 0xffe007ff, 0, 0, I1 }, +{"csealdata","+w,+b,+v",0x48400000, 0xffe0003f, 0, 0, I1 }, +{"cunseal", "+w,+b,+v", 0x48600000, 0xffe0003f, 0, 0, I1 }, +{"ccall", "+w,+b", 0x48a00000, 0xffe007ff, 0, 0, I1 }, +{"creturn", "", 0x48c00000, 0xffffffff, 0, 0, I1 }, {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
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