From owner-svn-src-vendor@freebsd.org Sun Feb 21 13:51:46 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id CB7F2AB087F; Sun, 21 Feb 2016 13:51:46 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 7065512AA; Sun, 21 Feb 2016 13:51:46 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1LDpjIx049388; Sun, 21 Feb 2016 13:51:45 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1LDphPK049366; Sun, 21 Feb 2016 13:51:43 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602211351.u1LDphPK049366@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sun, 21 Feb 2016 13:51:43 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r295846 - in vendor/llvm/dist: docs include/llvm/CodeGen include/llvm/IR lib/CodeGen lib/CodeGen/SelectionDAG lib/ExecutionEngine/IntelJITEvents lib/Support lib/Target/Sparc lib/Target/... X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Feb 2016 13:51:47 -0000 Author: dim Date: Sun Feb 21 13:51:43 2016 New Revision: 295846 URL: https://svnweb.freebsd.org/changeset/base/295846 Log: Vendor import of llvm release_38 branch r261369: https://llvm.org/svn/llvm-project/llvm/branches/release_38@261369 Added: vendor/llvm/dist/test/CodeGen/AArch64/fcopysign.ll vendor/llvm/dist/test/CodeGen/WinEH/wineh-noret-cleanup.ll vendor/llvm/dist/test/CodeGen/X86/pr26625.ll vendor/llvm/dist/test/CodeGen/X86/regalloc-spill-at-ehpad.ll vendor/llvm/dist/test/Transforms/PruneEH/pr26263.ll Deleted: vendor/llvm/dist/test/Transforms/LoopVectorize/X86/reg-usage.ll Modified: vendor/llvm/dist/docs/CMake.rst vendor/llvm/dist/docs/ReleaseNotes.rst vendor/llvm/dist/include/llvm/CodeGen/LiveInterval.h vendor/llvm/dist/include/llvm/IR/IRBuilder.h vendor/llvm/dist/include/llvm/IR/Instructions.h vendor/llvm/dist/lib/CodeGen/CalcSpillWeights.cpp vendor/llvm/dist/lib/CodeGen/LiveInterval.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp vendor/llvm/dist/lib/CodeGen/WinEHPrepare.cpp vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/CMakeLists.txt vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/LLVMBuild.txt vendor/llvm/dist/lib/Support/Triple.cpp vendor/llvm/dist/lib/Target/Sparc/SparcInstrAliases.td vendor/llvm/dist/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp vendor/llvm/dist/lib/Target/X86/X86FrameLowering.cpp vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td vendor/llvm/dist/lib/Transforms/IPO/PruneEH.cpp vendor/llvm/dist/lib/Transforms/Scalar/LoopStrengthReduce.cpp vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp vendor/llvm/dist/test/CodeGen/X86/shrink-wrap-chkstk.ll vendor/llvm/dist/test/MC/Sparc/sparc-ctrl-instructions.s vendor/llvm/dist/test/MC/Sparc/sparc64-ctrl-instructions.s vendor/llvm/dist/test/MC/X86/x86_nop.s vendor/llvm/dist/test/Transforms/InstCombine/fprintf-1.ll vendor/llvm/dist/test/Transforms/LoopStrengthReduce/funclet.ll vendor/llvm/dist/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll vendor/llvm/dist/test/Transforms/LoopVectorize/X86/vector_max_bandwidth.ll vendor/llvm/dist/test/Transforms/LoopVectorize/interleaved-accesses.ll Modified: vendor/llvm/dist/docs/CMake.rst ============================================================================== --- vendor/llvm/dist/docs/CMake.rst Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/docs/CMake.rst Sun Feb 21 13:51:43 2016 (r295846) @@ -197,12 +197,6 @@ CMake manual, or execute ``cmake --help- **CMAKE_CXX_FLAGS**:STRING Extra flags to use when compiling C++ source files. -**BUILD_SHARED_LIBS**:BOOL - Flag indicating if shared libraries will be built. Its default value is - OFF. This option is only recommended for use by LLVM developers. - On Windows, shared libraries may be used when building with MinGW, including - mingw-w64, but not when building with the Microsoft toolchain. - .. _LLVM-specific variables: LLVM-specific variables @@ -445,6 +439,30 @@ LLVM-specific variables $CMAKE_INSTALL_PREFIX/Toolchains containing an xctoolchain directory which can be used to override the default system tools. +**LLVM_BUILD_LLVM_DYLIB**:BOOL + If enabled, the target for building the libLLVM shared library is added. + This library contains all of LLVM's components in a single shared library. + Defaults to OFF. This cannot be used in conjunction with BUILD_SHARED_LIBS. + Tools will only be linked to the libLLVM shared library if LLVM_LINK_LLVM_DYLIB + is also ON. + The components in the library can be customised by setting LLVM_DYLIB_COMPONENTS + to a list of the desired components. + +**LLVM_LINK_LLVM_DYLIB**:BOOL + If enabled, tools will be linked with the libLLVM shared library. Defaults + to OFF. Setting LLVM_LINK_LLVM_DYLIB to ON also sets LLVM_BUILD_LLVM_DYLIB + to ON. + +**BUILD_SHARED_LIBS**:BOOL + Flag indicating if each LLVM component (e.g. Support) is built as a shared + library (ON) or as a static library (OFF). Its default value is OFF. On + Windows, shared libraries may be used when building with MinGW, including + mingw-w64, but not when building with the Microsoft toolchain. + + .. note:: BUILD_SHARED_LIBS is only recommended for use by LLVM developers. + If you want to build LLVM as a shared library, you should use the + ``LLVM_BUILD_LLVM_DYLIB`` option. + Executing the test suite ======================== Modified: vendor/llvm/dist/docs/ReleaseNotes.rst ============================================================================== --- vendor/llvm/dist/docs/ReleaseNotes.rst Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/docs/ReleaseNotes.rst Sun Feb 21 13:51:43 2016 (r295846) @@ -89,6 +89,30 @@ Non-comprehensive list of changes in thi the node ``N`` is guaranteed not to be the last in the list, it is safe to call ``&*++N->getIterator()`` directly. +* The `Kaleidoscope tutorials `_ have been updated to use + the ORC JIT APIs. + +* ORC now has a basic set of C bindings. + +* Optional support for linking clang and the LLVM tools with a single libLLVM + shared library. To enable this, pass ``-DLLVM_LINK_LLVM_DYLIB=ON`` to CMake. + See `Building LLVM with CMake`_ for more details. + +* The optimization to move the prologue and epilogue of functions in colder + code path (shrink-wrapping) is now enabled by default. + +* A new target-independent gcc-compatible emulated Thread Local Storage mode + is added. When ``-femultated-tls`` flag is used, all accesses to TLS + variables are converted to calls to ``__emutls_get_address`` in the runtime + library. + +* MSVC compatible exception handling has been completely overhauled. New + instructions have been introduced to facilitate this: + `New exception handling instructions `_. + While we have done our best to test this feature thoroughly, it would + not be completely surprising if there were a few lingering issues that + early adopters might bump into. + .. NOTE For small 1-3 sentence descriptions, just add an entry at the end of this list. If your description won't fit comfortably in one bullet @@ -115,7 +139,7 @@ Changes to the ARM Backends During this release the AArch64 target has: * Added support for more sanitizers (MSAN, TSAN) and made them compatible with - all VMA kernel configurations (kurrently tested on 39 and 42 bits). + all VMA kernel configurations (currently tested on 39 and 42 bits). * Gained initial LLD support in the new ELF back-end * Extended the Load/Store optimiser and cleaned up some of the bad decisions made earlier. @@ -218,9 +242,16 @@ Changes to the X86 Target * More efficient code for wide integer compares. (E.g. 64-bit compares on 32-bit targets.) -* Tail call support for ``thiscall``, ``stdcall`, ``vectorcall``, and +* Tail call support for ``thiscall``, ``stdcall``, ``vectorcall``, and ``fastcall`` functions. +Changes to the Hexagon Target +----------------------------- + +In addition to general code size and performance improvements, Hexagon target +now has basic support for Hexagon V60 architecture and Hexagon Vector +Extensions (HVX). + Changes to the AVR Target ------------------------- Modified: vendor/llvm/dist/include/llvm/CodeGen/LiveInterval.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/LiveInterval.h Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/include/llvm/CodeGen/LiveInterval.h Sun Feb 21 13:51:43 2016 (r295846) @@ -544,6 +544,11 @@ namespace llvm { return true; } + // Returns true if any segment in the live range contains any of the + // provided slot indexes. Slots which occur in holes between + // segments will not cause the function to return true. + bool isLiveAtIndexes(ArrayRef Slots) const; + bool operator<(const LiveRange& other) const { const SlotIndex &thisIndex = beginIndex(); const SlotIndex &otherIndex = other.beginIndex(); Modified: vendor/llvm/dist/include/llvm/IR/IRBuilder.h ============================================================================== --- vendor/llvm/dist/include/llvm/IR/IRBuilder.h Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/include/llvm/IR/IRBuilder.h Sun Feb 21 13:51:43 2016 (r295846) @@ -1539,16 +1539,7 @@ public: } CallInst *CreateCall(Value *Callee, ArrayRef Args = None, - ArrayRef OpBundles = None, const Twine &Name = "", MDNode *FPMathTag = nullptr) { - CallInst *CI = CallInst::Create(Callee, Args, OpBundles); - if (isa(CI)) - CI = cast(AddFPMathAttributes(CI, FPMathTag, FMF)); - return Insert(CI, Name); - } - - CallInst *CreateCall(Value *Callee, ArrayRef Args, - const Twine &Name, MDNode *FPMathTag = nullptr) { PointerType *PTy = cast(Callee->getType()); FunctionType *FTy = cast(PTy->getElementType()); return CreateCall(FTy, Callee, Args, Name, FPMathTag); @@ -1563,6 +1554,15 @@ public: return Insert(CI, Name); } + CallInst *CreateCall(Value *Callee, ArrayRef Args, + ArrayRef OpBundles, + const Twine &Name = "", MDNode *FPMathTag = nullptr) { + CallInst *CI = CallInst::Create(Callee, Args, OpBundles); + if (isa(CI)) + CI = cast(AddFPMathAttributes(CI, FPMathTag, FMF)); + return Insert(CI, Name); + } + CallInst *CreateCall(Function *Callee, ArrayRef Args, const Twine &Name = "", MDNode *FPMathTag = nullptr) { return CreateCall(Callee->getFunctionType(), Callee, Args, Name, FPMathTag); Modified: vendor/llvm/dist/include/llvm/IR/Instructions.h ============================================================================== --- vendor/llvm/dist/include/llvm/IR/Instructions.h Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/include/llvm/IR/Instructions.h Sun Feb 21 13:51:43 2016 (r295846) @@ -2512,6 +2512,14 @@ public: return block_begin() + getNumOperands(); } + iterator_range blocks() { + return make_range(block_begin(), block_end()); + } + + iterator_range blocks() const { + return make_range(block_begin(), block_end()); + } + op_range incoming_values() { return operands(); } const_op_range incoming_values() const { return operands(); } Modified: vendor/llvm/dist/lib/CodeGen/CalcSpillWeights.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/CalcSpillWeights.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/CodeGen/CalcSpillWeights.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -213,8 +213,11 @@ VirtRegAuxInfo::calculateSpillWeightAndH if (!Spillable) return; - // Mark li as unspillable if all live ranges are tiny. - if (li.isZeroLength(LIS.getSlotIndexes())) { + // Mark li as unspillable if all live ranges are tiny and the interval + // is not live at any reg mask. If the interval is live at a reg mask + // spilling may be required. + if (li.isZeroLength(LIS.getSlotIndexes()) && + !li.isLiveAtIndexes(LIS.getRegMaskSlots())) { li.markNotSpillable(); return; } Modified: vendor/llvm/dist/lib/CodeGen/LiveInterval.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/LiveInterval.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/CodeGen/LiveInterval.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -748,6 +748,40 @@ void LiveRange::flushSegmentSet() { verify(); } +bool LiveRange::isLiveAtIndexes(ArrayRef Slots) const { + ArrayRef::iterator SlotI = Slots.begin(); + ArrayRef::iterator SlotE = Slots.end(); + + // If there are no regmask slots, we have nothing to search. + if (SlotI == SlotE) + return false; + + // Start our search at the first segment that ends after the first slot. + const_iterator SegmentI = find(*SlotI); + const_iterator SegmentE = end(); + + // If there are no segments that end after the first slot, we're done. + if (SegmentI == SegmentE) + return false; + + // Look for each slot in the live range. + for ( ; SlotI != SlotE; ++SlotI) { + // Go to the next segment that ends after the current slot. + // The slot may be within a hole in the range. + SegmentI = advanceTo(SegmentI, *SlotI); + if (SegmentI == SegmentE) + return false; + + // If this segment contains the slot, we're done. + if (SegmentI->contains(*SlotI)) + return true; + // Otherwise, look for the next slot. + } + + // We didn't find a segment containing any of the slots. + return false; +} + void LiveInterval::freeSubRange(SubRange *S) { S->~SubRange(); // Memory was allocated with BumpPtr allocator and is not freed here. Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -1637,6 +1637,7 @@ struct FloatSignAsInt { MachinePointerInfo FloatPointerInfo; SDValue IntValue; APInt SignMask; + uint8_t SignBit; }; } @@ -1653,6 +1654,7 @@ void SelectionDAGLegalize::getSignAsIntV if (TLI.isTypeLegal(IVT)) { State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value); State.SignMask = APInt::getSignBit(NumBits); + State.SignBit = NumBits - 1; return; } @@ -1689,6 +1691,7 @@ void SelectionDAGLegalize::getSignAsIntV IntPtr, State.IntPointerInfo, MVT::i8, false, false, false, 0); State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7); + State.SignBit = 7; } /// Replace the integer value produced by getSignAsIntValue() with a new value @@ -1731,15 +1734,38 @@ SDValue SelectionDAGLegalize::ExpandFCOP return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue); } - // Transform values to integer, copy the sign bit and transform back. + // Transform Mag value to integer, and clear the sign bit. FloatSignAsInt MagAsInt; getSignAsIntValue(MagAsInt, DL, Mag); - assert(SignAsInt.SignMask == MagAsInt.SignMask); - SDValue ClearSignMask = DAG.getConstant(~SignAsInt.SignMask, DL, IntVT); - SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, MagAsInt.IntValue, + EVT MagVT = MagAsInt.IntValue.getValueType(); + SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT); + SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue, ClearSignMask); - SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit); + // Get the signbit at the right position for MagAsInt. + int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; + if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) { + if (ShiftAmount > 0) { + SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT); + SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst); + } else if (ShiftAmount < 0) { + SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT); + SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst); + } + SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit); + } else if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) { + SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); + if (ShiftAmount > 0) { + SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, MagVT); + SignBit = DAG.getNode(ISD::SRL, DL, MagVT, SignBit, ShiftCnst); + } else if (ShiftAmount < 0) { + SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, MagVT); + SignBit = DAG.getNode(ISD::SHL, DL, MagVT, SignBit, ShiftCnst); + } + } + + // Store the part with the modified sign and convert back to float. + SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit); return modifySignAsInt(MagAsInt, DL, CopiedSign); } Modified: vendor/llvm/dist/lib/CodeGen/WinEHPrepare.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/WinEHPrepare.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/CodeGen/WinEHPrepare.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -257,10 +257,14 @@ static void calculateCXXStateNumbers(Win if (auto *InnerCatchSwitch = dyn_cast(UserI)) if (InnerCatchSwitch->getUnwindDest() == CatchSwitch->getUnwindDest()) calculateCXXStateNumbers(FuncInfo, UserI, CatchLow); - if (auto *InnerCleanupPad = dyn_cast(UserI)) - if (getCleanupRetUnwindDest(InnerCleanupPad) == - CatchSwitch->getUnwindDest()) + if (auto *InnerCleanupPad = dyn_cast(UserI)) { + BasicBlock *UnwindDest = getCleanupRetUnwindDest(InnerCleanupPad); + // If a nested cleanup pad reports a null unwind destination and the + // enclosing catch pad doesn't it must be post-dominated by an + // unreachable instruction. + if (!UnwindDest || UnwindDest == CatchSwitch->getUnwindDest()) calculateCXXStateNumbers(FuncInfo, UserI, CatchLow); + } } } int CatchHigh = FuncInfo.getLastStateNumber(); @@ -360,10 +364,14 @@ static void calculateSEHStateNumbers(Win if (auto *InnerCatchSwitch = dyn_cast(UserI)) if (InnerCatchSwitch->getUnwindDest() == CatchSwitch->getUnwindDest()) calculateSEHStateNumbers(FuncInfo, UserI, ParentState); - if (auto *InnerCleanupPad = dyn_cast(UserI)) - if (getCleanupRetUnwindDest(InnerCleanupPad) == - CatchSwitch->getUnwindDest()) + if (auto *InnerCleanupPad = dyn_cast(UserI)) { + BasicBlock *UnwindDest = getCleanupRetUnwindDest(InnerCleanupPad); + // If a nested cleanup pad reports a null unwind destination and the + // enclosing catch pad doesn't it must be post-dominated by an + // unreachable instruction. + if (!UnwindDest || UnwindDest == CatchSwitch->getUnwindDest()) calculateSEHStateNumbers(FuncInfo, UserI, ParentState); + } } } else { auto *CleanupPad = cast(FirstNonPHI); Modified: vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/CMakeLists.txt ============================================================================== --- vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/CMakeLists.txt Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/CMakeLists.txt Sun Feb 21 13:51:43 2016 (r295846) @@ -1,8 +1,17 @@ include_directories( ${CMAKE_CURRENT_SOURCE_DIR}/.. ) +if( HAVE_LIBDL ) + set(LLVM_INTEL_JIT_LIBS ${CMAKE_DL_LIBS}) +endif() +if( HAVE_LIBPTHREAD ) + set(LLVM_INTEL_JIT_LIBS pthread ${LLVM_INTEL_JIT_LIBS}) +endif() + add_llvm_library(LLVMIntelJITEvents IntelJITEventListener.cpp jitprofiling.c - LINK_LIBS pthread ${CMAKE_DL_LIBS} + LINK_LIBS ${LLVM_INTEL_JIT_LIBS} ) + +add_dependencies(LLVMIntelJITEvents LLVMCodeGen) Modified: vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/LLVMBuild.txt ============================================================================== --- vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/LLVMBuild.txt Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/LLVMBuild.txt Sun Feb 21 13:51:43 2016 (r295846) @@ -21,4 +21,4 @@ type = OptionalLibrary name = IntelJITEvents parent = ExecutionEngine -required_libraries = Core DebugInfoDWARF Support Object ExecutionEngine +required_libraries = CodeGen Core DebugInfoDWARF Support Object ExecutionEngine Modified: vendor/llvm/dist/lib/Support/Triple.cpp ============================================================================== --- vendor/llvm/dist/lib/Support/Triple.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/Support/Triple.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -338,9 +338,9 @@ static Triple::ArchType parseArch(String // FIXME: Do we need to support these? .Cases("i786", "i886", "i986", Triple::x86) .Cases("amd64", "x86_64", "x86_64h", Triple::x86_64) - .Case("powerpc", Triple::ppc) - .Cases("powerpc64", "ppu", Triple::ppc64) - .Case("powerpc64le", Triple::ppc64le) + .Cases("powerpc", "ppc32", Triple::ppc) + .Cases("powerpc64", "ppu", "ppc64", Triple::ppc64) + .Cases("powerpc64le", "ppc64le", Triple::ppc64le) .Case("xscale", Triple::arm) .Case("xscaleeb", Triple::armeb) .Case("aarch64", Triple::aarch64) @@ -359,7 +359,7 @@ static Triple::ArchType parseArch(String .Case("r600", Triple::r600) .Case("amdgcn", Triple::amdgcn) .Case("hexagon", Triple::hexagon) - .Case("s390x", Triple::systemz) + .Cases("s390x", "systemz", Triple::systemz) .Case("sparc", Triple::sparc) .Case("sparcel", Triple::sparcel) .Cases("sparcv9", "sparc64", Triple::sparcv9) Modified: vendor/llvm/dist/lib/Target/Sparc/SparcInstrAliases.td ============================================================================== --- vendor/llvm/dist/lib/Target/Sparc/SparcInstrAliases.td Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/Target/Sparc/SparcInstrAliases.td Sun Feb 21 13:51:43 2016 (r295846) @@ -267,9 +267,9 @@ defm : int_cond_alias<"neg", 0b0110>; defm : int_cond_alias<"vc", 0b1111>; defm : int_cond_alias<"vs", 0b0111>; -defm : fp_cond_alias<"a", 0b0000>; -defm : fp_cond_alias<"", 0b0000>; // same as a; gnu asm, not in manual -defm : fp_cond_alias<"n", 0b1000>; +defm : fp_cond_alias<"a", 0b1000>; +defm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual +defm : fp_cond_alias<"n", 0b0000>; defm : fp_cond_alias<"u", 0b0111>; defm : fp_cond_alias<"g", 0b0110>; defm : fp_cond_alias<"ug", 0b0101>; Modified: vendor/llvm/dist/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -69,19 +69,15 @@ public: class X86AsmBackend : public MCAsmBackend { const StringRef CPU; bool HasNopl; - uint64_t MaxNopLength; + const uint64_t MaxNopLength; public: - X86AsmBackend(const Target &T, StringRef CPU) : MCAsmBackend(), CPU(CPU) { + X86AsmBackend(const Target &T, StringRef CPU) + : MCAsmBackend(), CPU(CPU), MaxNopLength(CPU == "slm" ? 7 : 15) { HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" && CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" && CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" && CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" && CPU != "c3" && CPU != "c3-2"; - // Max length of true long nop instruction is 15 bytes. - // Max length of long nop replacement instruction is 7 bytes. - // Taking into account SilverMont architecture features max length of nops - // is reduced for it to achieve better performance. - MaxNopLength = (!HasNopl || CPU == "slm") ? 7 : 15; } unsigned getNumFixupKinds() const override { @@ -299,7 +295,7 @@ void X86AsmBackend::relaxInstruction(con /// bytes. /// \return - true on success, false on failure bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { - static const uint8_t TrueNops[10][10] = { + static const uint8_t Nops[10][10] = { // nop {0x90}, // xchg %ax,%ax @@ -322,31 +318,17 @@ bool X86AsmBackend::writeNopData(uint64_ {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, }; - // Alternative nop instructions for CPUs which don't support long nops. - static const uint8_t AltNops[7][10] = { - // nop - {0x90}, - // xchg %ax,%ax - {0x66, 0x90}, - // lea 0x0(%esi),%esi - {0x8d, 0x76, 0x00}, - // lea 0x0(%esi),%esi - {0x8d, 0x74, 0x26, 0x00}, - // nop + lea 0x0(%esi),%esi - {0x90, 0x8d, 0x74, 0x26, 0x00}, - // lea 0x0(%esi),%esi - {0x8d, 0xb6, 0x00, 0x00, 0x00, 0x00 }, - // lea 0x0(%esi),%esi - {0x8d, 0xb4, 0x26, 0x00, 0x00, 0x00, 0x00}, - }; - - // Select the right NOP table. - // FIXME: Can we get if CPU supports long nops from the subtarget somehow? - const uint8_t (*Nops)[10] = HasNopl ? TrueNops : AltNops; - assert(HasNopl || MaxNopLength <= 7); + // This CPU doesn't support long nops. If needed add more. + // FIXME: Can we get this from the subtarget somehow? + // FIXME: We could generated something better than plain 0x90. + if (!HasNopl) { + for (uint64_t i = 0; i < Count; ++i) + OW->write8(0x90); + return true; + } - // Emit as many largest nops as needed, then emit a nop of the remaining - // length. + // 15 is the longest single nop instruction. Emit as many 15-byte nops as + // needed, then emit a nop of the remaining length. do { const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength); const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10; Modified: vendor/llvm/dist/lib/Target/X86/X86FrameLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86FrameLowering.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/Target/X86/X86FrameLowering.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -192,10 +192,9 @@ static unsigned findDeadCallerSavedReg(M return 0; } -static bool isEAXLiveIn(MachineFunction &MF) { - for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(), - EE = MF.getRegInfo().livein_end(); II != EE; ++II) { - unsigned Reg = II->first; +static bool isEAXLiveIn(MachineBasicBlock &MBB) { + for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) { + unsigned Reg = RegMask.PhysReg; if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX || Reg == X86::AH || Reg == X86::AL) @@ -261,7 +260,7 @@ void X86FrameLowering::emitSPUpdate(Mach // load the offset into a register and do one sub/add unsigned Reg = 0; - if (isSub && !isEAXLiveIn(*MBB.getParent())) + if (isSub && !isEAXLiveIn(MBB)) Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX); else Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit); @@ -1133,8 +1132,8 @@ void X86FrameLowering::emitPrologue(Mach if (IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF)) AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign); if (AlignedNumBytes >= StackProbeSize && UseStackProbe) { - // Check whether EAX is livein for this function. - bool isEAXAlive = isEAXLiveIn(MF); + // Check whether EAX is livein for this block. + bool isEAXAlive = isEAXLiveIn(MBB); if (isEAXAlive) { // Sanity check that EAX is not livein for this function. Modified: vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td Sun Feb 21 13:51:43 2016 (r295846) @@ -5896,7 +5896,7 @@ multiclass avx512_sqrt_scalar op def : Pat<(_.EltVT (OpNode (load addr:$src))), (!cast(NAME#SUFF#Zm) - (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>; + (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512, OptForSize]>; } multiclass avx512_sqrt_scalar_all opc, string OpcodeStr> { Modified: vendor/llvm/dist/lib/Transforms/IPO/PruneEH.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/IPO/PruneEH.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/Transforms/IPO/PruneEH.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -29,6 +29,7 @@ #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/LLVMContext.h" +#include "llvm/Transforms/Utils/Local.h" #include using namespace llvm; @@ -186,32 +187,8 @@ bool PruneEH::SimplifyFunction(Function for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) { if (InvokeInst *II = dyn_cast(BB->getTerminator())) if (II->doesNotThrow() && canSimplifyInvokeNoUnwind(F)) { - SmallVector Args(II->arg_begin(), II->arg_end()); - SmallVector OpBundles; - II->getOperandBundlesAsDefs(OpBundles); - - // Insert a call instruction before the invoke. - CallInst *Call = CallInst::Create(II->getCalledValue(), Args, OpBundles, - "", II); - Call->takeName(II); - Call->setCallingConv(II->getCallingConv()); - Call->setAttributes(II->getAttributes()); - Call->setDebugLoc(II->getDebugLoc()); - - // Anything that used the value produced by the invoke instruction - // now uses the value produced by the call instruction. Note that we - // do this even for void functions and calls with no uses so that the - // callgraph edge is updated. - II->replaceAllUsesWith(Call); BasicBlock *UnwindBlock = II->getUnwindDest(); - UnwindBlock->removePredecessor(II->getParent()); - - // Insert a branch to the normal destination right before the - // invoke. - BranchInst::Create(II->getNormalDest(), II); - - // Finally, delete the invoke instruction! - BB->getInstList().pop_back(); + removeUnwindEdge(&*BB); // If the unwind block is now dead, nuke it. if (pred_empty(UnwindBlock)) @@ -251,23 +228,39 @@ void PruneEH::DeleteBasicBlock(BasicBloc assert(pred_empty(BB) && "BB is not dead!"); CallGraph &CG = getAnalysis().getCallGraph(); + Instruction *TokenInst = nullptr; + CallGraphNode *CGN = CG[BB->getParent()]; for (BasicBlock::iterator I = BB->end(), E = BB->begin(); I != E; ) { --I; - if (CallInst *CI = dyn_cast(I)) { - if (!isa(I)) - CGN->removeCallEdgeFor(CI); - } else if (InvokeInst *II = dyn_cast(I)) - CGN->removeCallEdgeFor(II); + + if (I->getType()->isTokenTy()) { + TokenInst = &*I; + break; + } + + if (auto CS = CallSite (&*I)) { + const Function *Callee = CS.getCalledFunction(); + if (!Callee || !Intrinsic::isLeaf(Callee->getIntrinsicID())) + CGN->removeCallEdgeFor(CS); + else if (!Callee->isIntrinsic()) + CGN->removeCallEdgeFor(CS); + } + if (!I->use_empty()) I->replaceAllUsesWith(UndefValue::get(I->getType())); } - // Get the list of successors of this block. - std::vector Succs(succ_begin(BB), succ_end(BB)); + if (TokenInst) { + if (!isa(TokenInst)) + changeToUnreachable(TokenInst->getNextNode(), /*UseLLVMTrap=*/false); + } else { + // Get the list of successors of this block. + std::vector Succs(succ_begin(BB), succ_end(BB)); - for (unsigned i = 0, e = Succs.size(); i != e; ++i) - Succs[i]->removePredecessor(BB); + for (unsigned i = 0, e = Succs.size(); i != e; ++i) + Succs[i]->removePredecessor(BB); - BB->eraseFromParent(); + BB->eraseFromParent(); + } } Modified: vendor/llvm/dist/lib/Transforms/Scalar/LoopStrengthReduce.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/Scalar/LoopStrengthReduce.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/Transforms/Scalar/LoopStrengthReduce.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -4799,6 +4799,17 @@ LSRInstance::LSRInstance(Loop *L, IVUser DEBUG(dbgs() << "LSR skipping loop, too many IV Users in " << U << "\n"); return; } + // Bail out if we have a PHI on an EHPad that gets a value from a + // CatchSwitchInst. Because the CatchSwitchInst cannot be split, there is + // no good place to stick any instructions. + if (auto *PN = dyn_cast(U.getUser())) { + auto *FirstNonPHI = PN->getParent()->getFirstNonPHI(); + if (isa(FirstNonPHI) || + isa(FirstNonPHI)) + for (BasicBlock *PredBB : PN->blocks()) + if (isa(PredBB->getFirstNonPHI())) + return; + } } #ifndef NDEBUG Modified: vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp Sun Feb 21 13:49:26 2016 (r295845) +++ vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp Sun Feb 21 13:51:43 2016 (r295846) @@ -1409,14 +1409,15 @@ private: /// different operations. class LoopVectorizationCostModel { public: - LoopVectorizationCostModel(Loop *L, PredicatedScalarEvolution &PSE, - LoopInfo *LI, LoopVectorizationLegality *Legal, + LoopVectorizationCostModel(Loop *L, ScalarEvolution *SE, LoopInfo *LI, + LoopVectorizationLegality *Legal, const TargetTransformInfo &TTI, const TargetLibraryInfo *TLI, DemandedBits *DB, AssumptionCache *AC, const Function *F, - const LoopVectorizeHints *Hints) - : TheLoop(L), PSE(PSE), LI(LI), Legal(Legal), TTI(TTI), TLI(TLI), DB(DB), - AC(AC), TheFunction(F), Hints(Hints) {} + const LoopVectorizeHints *Hints, + SmallPtrSetImpl &ValuesToIgnore) + : TheLoop(L), SE(SE), LI(LI), Legal(Legal), TTI(TTI), TLI(TLI), DB(DB), + TheFunction(F), Hints(Hints), ValuesToIgnore(ValuesToIgnore) {} /// Information about vectorization costs struct VectorizationFactor { @@ -1464,9 +1465,6 @@ public: SmallVector calculateRegisterUsage(const SmallVector &VFs); - /// Collect values we want to ignore in the cost model. - void collectValuesToIgnore(); - private: /// Returns the expected execution cost. The unit of the cost does /// not matter because we use the 'cost' units to compare different @@ -1498,8 +1496,8 @@ public: /// The loop that we evaluate. Loop *TheLoop; - /// Predicated scalar evolution analysis. - PredicatedScalarEvolution &PSE; + /// Scev analysis. + ScalarEvolution *SE; /// Loop Info analysis. LoopInfo *LI; /// Vectorization legality. @@ -1508,17 +1506,13 @@ public: const TargetTransformInfo &TTI; /// Target Library Info. const TargetLibraryInfo *TLI; - /// Demanded bits analysis. + /// Demanded bits analysis DemandedBits *DB; - /// Assumption cache. - AssumptionCache *AC; const Function *TheFunction; - /// Loop Vectorize Hint. + // Loop Vectorize Hint. const LoopVectorizeHints *Hints; - /// Values to ignore in the cost model. - SmallPtrSet ValuesToIgnore; - /// Values to ignore in the cost model when VF > 1. - SmallPtrSet VecValuesToIgnore; + // Values to ignore in the cost model. + const SmallPtrSetImpl &ValuesToIgnore; }; /// \brief This holds vectorization requirements that must be verified late in @@ -1763,10 +1757,19 @@ struct LoopVectorize : public FunctionPa return false; } + // Collect values we want to ignore in the cost model. This includes + // type-promoting instructions we identified during reduction detection. + SmallPtrSet ValuesToIgnore; + CodeMetrics::collectEphemeralValues(L, AC, ValuesToIgnore); + for (auto &Reduction : *LVL.getReductionVars()) { + RecurrenceDescriptor &RedDes = Reduction.second; + SmallPtrSetImpl &Casts = RedDes.getCastInsts(); + ValuesToIgnore.insert(Casts.begin(), Casts.end()); + } + // Use the cost model. - LoopVectorizationCostModel CM(L, PSE, LI, &LVL, *TTI, TLI, DB, AC, F, - &Hints); - CM.collectValuesToIgnore(); + LoopVectorizationCostModel CM(L, PSE.getSE(), LI, &LVL, *TTI, TLI, DB, AC, + F, &Hints, ValuesToIgnore); // Check the function attributes to find out if this function should be // optimized for size. @@ -4636,6 +4639,8 @@ void InterleavedAccessInfo::analyzeInter // Holds all interleaved store groups temporarily. SmallSetVector StoreGroups; + // Holds all interleaved load groups temporarily. + SmallSetVector LoadGroups; // Search the load-load/write-write pair B-A in bottom-up order and try to // insert B into the interleave group of A according to 3 rules: @@ -4663,6 +4668,8 @@ void InterleavedAccessInfo::analyzeInter if (A->mayWriteToMemory()) StoreGroups.insert(Group); + else + LoadGroups.insert(Group); for (auto II = std::next(I); II != E; ++II) { Instruction *B = II->first; @@ -4710,6 +4717,12 @@ void InterleavedAccessInfo::analyzeInter for (InterleaveGroup *Group : StoreGroups) if (Group->getNumMembers() != Group->getFactor()) releaseGroup(Group); + + // Remove interleaved load groups that don't have the first and last member. + // This guarantees that we won't do speculative out of bounds loads. + for (InterleaveGroup *Group : LoadGroups) + if (!Group->getMember(0) || !Group->getMember(Group->getFactor() - 1)) + releaseGroup(Group); } LoopVectorizationCostModel::VectorizationFactor @@ -4734,7 +4747,7 @@ LoopVectorizationCostModel::selectVector } // Find the trip count. - unsigned TC = PSE.getSE()->getSmallConstantTripCount(TheLoop); + unsigned TC = SE->getSmallConstantTripCount(TheLoop); DEBUG(dbgs() << "LV: Found trip count: " << TC << '\n'); MinBWs = computeMinimumValueSizes(TheLoop->getBlocks(), *DB, &TTI); @@ -4936,7 +4949,7 @@ unsigned LoopVectorizationCostModel::sel return 1; // Do not interleave loops with a relatively small trip count. - unsigned TC = PSE.getSE()->getSmallConstantTripCount(TheLoop); + unsigned TC = SE->getSmallConstantTripCount(TheLoop); if (TC > 1 && TC < TinyTripCountInterleaveThreshold) return 1; @@ -5164,15 +5177,15 @@ LoopVectorizationCostModel::calculateReg // Ignore instructions that are never used within the loop. if (!Ends.count(I)) continue; + // Skip ignored values. + if (ValuesToIgnore.count(I)) + continue; + // Remove all of the instructions that end at this location. InstrList &List = TransposeEnds[i]; for (unsigned int j = 0, e = List.size(); j < e; ++j) OpenIntervals.erase(List[j]); - // Skip ignored values. - if (ValuesToIgnore.count(I)) - continue; - // For each VF find the maximum usage of registers. for (unsigned j = 0, e = VFs.size(); j < e; ++j) { if (VFs[j] == 1) { @@ -5182,12 +5195,8 @@ LoopVectorizationCostModel::calculateReg // Count the number of live intervals. unsigned RegUsage = 0; - for (auto Inst : OpenIntervals) { - // Skip ignored values for VF > 1. - if (VecValuesToIgnore.count(Inst)) - continue; + for (auto Inst : OpenIntervals) RegUsage += GetRegUsage(Inst->getType(), VFs[j]); - } MaxUsages[j] = std::max(MaxUsages[j], RegUsage); } @@ -5331,7 +5340,6 @@ LoopVectorizationCostModel::getInstructi if (VF > 1 && MinBWs.count(I)) RetTy = IntegerType::get(RetTy->getContext(), MinBWs[I]); Type *VectorTy = ToVectorTy(RetTy, VF); - auto SE = PSE.getSE(); // TODO: We need to estimate the cost of intrinsic calls. switch (I->getOpcode()) { @@ -5633,79 +5641,6 @@ bool LoopVectorizationCostModel::isConse return false; } -void LoopVectorizationCostModel::collectValuesToIgnore() { - // Ignore ephemeral values. - CodeMetrics::collectEphemeralValues(TheLoop, AC, ValuesToIgnore); - - // Ignore type-promoting instructions we identified during reduction - // detection. - for (auto &Reduction : *Legal->getReductionVars()) { - RecurrenceDescriptor &RedDes = Reduction.second; - SmallPtrSetImpl &Casts = RedDes.getCastInsts(); - VecValuesToIgnore.insert(Casts.begin(), Casts.end()); - } - - // Ignore induction phis that are only used in either GetElementPtr or ICmp - // instruction to exit loop. Induction variables usually have large types and - // can have big impact when estimating register usage. - // This is for when VF > 1. - for (auto &Induction : *Legal->getInductionVars()) { - auto *PN = Induction.first; - auto *UpdateV = PN->getIncomingValueForBlock(TheLoop->getLoopLatch()); - - // Check that the PHI is only used by the induction increment (UpdateV) or - // by GEPs. Then check that UpdateV is only used by a compare instruction or - // the loop header PHI. - // FIXME: Need precise def-use analysis to determine if this instruction - // variable will be vectorized. - if (std::all_of(PN->user_begin(), PN->user_end(), - [&](const User *U) -> bool { - return U == UpdateV || isa(U); - }) && - std::all_of(UpdateV->user_begin(), UpdateV->user_end(), - [&](const User *U) -> bool { - return U == PN || isa(U); - })) { - VecValuesToIgnore.insert(PN); - VecValuesToIgnore.insert(UpdateV); - } - } - - // Ignore instructions that will not be vectorized. - // This is for when VF > 1. - for (auto bb = TheLoop->block_begin(), be = TheLoop->block_end(); bb != be; - ++bb) { - for (auto &Inst : **bb) { - switch (Inst.getOpcode()) { - case Instruction::GetElementPtr: { - // Ignore GEP if its last operand is an induction variable so that it is - // a consecutive load/store and won't be vectorized as scatter/gather - // pattern. - - GetElementPtrInst *Gep = cast(&Inst); - unsigned NumOperands = Gep->getNumOperands(); - unsigned InductionOperand = getGEPInductionOperand(Gep); - bool GepToIgnore = true; - - // Check that all of the gep indices are uniform except for the - // induction operand. - for (unsigned i = 0; i != NumOperands; ++i) { - if (i != InductionOperand && - !PSE.getSE()->isLoopInvariant(PSE.getSCEV(Gep->getOperand(i)), - TheLoop)) { - GepToIgnore = false; - break; - } - } - - if (GepToIgnore) - VecValuesToIgnore.insert(&Inst); - break; - } - } - } - } -} void InnerLoopUnroller::scalarizeInstruction(Instruction *Instr, bool IfPredicateStore) { Added: vendor/llvm/dist/test/CodeGen/AArch64/fcopysign.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/CodeGen/AArch64/fcopysign.ll Sun Feb 21 13:51:43 2016 (r295846) @@ -0,0 +1,23 @@ +; RUN: llc -o - %s | FileCheck %s +; Check that selection dag legalization of fcopysign works in cases with +; different modes for the arguments. +target triple = "aarch64--" + +declare fp128 @llvm.copysign.f128(fp128, fp128) + +@val = global double zeroinitializer, align 8 + +; CHECK-LABEL: copysign0 +; CHECK: ldr [[REG:x[0-9]+]], [x8, :lo12:val] +; CHECK: and [[ANDREG:x[0-9]+]], [[REG]], #0x8000000000000000 +; CHECK: lsr x[[LSRREGNUM:[0-9]+]], [[ANDREG]], #56 +; CHECK: bfxil w[[LSRREGNUM]], w{{[0-9]+}}, #0, #7 +; CHECK: strb w[[LSRREGNUM]], +; CHECK: ldr q{{[0-9]+}}, +define fp128 @copysign0() { +entry: + %v = load double, double* @val, align 8 + %conv = fpext double %v to fp128 + %call = tail call fp128 @llvm.copysign.f128(fp128 0xL00000000000000007FFF000000000000, fp128 %conv) #2 + ret fp128 %call +} Added: vendor/llvm/dist/test/CodeGen/WinEH/wineh-noret-cleanup.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/CodeGen/WinEH/wineh-noret-cleanup.ll Sun Feb 21 13:51:43 2016 (r295846) @@ -0,0 +1,80 @@ +; RUN: sed -e s/.Cxx:// %s | llc -mtriple=x86_64-pc-windows-msvc | FileCheck %s --check-prefix=CXX +; RUN: sed -e s/.Seh:// %s | llc -mtriple=x86_64-pc-windows-msvc | FileCheck %s --check-prefix=SEH + +declare i32 @__CxxFrameHandler3(...) +declare i32 @__C_specific_handler(...) +declare void @dummy_filter() + +declare void @f(i32) + +;Cxx: define void @test() personality i32 (...)* @__CxxFrameHandler3 { +;Seh: define void @test() personality i32 (...)* @__C_specific_handler { +entry: + invoke void @f(i32 1) + to label %invoke.cont unwind label %catch.dispatch + +catch.dispatch: + %cs1 = catchswitch within none [label %catch.body] unwind label %catch.dispatch.2 + +catch.body: +;Cxx: %catch = catchpad within %cs1 [i8* null, i32 u0x40, i8* null] +;Seh: %catch = catchpad within %cs1 [void ()* @dummy_filter] + invoke void @f(i32 2) [ "funclet"(token %catch) ] + to label %unreachable unwind label %terminate + +terminate: + %cleanup = cleanuppad within %catch [] + call void @f(i32 3) [ "funclet"(token %cleanup) ] + unreachable + +unreachable: + unreachable + +invoke.cont: + ret void + +catch.dispatch.2: + %cs2 = catchswitch within none [label %catch.body.2] unwind to caller + +catch.body.2: +;Cxx: %catch2 = catchpad within %cs2 [i8* null, i32 u0x40, i8* null] +;Seh: %catch2 = catchpad within %cs2 [void ()* @dummy_filter] + unreachable +} + +; CXX-LABEL: test: +; CXX-LABEL: $ip2state$test: +; CXX-NEXT: .long .Lfunc_begin0@IMGREL +; CXX-NEXT: .long -1 +; CXX-NEXT: .long .Ltmp0@IMGREL+1 +; CXX-NEXT: .long 1 +; CXX-NEXT: .long .Ltmp1@IMGREL+1 +; CXX-NEXT: .long -1 +; CXX-NEXT: .long "?catch$3@?0?test@4HA"@IMGREL +; CXX-NEXT: .long 2 +; CXX-NEXT: .long .Ltmp2@IMGREL+1 +; CXX-NEXT: .long 3 +; CXX-NEXT: .long .Ltmp3@IMGREL+1 +; CXX-NEXT: .long 2 +; CXX-NEXT: .long "?catch$5@?0?test@4HA"@IMGREL +; CXX-NEXT: .long 4 + +; SEH-LABEL: test: +; SEH-LABEL: .Llsda_begin0: +; SEH-NEXT: .long .Ltmp0@IMGREL+1 +; SEH-NEXT: .long .Ltmp1@IMGREL+1 +; SEH-NEXT: .long dummy_filter@IMGREL +; SEH-NEXT: .long .LBB0_3@IMGREL *** DIFF OUTPUT TRUNCATED AT 1000 LINES *** From owner-svn-src-vendor@freebsd.org Sun Feb 21 13:52:13 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id A0F61AB08B9; Sun, 21 Feb 2016 13:52:13 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 54B14145D; Sun, 21 Feb 2016 13:52:13 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1LDqCCO051281; Sun, 21 Feb 2016 13:52:12 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1LDqCUW051280; Sun, 21 Feb 2016 13:52:12 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602211352.u1LDqCUW051280@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sun, 21 Feb 2016 13:52:12 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r295847 - vendor/llvm/llvm-release_38-r261369 X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Feb 2016 13:52:13 -0000 Author: dim Date: Sun Feb 21 13:52:12 2016 New Revision: 295847 URL: https://svnweb.freebsd.org/changeset/base/295847 Log: Tag llvm release_38 branch r261369. Added: vendor/llvm/llvm-release_38-r261369/ - copied from r295846, vendor/llvm/dist/ From owner-svn-src-vendor@freebsd.org Sun Feb 21 13:52:35 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8861BAB08F6; Sun, 21 Feb 2016 13:52:35 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 51FC21610; Sun, 21 Feb 2016 13:52:35 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1LDqYbE051350; Sun, 21 Feb 2016 13:52:34 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1LDqWYK051334; Sun, 21 Feb 2016 13:52:32 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602211352.u1LDqWYK051334@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sun, 21 Feb 2016 13:52:32 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r295848 - in vendor/clang/dist: docs lib/Basic lib/CodeGen lib/Driver lib/Format lib/Sema test/CodeGen test/CodeGenCXX test/Driver test/OpenMP unittests/Format X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Feb 2016 13:52:35 -0000 Author: dim Date: Sun Feb 21 13:52:32 2016 New Revision: 295848 URL: https://svnweb.freebsd.org/changeset/base/295848 Log: Vendor import of clang release_38 branch r261369: https://llvm.org/svn/llvm-project/cfe/branches/release_38@261369 Added: vendor/clang/dist/test/CodeGen/arm-vfp-asm-constraint.c (contents, props changed) vendor/clang/dist/test/CodeGenCXX/windows-on-arm-stack-probe-size.cpp (contents, props changed) Modified: vendor/clang/dist/docs/ReleaseNotes.rst vendor/clang/dist/lib/Basic/Targets.cpp vendor/clang/dist/lib/CodeGen/CGStmtOpenMP.cpp vendor/clang/dist/lib/CodeGen/TargetInfo.cpp vendor/clang/dist/lib/Driver/ToolChains.cpp vendor/clang/dist/lib/Driver/ToolChains.h vendor/clang/dist/lib/Format/ContinuationIndenter.cpp vendor/clang/dist/lib/Sema/SemaOpenMP.cpp vendor/clang/dist/test/Driver/freebsd.cpp vendor/clang/dist/test/OpenMP/for_ast_print.cpp vendor/clang/dist/test/OpenMP/for_lastprivate_codegen.cpp vendor/clang/dist/test/OpenMP/parallel_messages.cpp vendor/clang/dist/unittests/Format/FormatTest.cpp Modified: vendor/clang/dist/docs/ReleaseNotes.rst ============================================================================== --- vendor/clang/dist/docs/ReleaseNotes.rst Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/docs/ReleaseNotes.rst Sun Feb 21 13:52:32 2016 (r295848) @@ -39,12 +39,16 @@ Major New Features - Feature1... Improvements to Clang's diagnostics -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +----------------------------------- Clang's diagnostics are constantly being improved to catch more issues, explain them more clearly, and provide more accurate source information about them. The improvements since the 3.7 release include: +- ``-Wmicrosoft`` has been split into many targeted flags, so that projects can + choose to enable only a subset of these warnings. ``-Wno-microsoft`` still + disables all these warnings, and ``-Wmicrosoft`` still enables them all. + - ... New Compiler Flags @@ -140,7 +144,51 @@ Objective-C Language Changes in Clang OpenCL C Language Changes in Clang ---------------------------------- -... +Several OpenCL 2.0 features have been added, including: + +- Command-line option ``-std=CL2.0``. + +- Generic address space (``__generic``) along with new conversion rules + between different address spaces and default address space deduction. + +- Support for program scope variables with ``__global`` address space. + +- Pipe specifier was added (although no pipe functions are supported yet). + +- Atomic types: ``atomic_int``, ``atomic_uint``, ``atomic_long``, + ``atomic_ulong``, ``atomic_float``, ``atomic_double``, ``atomic_flag``, + ``atomic_intptr_t``, ``atomic_uintptr_t``, ``atomic_size_t``, + ``atomic_ptrdiff_t`` and their usage with C11 style builtin functions. + +- Image types: ``image2d_depth_t``, ``image2d_array_depth_t``, + ``image2d_msaa_t``, ``image2d_array_msaa_t``, ``image2d_msaa_depth_t``, + ``image2d_array_msaa_depth_t``. + +- Other types (for pipes and device side enqueue): ``clk_event_t``, + ``queue_t``, ``ndrange_t``, ``reserve_id_t``. + +Several additional features/bugfixes have been added to the previous standards: + +- A set of floating point arithmetic relaxation flags: ``-cl-no-signed-zeros``, + ``-cl-unsafe-math-optimizations``, ``-cl-finite-math-only``, + ``-cl-fast-relaxed-math``. + +- Added ``^^`` to the list of reserved operations. + +- Improved vector support and diagnostics. + +- Improved diagnostics for function pointers. + +CUDA Support in Clang +--------------------- +Clang has experimental support for end-to-end CUDA compilation now: + +- The driver now detects CUDA installation, creates host and device compilation + pipelines, links device-side code with appropriate CUDA bitcode and produces + single object file with host and GPU code. + +- Implemented target attribute-based function overloading which allows clang to + compile CUDA sources without splitting them into separate host/device TUs. Internal API Changes -------------------- @@ -220,7 +268,7 @@ Several new checks were added: ``-enable-checker optin.performance.Padding``. - The checks to detect misuse of ``_Nonnull`` type qualifiers as well as checks to detect misuse of Objective-C generics were added. -- The analyzer now has opt in checks to detect localization errors in Coca +- The analyzer now has opt in checks to detect localization errors in Cocoa applications. The checks warn about uses of non-localized ``NSStrings`` passed to UI methods expecting localized strings and on ``NSLocalizedString`` macros that are missing the comment argument. These can be enabled by passing Modified: vendor/clang/dist/lib/Basic/Targets.cpp ============================================================================== --- vendor/clang/dist/lib/Basic/Targets.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/lib/Basic/Targets.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -4915,8 +4915,8 @@ public: default: break; case 'l': // r0-r7 case 'h': // r8-r15 - case 'w': // VFP Floating point register single precision - case 'P': // VFP Floating point register double precision + case 't': // VFP Floating point register single precision + case 'w': // VFP Floating point register double precision Info.setAllowsRegister(); return true; case 'I': Modified: vendor/clang/dist/lib/CodeGen/CGStmtOpenMP.cpp ============================================================================== --- vendor/clang/dist/lib/CodeGen/CGStmtOpenMP.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/lib/CodeGen/CGStmtOpenMP.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -585,71 +585,48 @@ void CodeGenFunction::EmitOMPLastprivate EmitBlock(ThenBB); } llvm::DenseMap LoopCountersAndUpdates; - const Expr *LastIterVal = nullptr; - const Expr *IVExpr = nullptr; - const Expr *IncExpr = nullptr; if (auto *LoopDirective = dyn_cast(&D)) { - if (isOpenMPWorksharingDirective(D.getDirectiveKind())) { - LastIterVal = cast(cast( - LoopDirective->getUpperBoundVariable()) - ->getDecl()) - ->getAnyInitializer(); - IVExpr = LoopDirective->getIterationVariable(); - IncExpr = LoopDirective->getInc(); - auto IUpdate = LoopDirective->updates().begin(); - for (auto *E : LoopDirective->counters()) { - auto *D = cast(E)->getDecl()->getCanonicalDecl(); - LoopCountersAndUpdates[D] = *IUpdate; - ++IUpdate; - } + auto IC = LoopDirective->counters().begin(); + for (auto F : LoopDirective->finals()) { + auto *D = cast(*IC)->getDecl()->getCanonicalDecl(); + LoopCountersAndUpdates[D] = F; + ++IC; } } - { - llvm::DenseSet AlreadyEmittedVars; - bool FirstLCV = true; - for (const auto *C : D.getClausesOfKind()) { - auto IRef = C->varlist_begin(); - auto ISrcRef = C->source_exprs().begin(); - auto IDestRef = C->destination_exprs().begin(); - for (auto *AssignOp : C->assignment_ops()) { - auto *PrivateVD = cast(cast(*IRef)->getDecl()); - QualType Type = PrivateVD->getType(); - auto *CanonicalVD = PrivateVD->getCanonicalDecl(); - if (AlreadyEmittedVars.insert(CanonicalVD).second) { - // If lastprivate variable is a loop control variable for loop-based - // directive, update its value before copyin back to original - // variable. - if (auto *UpExpr = LoopCountersAndUpdates.lookup(CanonicalVD)) { - if (FirstLCV && LastIterVal) { - EmitAnyExprToMem(LastIterVal, EmitLValue(IVExpr).getAddress(), - IVExpr->getType().getQualifiers(), - /*IsInitializer=*/false); - EmitIgnoredExpr(IncExpr); - FirstLCV = false; - } - EmitIgnoredExpr(UpExpr); - } - auto *SrcVD = cast(cast(*ISrcRef)->getDecl()); - auto *DestVD = cast(cast(*IDestRef)->getDecl()); - // Get the address of the original variable. - Address OriginalAddr = GetAddrOfLocalVar(DestVD); - // Get the address of the private variable. - Address PrivateAddr = GetAddrOfLocalVar(PrivateVD); - if (auto RefTy = PrivateVD->getType()->getAs()) - PrivateAddr = + llvm::DenseSet AlreadyEmittedVars; + for (const auto *C : D.getClausesOfKind()) { + auto IRef = C->varlist_begin(); + auto ISrcRef = C->source_exprs().begin(); + auto IDestRef = C->destination_exprs().begin(); + for (auto *AssignOp : C->assignment_ops()) { + auto *PrivateVD = cast(cast(*IRef)->getDecl()); + QualType Type = PrivateVD->getType(); + auto *CanonicalVD = PrivateVD->getCanonicalDecl(); + if (AlreadyEmittedVars.insert(CanonicalVD).second) { + // If lastprivate variable is a loop control variable for loop-based + // directive, update its value before copyin back to original + // variable. + if (auto *UpExpr = LoopCountersAndUpdates.lookup(CanonicalVD)) + EmitIgnoredExpr(UpExpr); + auto *SrcVD = cast(cast(*ISrcRef)->getDecl()); + auto *DestVD = cast(cast(*IDestRef)->getDecl()); + // Get the address of the original variable. + Address OriginalAddr = GetAddrOfLocalVar(DestVD); + // Get the address of the private variable. + Address PrivateAddr = GetAddrOfLocalVar(PrivateVD); + if (auto RefTy = PrivateVD->getType()->getAs()) + PrivateAddr = Address(Builder.CreateLoad(PrivateAddr), getNaturalTypeAlignment(RefTy->getPointeeType())); - EmitOMPCopy(Type, OriginalAddr, PrivateAddr, DestVD, SrcVD, AssignOp); - } - ++IRef; - ++ISrcRef; - ++IDestRef; + EmitOMPCopy(Type, OriginalAddr, PrivateAddr, DestVD, SrcVD, AssignOp); } + ++IRef; + ++ISrcRef; + ++IDestRef; } } - if (IsLastIterCond) { + if (IsLastIterCond) EmitBlock(DoneBB, /*IsFinished=*/true); - } } void CodeGenFunction::EmitOMPReductionClauseInit( @@ -919,10 +896,6 @@ void CodeGenFunction::EmitOMPLoopBody(co // The end (updates/cleanups). EmitBlock(Continue.getBlock()); BreakContinueStack.pop_back(); - // TODO: Update lastprivates if the SeparateIter flag is true. - // This will be implemented in a follow-up OMPLastprivateClause patch, but - // result should be still correct without it, as we do not make these - // variables private yet. } void CodeGenFunction::EmitOMPInnerLoop( Modified: vendor/clang/dist/lib/CodeGen/TargetInfo.cpp ============================================================================== --- vendor/clang/dist/lib/CodeGen/TargetInfo.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/lib/CodeGen/TargetInfo.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -4868,9 +4868,6 @@ public: }; class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo { - void addStackProbeSizeTargetAttribute(const Decl *D, llvm::GlobalValue *GV, - CodeGen::CodeGenModule &CGM) const; - public: WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K) : ARMTargetCodeGenInfo(CGT, K) {} @@ -4879,18 +4876,6 @@ public: CodeGen::CodeGenModule &CGM) const override; }; -void WindowsARMTargetCodeGenInfo::addStackProbeSizeTargetAttribute( - const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { - if (!isa(D)) - return; - if (CGM.getCodeGenOpts().StackProbeSize == 4096) - return; - - llvm::Function *F = cast(GV); - F->addFnAttr("stack-probe-size", - llvm::utostr(CGM.getCodeGenOpts().StackProbeSize)); -} - void WindowsARMTargetCodeGenInfo::setTargetAttributes( const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM); Modified: vendor/clang/dist/lib/Driver/ToolChains.cpp ============================================================================== --- vendor/clang/dist/lib/Driver/ToolChains.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/lib/Driver/ToolChains.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -3108,6 +3108,22 @@ void FreeBSD::AddClangCXXStdlibIncludeAr } } +void FreeBSD::AddCXXStdlibLibArgs(const ArgList &Args, + ArgStringList &CmdArgs) const { + CXXStdlibType Type = GetCXXStdlibType(Args); + bool Profiling = Args.hasArg(options::OPT_pg); + + switch (Type) { + case ToolChain::CST_Libcxx: + CmdArgs.push_back(Profiling ? "-lc++_p" : "-lc++"); + break; + + case ToolChain::CST_Libstdcxx: + CmdArgs.push_back(Profiling ? "-lstdc++_p" : "-lstdc++"); + break; + } +} + Tool *FreeBSD::buildAssembler() const { return new tools::freebsd::Assembler(*this); } Modified: vendor/clang/dist/lib/Driver/ToolChains.h ============================================================================== --- vendor/clang/dist/lib/Driver/ToolChains.h Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/lib/Driver/ToolChains.h Sun Feb 21 13:52:32 2016 (r295848) @@ -722,6 +722,8 @@ public: void AddClangCXXStdlibIncludeArgs( const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; + void AddCXXStdlibLibArgs(const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const override; bool UseSjLjExceptions(const llvm::opt::ArgList &Args) const override; bool isPIEDefault() const override; Modified: vendor/clang/dist/lib/Format/ContinuationIndenter.cpp ============================================================================== --- vendor/clang/dist/lib/Format/ContinuationIndenter.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/lib/Format/ContinuationIndenter.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -182,7 +182,7 @@ bool ContinuationIndenter::mustBreak(con return true; unsigned NewLineColumn = getNewLineColumn(State); - if (Current.isMemberAccess() && + if (Current.isMemberAccess() && Style.ColumnLimit != 0 && State.Column + getLengthToNextOperator(Current) > Style.ColumnLimit && (State.Column > NewLineColumn || Current.NestingLevel < State.StartOfLineLevel)) Modified: vendor/clang/dist/lib/Sema/SemaOpenMP.cpp ============================================================================== --- vendor/clang/dist/lib/Sema/SemaOpenMP.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/lib/Sema/SemaOpenMP.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -634,7 +634,8 @@ DSAStackTy::DSAVarData DSAStackTy::getTo if (auto *CTD = CTSD->getSpecializedTemplate()) RD = CTD->getTemplatedDecl(); if (IsConstant && - !(SemaRef.getLangOpts().CPlusPlus && RD && RD->hasMutableFields())) { + !(SemaRef.getLangOpts().CPlusPlus && RD && RD->hasDefinition() && + RD->hasMutableFields())) { // Variables with const-qualified type having no mutable member may be // listed in a firstprivate clause, even if they are static data members. DSAVarData DVarTemp = hasDSA(D, MatchesAnyClause(OMPC_firstprivate), @@ -3204,7 +3205,7 @@ public: NewVD->setInitStyle(VD->getInitStyle()); NewVD->setExceptionVariable(VD->isExceptionVariable()); NewVD->setNRVOVariable(VD->isNRVOVariable()); - NewVD->setCXXForRangeDecl(VD->isInExternCXXContext()); + NewVD->setCXXForRangeDecl(VD->isCXXForRangeDecl()); NewVD->setConstexpr(VD->isConstexpr()); NewVD->setInitCapture(VD->isInitCapture()); NewVD->setPreviousDeclInSameBlockScope( @@ -3249,14 +3250,20 @@ OpenMPIterationSpaceChecker::BuildNumIte Expr *Lower = Transform.TransformExpr(LBExpr).get(); if (!Upper || !Lower) return nullptr; - Upper = SemaRef.PerformImplicitConversion(Upper, UBExpr->getType(), - Sema::AA_Converting, - /*AllowExplicit=*/true) - .get(); - Lower = SemaRef.PerformImplicitConversion(Lower, LBExpr->getType(), - Sema::AA_Converting, - /*AllowExplicit=*/true) - .get(); + if (!SemaRef.Context.hasSameType(Upper->getType(), UBExpr->getType())) { + Upper = SemaRef + .PerformImplicitConversion(Upper, UBExpr->getType(), + Sema::AA_Converting, + /*AllowExplicit=*/true) + .get(); + } + if (!SemaRef.Context.hasSameType(Lower->getType(), LBExpr->getType())) { + Lower = SemaRef + .PerformImplicitConversion(Lower, LBExpr->getType(), + Sema::AA_Converting, + /*AllowExplicit=*/true) + .get(); + } if (!Upper || !Lower) return nullptr; @@ -3283,14 +3290,18 @@ OpenMPIterationSpaceChecker::BuildNumIte return nullptr; // Upper - Lower [- 1] + Step - auto NewStep = Transform.TransformExpr(Step->IgnoreImplicit()); - if (NewStep.isInvalid()) - return nullptr; - NewStep = SemaRef.PerformImplicitConversion( - NewStep.get(), Step->IgnoreImplicit()->getType(), Sema::AA_Converting, - /*AllowExplicit=*/true); + auto *StepNoImp = Step->IgnoreImplicit(); + auto NewStep = Transform.TransformExpr(StepNoImp); if (NewStep.isInvalid()) return nullptr; + if (!SemaRef.Context.hasSameType(NewStep.get()->getType(), + StepNoImp->getType())) { + NewStep = SemaRef.PerformImplicitConversion( + NewStep.get(), StepNoImp->getType(), Sema::AA_Converting, + /*AllowExplicit=*/true); + if (NewStep.isInvalid()) + return nullptr; + } Diff = SemaRef.BuildBinOp(S, DefaultLoc, BO_Add, Diff.get(), NewStep.get()); if (!Diff.isUsable()) return nullptr; @@ -3301,14 +3312,17 @@ OpenMPIterationSpaceChecker::BuildNumIte return nullptr; // (Upper - Lower [- 1] + Step) / Step - NewStep = Transform.TransformExpr(Step->IgnoreImplicit()); - if (NewStep.isInvalid()) - return nullptr; - NewStep = SemaRef.PerformImplicitConversion( - NewStep.get(), Step->IgnoreImplicit()->getType(), Sema::AA_Converting, - /*AllowExplicit=*/true); + NewStep = Transform.TransformExpr(StepNoImp); if (NewStep.isInvalid()) return nullptr; + if (!SemaRef.Context.hasSameType(NewStep.get()->getType(), + StepNoImp->getType())) { + NewStep = SemaRef.PerformImplicitConversion( + NewStep.get(), StepNoImp->getType(), Sema::AA_Converting, + /*AllowExplicit=*/true); + if (NewStep.isInvalid()) + return nullptr; + } Diff = SemaRef.BuildBinOp(S, DefaultLoc, BO_Div, Diff.get(), NewStep.get()); if (!Diff.isUsable()) return nullptr; @@ -3324,10 +3338,12 @@ OpenMPIterationSpaceChecker::BuildNumIte bool IsSigned = UseVarType ? VarType->hasSignedIntegerRepresentation() : Type->hasSignedIntegerRepresentation(); Type = C.getIntTypeForBitwidth(NewSize, IsSigned); - Diff = SemaRef.PerformImplicitConversion( - Diff.get(), Type, Sema::AA_Converting, /*AllowExplicit=*/true); - if (!Diff.isUsable()) - return nullptr; + if (!SemaRef.Context.hasSameType(Diff.get()->getType(), Type)) { + Diff = SemaRef.PerformImplicitConversion( + Diff.get(), Type, Sema::AA_Converting, /*AllowExplicit=*/true); + if (!Diff.isUsable()) + return nullptr; + } } if (LimitedType) { unsigned NewSize = (C.getTypeSize(Type) > 32) ? 64 : 32; @@ -3340,10 +3356,12 @@ OpenMPIterationSpaceChecker::BuildNumIte QualType NewType = C.getIntTypeForBitwidth( NewSize, Type->hasSignedIntegerRepresentation() || C.getTypeSize(Type) < NewSize); - Diff = SemaRef.PerformImplicitConversion(Diff.get(), NewType, - Sema::AA_Converting, true); - if (!Diff.isUsable()) - return nullptr; + if (!SemaRef.Context.hasSameType(Diff.get()->getType(), NewType)) { + Diff = SemaRef.PerformImplicitConversion(Diff.get(), NewType, + Sema::AA_Converting, true); + if (!Diff.isUsable()) + return nullptr; + } } } @@ -3360,12 +3378,16 @@ Expr *OpenMPIterationSpaceChecker::Build auto NewUB = Transform.TransformExpr(UB); if (NewLB.isInvalid() || NewUB.isInvalid()) return Cond; - NewLB = SemaRef.PerformImplicitConversion(NewLB.get(), LB->getType(), - Sema::AA_Converting, - /*AllowExplicit=*/true); - NewUB = SemaRef.PerformImplicitConversion(NewUB.get(), UB->getType(), - Sema::AA_Converting, - /*AllowExplicit=*/true); + if (!SemaRef.Context.hasSameType(NewLB.get()->getType(), LB->getType())) { + NewLB = SemaRef.PerformImplicitConversion(NewLB.get(), LB->getType(), + Sema::AA_Converting, + /*AllowExplicit=*/true); + } + if (!SemaRef.Context.hasSameType(NewUB.get()->getType(), UB->getType())) { + NewUB = SemaRef.PerformImplicitConversion(NewUB.get(), UB->getType(), + Sema::AA_Converting, + /*AllowExplicit=*/true); + } if (NewLB.isInvalid() || NewUB.isInvalid()) return Cond; auto CondExpr = SemaRef.BuildBinOp( @@ -3373,9 +3395,11 @@ Expr *OpenMPIterationSpaceChecker::Build : (TestIsStrictOp ? BO_GT : BO_GE), NewLB.get(), NewUB.get()); if (CondExpr.isUsable()) { - CondExpr = SemaRef.PerformImplicitConversion( - CondExpr.get(), SemaRef.Context.BoolTy, /*Action=*/Sema::AA_Casting, - /*AllowExplicit=*/true); + if (!SemaRef.Context.hasSameType(CondExpr.get()->getType(), + SemaRef.Context.BoolTy)) + CondExpr = SemaRef.PerformImplicitConversion( + CondExpr.get(), SemaRef.Context.BoolTy, /*Action=*/Sema::AA_Casting, + /*AllowExplicit=*/true); } SemaRef.getDiagnostics().setSuppressAllDiagnostics(Suppress); // Otherwise use original loop conditon and evaluate it in runtime. @@ -3602,20 +3626,26 @@ static ExprResult BuildCounterInit(Sema ExprResult VarRef, ExprResult Start) { TransformToNewDefs Transform(SemaRef); // Build 'VarRef = Start. - auto NewStart = Transform.TransformExpr(Start.get()->IgnoreImplicit()); - if (NewStart.isInvalid()) - return ExprError(); - NewStart = SemaRef.PerformImplicitConversion( - NewStart.get(), Start.get()->IgnoreImplicit()->getType(), - Sema::AA_Converting, - /*AllowExplicit=*/true); + auto *StartNoImp = Start.get()->IgnoreImplicit(); + auto NewStart = Transform.TransformExpr(StartNoImp); if (NewStart.isInvalid()) return ExprError(); - NewStart = SemaRef.PerformImplicitConversion( - NewStart.get(), VarRef.get()->getType(), Sema::AA_Converting, - /*AllowExplicit=*/true); - if (!NewStart.isUsable()) - return ExprError(); + if (!SemaRef.Context.hasSameType(NewStart.get()->getType(), + StartNoImp->getType())) { + NewStart = SemaRef.PerformImplicitConversion( + NewStart.get(), StartNoImp->getType(), Sema::AA_Converting, + /*AllowExplicit=*/true); + if (NewStart.isInvalid()) + return ExprError(); + } + if (!SemaRef.Context.hasSameType(NewStart.get()->getType(), + VarRef.get()->getType())) { + NewStart = SemaRef.PerformImplicitConversion( + NewStart.get(), VarRef.get()->getType(), Sema::AA_Converting, + /*AllowExplicit=*/true); + if (!NewStart.isUsable()) + return ExprError(); + } auto Init = SemaRef.BuildBinOp(S, Loc, BO_Assign, VarRef.get(), NewStart.get()); @@ -3633,31 +3663,37 @@ static ExprResult BuildCounterUpdate(Sem !Step.isUsable()) return ExprError(); + auto *StepNoImp = Step.get()->IgnoreImplicit(); TransformToNewDefs Transform(SemaRef); - auto NewStep = Transform.TransformExpr(Step.get()->IgnoreImplicit()); - if (NewStep.isInvalid()) - return ExprError(); - NewStep = SemaRef.PerformImplicitConversion( - NewStep.get(), Step.get()->IgnoreImplicit()->getType(), - Sema::AA_Converting, - /*AllowExplicit=*/true); + auto NewStep = Transform.TransformExpr(StepNoImp); if (NewStep.isInvalid()) return ExprError(); + if (!SemaRef.Context.hasSameType(NewStep.get()->getType(), + StepNoImp->getType())) { + NewStep = SemaRef.PerformImplicitConversion( + NewStep.get(), StepNoImp->getType(), Sema::AA_Converting, + /*AllowExplicit=*/true); + if (NewStep.isInvalid()) + return ExprError(); + } ExprResult Update = SemaRef.BuildBinOp(S, Loc, BO_Mul, Iter.get(), NewStep.get()); if (!Update.isUsable()) return ExprError(); // Build 'VarRef = Start + Iter * Step'. - auto NewStart = Transform.TransformExpr(Start.get()->IgnoreImplicit()); - if (NewStart.isInvalid()) - return ExprError(); - NewStart = SemaRef.PerformImplicitConversion( - NewStart.get(), Start.get()->IgnoreImplicit()->getType(), - Sema::AA_Converting, - /*AllowExplicit=*/true); + auto *StartNoImp = Start.get()->IgnoreImplicit(); + auto NewStart = Transform.TransformExpr(StartNoImp); if (NewStart.isInvalid()) return ExprError(); + if (!SemaRef.Context.hasSameType(NewStart.get()->getType(), + StartNoImp->getType())) { + NewStart = SemaRef.PerformImplicitConversion( + NewStart.get(), StartNoImp->getType(), Sema::AA_Converting, + /*AllowExplicit=*/true); + if (NewStart.isInvalid()) + return ExprError(); + } Update = SemaRef.BuildBinOp(S, Loc, (Subtract ? BO_Sub : BO_Add), NewStart.get(), Update.get()); if (!Update.isUsable()) Added: vendor/clang/dist/test/CodeGen/arm-vfp-asm-constraint.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/clang/dist/test/CodeGen/arm-vfp-asm-constraint.c Sun Feb 21 13:52:32 2016 (r295848) @@ -0,0 +1,36 @@ +// REQUIRES: arm-registered-target +// RUN: %clang_cc1 -triple armv7-unknown-unknown -mfpmath vfp -emit-llvm -o - %s | FileCheck %s + +// CHECK-NOT: error: + +double fabs(double x) { // CHECK-LABEL: @fabs( + // CHECK: call double asm "vabs.f64 ${0:P}, ${1:P}", "=w,w"(double + __asm__("vabs.f64 %P0, %P1" + : "=w"(x) + : "w"(x)); + return x; +} + +float fabsf(float x) { // CHECK-LABEL: @fabsf( + // CHECK: call float asm "vabs.f32 $0, $1", "=t,t"(float + __asm__("vabs.f32 %0, %1" + : "=t"(x) + : "t"(x)); + return x; +} + +double sqrt(double x) { // CHECK-LABEL: @sqrt( + // CHECK: call double asm "vsqrt.f64 ${0:P}, ${1:P}", "=w,w"(double + __asm__("vsqrt.f64 %P0, %P1" + : "=w"(x) + : "w"(x)); + return x; +} + +float sqrtf(float x) { // CHECK-LABEL: @sqrtf( + // CHECK: call float asm "vsqrt.f32 $0, $1", "=t,t"(float + __asm__("vsqrt.f32 %0, %1" + : "=t"(x) + : "t"(x)); + return x; +} Added: vendor/clang/dist/test/CodeGenCXX/windows-on-arm-stack-probe-size.cpp ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/clang/dist/test/CodeGenCXX/windows-on-arm-stack-probe-size.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -0,0 +1,13 @@ +// RUN: %clang_cc1 -triple thumbv7--windows-msvc -S -emit-llvm -o - -x c++ %s | FileCheck %s +// RUN: %clang_cc1 -triple thumbv7--windows-itanium -fno-use-cxa-atexit -S -emit-llvm -o - -x c++ %s | FileCheck %s + +class C { +public: + ~C(); +}; + +static C sc; +void f(const C &ci) { sc = ci; } + +// CHECK: atexit + Modified: vendor/clang/dist/test/Driver/freebsd.cpp ============================================================================== --- vendor/clang/dist/test/Driver/freebsd.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/test/Driver/freebsd.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -2,5 +2,12 @@ // RUN: | FileCheck --check-prefix=CHECK-TEN %s // RUN: %clangxx %s -### -o %t.o -target amd64-unknown-freebsd9.2 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NINE %s -// CHECK-TEN: -lc++ -// CHECK-NINE: -lstdc++ +// CHECK-TEN: "-lc++" "-lm" +// CHECK-NINE: "-lstdc++" "-lm" + +// RUN: %clangxx %s -### -pg -o %t.o -target amd64-unknown-freebsd10.0 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-PG-TEN %s +// RUN: %clangxx %s -### -pg -o %t.o -target amd64-unknown-freebsd9.2 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-PG-NINE %s +// CHECK-PG-TEN: "-lc++_p" "-lm_p" +// CHECK-PG-NINE: "-lstdc++_p" "-lm_p" Modified: vendor/clang/dist/test/OpenMP/for_ast_print.cpp ============================================================================== --- vendor/clang/dist/test/OpenMP/for_ast_print.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/test/OpenMP/for_ast_print.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -68,6 +68,18 @@ int main(int argc, char **argv) { // CHECK-NEXT: for (int i = 0; i < 10; ++i) // CHECK-NEXT: for (int j = 0; j < 10; ++j) // CHECK-NEXT: foo(); + char buf[9] = "01234567"; + char *p, *q; +#pragma omp parallel +#pragma omp for + for (p = buf; p < &buf[8]; p++) + for (q = &buf[0]; q <= buf + 7; q++) + foo(); + // CHECK: #pragma omp parallel + // CHECK-NEXT: #pragma omp for + // CHECK-NEXT: for (p = buf; p < &buf[8]; p++) + // CHECK-NEXT: for (q = &buf[0]; q <= buf + 7; q++) + // CHECK-NEXT: foo(); return (tmain(argc) + tmain(argv[0][0])); } Modified: vendor/clang/dist/test/OpenMP/for_lastprivate_codegen.cpp ============================================================================== --- vendor/clang/dist/test/OpenMP/for_lastprivate_codegen.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/test/OpenMP/for_lastprivate_codegen.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -396,20 +396,9 @@ int main() { // CHECK: br i1 [[IS_LAST_ITER:%.+]], label %[[LAST_THEN:.+]], label %[[LAST_DONE:.+]] // CHECK: [[LAST_THEN]] -// Calculate last iter count -// CHECK: store i32 1, i32* [[OMP_IV]] -// CHECK: [[IV1_1:%.+]] = load i32, i32* [[OMP_IV]] -// CHECK-NEXT: [[CALC_I_2:%.+]] = add nsw i32 [[IV1_1]], 1 -// CHECK-NEXT: store i32 [[CALC_I_2]], i32* [[OMP_IV]] -// Actual copying. - -// original cnt=private_cnt; // Calculate private cnt value. -// CHECK: [[IV1_1:%.+]] = load i32, i32* [[OMP_IV]] -// CHECK: [[MUL:%.+]] = mul nsw i32 [[IV1_1]], 1 -// CHECK: [[ADD:%.+]] = add nsw i32 0, [[MUL]] -// CHECK: [[CONV:%.+]] = trunc i32 [[ADD]] to i8 -// CHECK: store i8 [[CONV]], i8* [[CNT_PRIV]] +// CHECK: store i8 2, i8* [[CNT_PRIV]] +// original cnt=private_cnt; // CHECK: [[CNT_VAL:%.+]] = load i8, i8* [[CNT_PRIV]], // CHECK: store i8 [[CNT_VAL]], i8* [[CNT]], Modified: vendor/clang/dist/test/OpenMP/parallel_messages.cpp ============================================================================== --- vendor/clang/dist/test/OpenMP/parallel_messages.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/test/OpenMP/parallel_messages.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -5,7 +5,12 @@ void foo() { #pragma omp parallel // expected-error {{unexpected OpenMP directive '#pragma omp parallel'}} +struct S; +S& bar(); int main(int argc, char **argv) { + S &s = bar(); + #pragma omp parallel + (void)&s; #pragma omp parallel { // expected-warning {{extra tokens at the end of '#pragma omp parallel' are ignored}} foo(); #pragma omp parallel ( // expected-warning {{extra tokens at the end of '#pragma omp parallel' are ignored}} Modified: vendor/clang/dist/unittests/Format/FormatTest.cpp ============================================================================== --- vendor/clang/dist/unittests/Format/FormatTest.cpp Sun Feb 21 13:52:12 2016 (r295847) +++ vendor/clang/dist/unittests/Format/FormatTest.cpp Sun Feb 21 13:52:32 2016 (r295848) @@ -6135,6 +6135,9 @@ TEST_F(FormatTest, FormatsArrays) { " .aaaaaaaaaaaaaaaaaaaaaa();"); verifyNoCrash("a[,Y?)]", getLLVMStyleWithColumns(10)); + + FormatStyle NoColumnLimit = getLLVMStyleWithColumns(0); + verifyFormat("aaaaa[bbbbbb].cccccc()", NoColumnLimit); } TEST_F(FormatTest, LineStartsWithSpecialCharacter) { From owner-svn-src-vendor@freebsd.org Sun Feb 21 13:52:53 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 63F6DAB093A; Sun, 21 Feb 2016 13:52:53 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 1C6D11827; Sun, 21 Feb 2016 13:52:53 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1LDqqub051404; Sun, 21 Feb 2016 13:52:52 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1LDqqBU051403; Sun, 21 Feb 2016 13:52:52 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602211352.u1LDqqBU051403@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sun, 21 Feb 2016 13:52:52 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r295849 - vendor/clang/clang-release_38-r261369 X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Feb 2016 13:52:53 -0000 Author: dim Date: Sun Feb 21 13:52:51 2016 New Revision: 295849 URL: https://svnweb.freebsd.org/changeset/base/295849 Log: Tag clang release_38 branch r261369. Added: vendor/clang/clang-release_38-r261369/ - copied from r295848, vendor/clang/dist/ From owner-svn-src-vendor@freebsd.org Sun Feb 21 13:53:14 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8FEBAAB0986; Sun, 21 Feb 2016 13:53:14 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 5121019AD; Sun, 21 Feb 2016 13:53:14 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1LDrDhP051468; Sun, 21 Feb 2016 13:53:13 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1LDrCIE051461; Sun, 21 Feb 2016 13:53:12 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602211353.u1LDrCIE051461@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sun, 21 Feb 2016 13:53:12 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r295850 - in vendor/compiler-rt/dist: lib/msan lib/sanitizer_common lib/tsan/go test/asan/TestCases test/tsan X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Feb 2016 13:53:14 -0000 Author: dim Date: Sun Feb 21 13:53:12 2016 New Revision: 295850 URL: https://svnweb.freebsd.org/changeset/base/295850 Log: Vendor import of compiler-rt release_38 branch r261369: https://llvm.org/svn/llvm-project/compiler-rt/branches/release_38@261369 Modified: vendor/compiler-rt/dist/lib/msan/msan_interceptors.cc vendor/compiler-rt/dist/lib/sanitizer_common/sanitizer_linux_libcdep.cc vendor/compiler-rt/dist/lib/tsan/go/buildgo.sh vendor/compiler-rt/dist/test/asan/TestCases/throw_catch.cc vendor/compiler-rt/dist/test/tsan/CMakeLists.txt vendor/compiler-rt/dist/test/tsan/ignore_lib0.cc vendor/compiler-rt/dist/test/tsan/printf-1.c Modified: vendor/compiler-rt/dist/lib/msan/msan_interceptors.cc ============================================================================== --- vendor/compiler-rt/dist/lib/msan/msan_interceptors.cc Sun Feb 21 13:52:51 2016 (r295849) +++ vendor/compiler-rt/dist/lib/msan/msan_interceptors.cc Sun Feb 21 13:53:12 2016 (r295850) @@ -1408,12 +1408,12 @@ int OnExit() { __msan_unpoison(ptr, size) #define COMMON_INTERCEPTOR_ENTER(ctx, func, ...) \ if (msan_init_is_running) return REAL(func)(__VA_ARGS__); \ + ENSURE_MSAN_INITED(); \ MSanInterceptorContext msan_ctx = {IsInInterceptorScope()}; \ ctx = (void *)&msan_ctx; \ (void)ctx; \ InterceptorScope interceptor_scope; \ - __msan_unpoison(__errno_location(), sizeof(int)); /* NOLINT */ \ - ENSURE_MSAN_INITED(); + __msan_unpoison(__errno_location(), sizeof(int)); /* NOLINT */ #define COMMON_INTERCEPTOR_DIR_ACQUIRE(ctx, path) \ do { \ } while (false) Modified: vendor/compiler-rt/dist/lib/sanitizer_common/sanitizer_linux_libcdep.cc ============================================================================== --- vendor/compiler-rt/dist/lib/sanitizer_common/sanitizer_linux_libcdep.cc Sun Feb 21 13:52:51 2016 (r295849) +++ vendor/compiler-rt/dist/lib/sanitizer_common/sanitizer_linux_libcdep.cc Sun Feb 21 13:53:12 2016 (r295850) @@ -222,6 +222,11 @@ uptr ThreadDescriptorSize() { char *end; int minor = internal_simple_strtoll(buf + 8, &end, 10); if (end != buf + 8 && (*end == '\0' || *end == '.')) { + int patch = 0; + if (*end == '.') + // strtoll will return 0 if no valid conversion could be performed + patch = internal_simple_strtoll(end + 1, nullptr, 10); + /* sizeof(struct pthread) values from various glibc versions. */ if (SANITIZER_X32) val = 1728; // Assume only one particular version for x32. @@ -235,9 +240,9 @@ uptr ThreadDescriptorSize() { val = FIRST_32_SECOND_64(1136, 1712); else if (minor == 10) val = FIRST_32_SECOND_64(1168, 1776); - else if (minor <= 12) + else if (minor == 11 || (minor == 12 && patch == 1)) val = FIRST_32_SECOND_64(1168, 2288); - else if (minor == 13) + else if (minor <= 13) val = FIRST_32_SECOND_64(1168, 2304); else val = FIRST_32_SECOND_64(1216, 2304); Modified: vendor/compiler-rt/dist/lib/tsan/go/buildgo.sh ============================================================================== --- vendor/compiler-rt/dist/lib/tsan/go/buildgo.sh Sun Feb 21 13:52:51 2016 (r295849) +++ vendor/compiler-rt/dist/lib/tsan/go/buildgo.sh Sun Feb 21 13:53:12 2016 (r295850) @@ -50,19 +50,20 @@ if [ "`uname -a | grep Linux`" != "" ]; ../../sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc " elif [ "`uname -a | grep FreeBSD`" != "" ]; then - SUFFIX="freebsd_amd64" - OSCFLAGS="-fno-strict-aliasing -fPIC -Werror" - OSLDFLAGS="-lpthread -fPIC -fpie" - SRCS=" - $SRCS - ../rtl/tsan_platform_linux.cc - ../../sanitizer_common/sanitizer_posix.cc - ../../sanitizer_common/sanitizer_posix_libcdep.cc - ../../sanitizer_common/sanitizer_procmaps_common.cc - ../../sanitizer_common/sanitizer_procmaps_freebsd.cc - ../../sanitizer_common/sanitizer_linux.cc - ../../sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc - " + SUFFIX="freebsd_amd64" + OSCFLAGS="-fno-strict-aliasing -fPIC -Werror" + OSLDFLAGS="-lpthread -fPIC -fpie" + SRCS=" + $SRCS + ../rtl/tsan_platform_linux.cc + ../../sanitizer_common/sanitizer_posix.cc + ../../sanitizer_common/sanitizer_posix_libcdep.cc + ../../sanitizer_common/sanitizer_procmaps_common.cc + ../../sanitizer_common/sanitizer_procmaps_freebsd.cc + ../../sanitizer_common/sanitizer_linux.cc + ../../sanitizer_common/sanitizer_linux_libcdep.cc + ../../sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc + " elif [ "`uname -a | grep Darwin`" != "" ]; then SUFFIX="darwin_amd64" OSCFLAGS="-fPIC -Wno-unused-const-variable -Wno-unknown-warning-option" Modified: vendor/compiler-rt/dist/test/asan/TestCases/throw_catch.cc ============================================================================== --- vendor/compiler-rt/dist/test/asan/TestCases/throw_catch.cc Sun Feb 21 13:52:51 2016 (r295849) +++ vendor/compiler-rt/dist/test/asan/TestCases/throw_catch.cc Sun Feb 21 13:53:12 2016 (r295850) @@ -1,8 +1,5 @@ // RUN: %clangxx_asan -O %s -o %t && %run %t -// Clang doesn't support exceptions on Windows yet. -// XFAIL: win32 - #include #include #include Modified: vendor/compiler-rt/dist/test/tsan/CMakeLists.txt ============================================================================== --- vendor/compiler-rt/dist/test/tsan/CMakeLists.txt Sun Feb 21 13:52:51 2016 (r295849) +++ vendor/compiler-rt/dist/test/tsan/CMakeLists.txt Sun Feb 21 13:53:12 2016 (r295850) @@ -47,6 +47,7 @@ if(COMPILER_RT_INCLUDE_TESTS) ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.in ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg) list(APPEND TSAN_TEST_DEPS TsanUnitTests) + list(APPEND TSAN_TESTSUITES ${CMAKE_CURRENT_BINARY_DIR}/Unit) endif() add_lit_testsuite(check-tsan "Running ThreadSanitizer tests" Modified: vendor/compiler-rt/dist/test/tsan/ignore_lib0.cc ============================================================================== --- vendor/compiler-rt/dist/test/tsan/ignore_lib0.cc Sun Feb 21 13:52:51 2016 (r295849) +++ vendor/compiler-rt/dist/test/tsan/ignore_lib0.cc Sun Feb 21 13:53:12 2016 (r295850) @@ -1,9 +1,9 @@ // RUN: %clangxx_tsan -O1 %s -DLIB -fPIC -fno-sanitize=thread -shared -o %T/libignore_lib0.so // RUN: %clangxx_tsan -O1 %s -L%T -lignore_lib0 -o %t // RUN: echo running w/o suppressions: -// RUN: LD_LIBRARY_PATH=%T${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH} %deflake %run %t | FileCheck %s --check-prefix=CHECK-NOSUPP +// RUN: env LD_LIBRARY_PATH=%T${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH} %deflake %run %t | FileCheck %s --check-prefix=CHECK-NOSUPP // RUN: echo running with suppressions: -// RUN: LD_LIBRARY_PATH=%T${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH} %env_tsan_opts=suppressions='%s.supp' %run %t 2>&1 | FileCheck %s --check-prefix=CHECK-WITHSUPP +// RUN: env LD_LIBRARY_PATH=%T${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH} %env_tsan_opts=suppressions='%s.supp' %run %t 2>&1 | FileCheck %s --check-prefix=CHECK-WITHSUPP // Tests that interceptors coming from a library specified in called_from_lib // suppression are ignored. Modified: vendor/compiler-rt/dist/test/tsan/printf-1.c ============================================================================== --- vendor/compiler-rt/dist/test/tsan/printf-1.c Sun Feb 21 13:52:51 2016 (r295849) +++ vendor/compiler-rt/dist/test/tsan/printf-1.c Sun Feb 21 13:53:12 2016 (r295850) @@ -1,6 +1,6 @@ // RUN: %clang_tsan -O2 %s -o %t -// RUN: ASAN_OPTIONS=check_printf=1 %run %t 2>&1 | FileCheck %s -// RUN: ASAN_OPTIONS=check_printf=0 %run %t 2>&1 | FileCheck %s +// RUN: %env_tsan_opts=check_printf=1 %run %t 2>&1 | FileCheck %s +// RUN: %env_tsan_opts=check_printf=0 %run %t 2>&1 | FileCheck %s // RUN: %run %t 2>&1 | FileCheck %s #include From owner-svn-src-vendor@freebsd.org Sun Feb 21 13:53:37 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8B395AB09EA; Sun, 21 Feb 2016 13:53:37 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 423761AEA; Sun, 21 Feb 2016 13:53:37 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1LDraOt051523; Sun, 21 Feb 2016 13:53:36 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1LDraP2051522; Sun, 21 Feb 2016 13:53:36 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602211353.u1LDraP2051522@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sun, 21 Feb 2016 13:53:36 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r295851 - vendor/compiler-rt/compiler-rt-release_38-r261369 X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Feb 2016 13:53:37 -0000 Author: dim Date: Sun Feb 21 13:53:36 2016 New Revision: 295851 URL: https://svnweb.freebsd.org/changeset/base/295851 Log: Tag compiler-rt release_38 branch r261369. Added: vendor/compiler-rt/compiler-rt-release_38-r261369/ - copied from r295850, vendor/compiler-rt/dist/ From owner-svn-src-vendor@freebsd.org Sun Feb 21 13:54:01 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 55FF2AB0A33; Sun, 21 Feb 2016 13:54:01 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 30D171C90; Sun, 21 Feb 2016 13:54:01 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1LDs08m051587; Sun, 21 Feb 2016 13:54:00 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1LDs0Ka051581; Sun, 21 Feb 2016 13:54:00 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602211354.u1LDs0Ka051581@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sun, 21 Feb 2016 13:54:00 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r295852 - in vendor/libc++/dist: include test/std/re/re.regex/re.regex.construct test/std/re/re.results/re.results.form X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Feb 2016 13:54:01 -0000 Author: dim Date: Sun Feb 21 13:53:59 2016 New Revision: 295852 URL: https://svnweb.freebsd.org/changeset/base/295852 Log: Vendor import of libc++ release_38 branch r261369: https://llvm.org/svn/llvm-project/libcxx/branches/release_38@261369 Modified: vendor/libc++/dist/include/regex vendor/libc++/dist/test/std/re/re.regex/re.regex.construct/bad_escape.pass.cpp vendor/libc++/dist/test/std/re/re.results/re.results.form/form1.pass.cpp Modified: vendor/libc++/dist/include/regex ============================================================================== --- vendor/libc++/dist/include/regex Sun Feb 21 13:53:36 2016 (r295851) +++ vendor/libc++/dist/include/regex Sun Feb 21 13:53:59 2016 (r295852) @@ -976,7 +976,12 @@ public: typedef locale locale_type; typedef ctype_base::mask char_class_type; +#if defined(__mips__) && defined(__GLIBC__) + static const char_class_type __regex_word = static_cast(_ISbit(15)); +#else static const char_class_type __regex_word = 0x80; +#endif + private: locale __loc_; const ctype* __ct_; @@ -4265,6 +4270,9 @@ basic_regex<_CharT, _Traits>::__parse_at if (__first != __last && *__first == '\\') { _ForwardIterator __t1 = _VSTD::next(__first); + if (__t1 == __last) + __throw_regex_error(); + _ForwardIterator __t2 = __parse_decimal_escape(__t1, __last); if (__t2 != __t1) __first = __t2; @@ -5384,8 +5392,8 @@ match_results<_BidirectionalIterator, _A if ('0' <= *__fmt_first && *__fmt_first <= '9') { size_t __i = *__fmt_first - '0'; - __out = _VSTD::copy(__matches_[__i].first, - __matches_[__i].second, __out); + __out = _VSTD::copy((*this)[__i].first, + (*this)[__i].second, __out); } else { @@ -5436,8 +5444,8 @@ match_results<_BidirectionalIterator, _A ++__fmt_first; __i = 10 * __i + *__fmt_first - '0'; } - __out = _VSTD::copy(__matches_[__i].first, - __matches_[__i].second, __out); + __out = _VSTD::copy((*this)[__i].first, + (*this)[__i].second, __out); } else { Modified: vendor/libc++/dist/test/std/re/re.regex/re.regex.construct/bad_escape.pass.cpp ============================================================================== --- vendor/libc++/dist/test/std/re/re.regex/re.regex.construct/bad_escape.pass.cpp Sun Feb 21 13:53:36 2016 (r295851) +++ vendor/libc++/dist/test/std/re/re.regex/re.regex.construct/bad_escape.pass.cpp Sun Feb 21 13:53:59 2016 (r295852) @@ -33,6 +33,7 @@ int main() { assert(error_escape_thrown("[\\a]")); assert(error_escape_thrown("\\a")); + assert(error_escape_thrown("\\")); assert(error_escape_thrown("[\\e]")); assert(error_escape_thrown("\\e")); Modified: vendor/libc++/dist/test/std/re/re.results/re.results.form/form1.pass.cpp ============================================================================== --- vendor/libc++/dist/test/std/re/re.results/re.results.form/form1.pass.cpp Sun Feb 21 13:53:36 2016 (r295851) +++ vendor/libc++/dist/test/std/re/re.results/re.results.form/form1.pass.cpp Sun Feb 21 13:53:59 2016 (r295852) @@ -38,6 +38,31 @@ int main() { std::match_results m; const char s[] = "abcdefghijk"; + assert(std::regex_search(s, m, std::regex("cd((e)fg)hi", + std::regex_constants::nosubs))); + + char out[100] = {0}; + const char fmt[] = "prefix: $`, match: $&, suffix: $', m[1]: $1, m[2]: $2"; + char* r = m.format(output_iterator(out), + fmt, fmt + std::char_traits::length(fmt)).base(); + assert(r == out + 54); + assert(std::string(out) == "prefix: ab, match: cdefghi, suffix: jk, m[1]: , m[2]: "); + } + { + std::match_results m; + const char s[] = "abcdefghijk"; + assert(std::regex_search(s, m, std::regex("cdefghi"))); + + char out[100] = {0}; + const char fmt[] = "prefix: $`, match: $&, suffix: $', m[1]: $1, m[2]: $2"; + char* r = m.format(output_iterator(out), + fmt, fmt + std::char_traits::length(fmt)).base(); + assert(r == out + 54); + assert(std::string(out) == "prefix: ab, match: cdefghi, suffix: jk, m[1]: , m[2]: "); + } + { + std::match_results m; + const char s[] = "abcdefghijk"; assert(std::regex_search(s, m, std::regex("cd((e)fg)hi"))); char out[100] = {0}; @@ -61,6 +86,33 @@ int main() assert(r == out + 34); assert(std::string(out) == "match: cdefghi, m[1]: efg, m[2]: e"); } + { + std::match_results m; + const char s[] = "abcdefghijk"; + assert(std::regex_search(s, m, std::regex("cd((e)fg)hi", + std::regex_constants::nosubs))); + + char out[100] = {0}; + const char fmt[] = "match: &, m[1]: \\1, m[2]: \\2"; + char* r = m.format(output_iterator(out), + fmt, fmt + std::char_traits::length(fmt), + std::regex_constants::format_sed).base(); + assert(r == out + 30); + assert(std::string(out) == "match: cdefghi, m[1]: , m[2]: "); + } + { + std::match_results m; + const char s[] = "abcdefghijk"; + assert(std::regex_search(s, m, std::regex("cdefghi"))); + + char out[100] = {0}; + const char fmt[] = "match: &, m[1]: \\1, m[2]: \\2"; + char* r = m.format(output_iterator(out), + fmt, fmt + std::char_traits::length(fmt), + std::regex_constants::format_sed).base(); + assert(r == out + 30); + assert(std::string(out) == "match: cdefghi, m[1]: , m[2]: "); + } { std::match_results m; From owner-svn-src-vendor@freebsd.org Sun Feb 21 13:54:23 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 790DFAB0A7F; Sun, 21 Feb 2016 13:54:23 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 309AA1DC8; Sun, 21 Feb 2016 13:54:23 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1LDsMnW051642; Sun, 21 Feb 2016 13:54:22 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1LDsMIl051641; Sun, 21 Feb 2016 13:54:22 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602211354.u1LDsMIl051641@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sun, 21 Feb 2016 13:54:22 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r295853 - vendor/libc++/libc++-release_38-r261369 X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Feb 2016 13:54:23 -0000 Author: dim Date: Sun Feb 21 13:54:22 2016 New Revision: 295853 URL: https://svnweb.freebsd.org/changeset/base/295853 Log: Tag libc++ release_38 branch r261369. Added: vendor/libc++/libc++-release_38-r261369/ - copied from r295852, vendor/libc++/dist/ From owner-svn-src-vendor@freebsd.org Tue Feb 23 07:04:56 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id F3F7AAB15F1; Tue, 23 Feb 2016 07:04:55 +0000 (UTC) (envelope-from delphij@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C36D21D99; Tue, 23 Feb 2016 07:04:55 +0000 (UTC) (envelope-from delphij@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1N74sqU081140; Tue, 23 Feb 2016 07:04:54 GMT (envelope-from delphij@FreeBSD.org) Received: (from delphij@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1N74s94081139; Tue, 23 Feb 2016 07:04:54 GMT (envelope-from delphij@FreeBSD.org) Message-Id: <201602230704.u1N74s94081139@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: delphij set sender to delphij@FreeBSD.org using -f From: Xin LI Date: Tue, 23 Feb 2016 07:04:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r295913 - vendor/libarchive/dist/libarchive X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Feb 2016 07:04:56 -0000 Author: delphij Date: Tue Feb 23 07:04:54 2016 New Revision: 295913 URL: https://svnweb.freebsd.org/changeset/base/295913 Log: Apply upstream commit 6e06b1c8 (partial, by kientzle): Fix a potential crash issue discovered by Alexander Cherepanov: It seems bsdtar automatically handles stacked compression. This is a nice feature but it could be problematic when it's completely unlimited. Most clearly it's illustrated with quines: $ curl -sRO http://www.maximumcompression.com/selfgz.gz $ (ulimit -v 10000000 && bsdtar -tvf selfgz.gz) bsdtar: Error opening archive: Can't allocate data for gzip decompression Without ulimit, bsdtar will eat all available memory. This could also be a problem for other applications using libarchive. Modified: vendor/libarchive/dist/libarchive/archive_read.c Modified: vendor/libarchive/dist/libarchive/archive_read.c ============================================================================== --- vendor/libarchive/dist/libarchive/archive_read.c Tue Feb 23 06:29:57 2016 (r295912) +++ vendor/libarchive/dist/libarchive/archive_read.c Tue Feb 23 07:04:54 2016 (r295913) @@ -544,13 +544,13 @@ archive_read_open1(struct archive *_a) static int choose_filters(struct archive_read *a) { - int number_bidders, i, bid, best_bid; + int number_bidders, i, bid, best_bid, n; struct archive_read_filter_bidder *bidder, *best_bidder; struct archive_read_filter *filter; ssize_t avail; int r; - for (;;) { + for (n = 0; n < 25; ++n) { number_bidders = sizeof(a->bidders) / sizeof(a->bidders[0]); best_bid = 0; @@ -596,6 +596,9 @@ choose_filters(struct archive_read *a) return (ARCHIVE_FATAL); } } + archive_set_error(&a->archive, ARCHIVE_ERRNO_FILE_FORMAT, + "Input requires too many filters for decoding"); + return (ARCHIVE_FATAL); } /* From owner-svn-src-vendor@freebsd.org Wed Feb 24 21:33:01 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 0C604AB3BFB; Wed, 24 Feb 2016 21:33:01 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A4EB51A29; Wed, 24 Feb 2016 21:33:00 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1OLWxtT066456; Wed, 24 Feb 2016 21:32:59 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1OLWwnw066441; Wed, 24 Feb 2016 21:32:58 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602242132.u1OLWwnw066441@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 24 Feb 2016 21:32:58 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r296003 - in vendor/llvm/dist: lib/CodeGen lib/Target/AArch64 lib/Target/PowerPC lib/Target/X86 test/CodeGen/AArch64 test/CodeGen/ARM/Windows test/CodeGen/PowerPC test/CodeGen/X86 X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Feb 2016 21:33:01 -0000 Author: dim Date: Wed Feb 24 21:32:58 2016 New Revision: 296003 URL: https://svnweb.freebsd.org/changeset/base/296003 Log: Vendor import of llvm release_38 branch r261684: https://llvm.org/svn/llvm-project/llvm/branches/release_38@261684 Added: vendor/llvm/dist/test/CodeGen/PowerPC/pr26690.ll vendor/llvm/dist/test/CodeGen/X86/i386-tlscall-fastregalloc.ll vendor/llvm/dist/test/CodeGen/X86/tls-shrink-wrapping.ll Modified: vendor/llvm/dist/lib/CodeGen/RegAllocFast.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.h vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.h vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist/lib/Target/X86/X86ISelLowering.h vendor/llvm/dist/lib/Target/X86/X86InstrCompiler.td vendor/llvm/dist/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll vendor/llvm/dist/test/CodeGen/AArch64/arm64-shrink-wrapping.ll vendor/llvm/dist/test/CodeGen/ARM/Windows/alloca.ll Modified: vendor/llvm/dist/lib/CodeGen/RegAllocFast.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/RegAllocFast.cpp Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/lib/CodeGen/RegAllocFast.cpp Wed Feb 24 21:32:58 2016 (r296003) @@ -1002,11 +1002,13 @@ void RAFast::AllocateBasicBlock() { unsigned DefOpEnd = MI->getNumOperands(); if (MI->isCall()) { - // Spill all virtregs before a call. This serves two purposes: 1. If an + // Spill all virtregs before a call. This serves one purpose: If an // exception is thrown, the landing pad is going to expect to find - // registers in their spill slots, and 2. we don't have to wade through - // all the operands on the call instruction. - DefOpEnd = VirtOpEnd; + // registers in their spill slots. + // Note: although this is appealing to just consider all definitions + // as call-clobbered, this is not correct because some of those + // definitions may be used later on and we do not want to reuse + // those for virtual registers in between. DEBUG(dbgs() << " Spilling remaining registers before call.\n"); spillAll(MI); Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp Wed Feb 24 21:32:58 2016 (r296003) @@ -275,6 +275,18 @@ static bool isCSSave(MachineInstr *MBBI) MBBI->getOpcode() == AArch64::STPDpre; } +bool AArch64FrameLowering::canUseAsPrologue( + const MachineBasicBlock &MBB) const { + const MachineFunction *MF = MBB.getParent(); + const AArch64Subtarget &Subtarget = MF->getSubtarget(); + const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); + + // Don't need a scratch register if we're not going to re-align the stack. + // Otherwise, we may need a scratch register to be available and we do not + // support that for now. + return !RegInfo->needsStackRealignment(*MF); +} + void AArch64FrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = MBB.begin(); Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.h ============================================================================== --- vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.h Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.h Wed Feb 24 21:32:58 2016 (r296003) @@ -37,6 +37,8 @@ public: void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + bool canUseAsPrologue(const MachineBasicBlock &MBB) const override; + int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override; int resolveFrameIndexReference(const MachineFunction &MF, int FI, Modified: vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.cpp Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.cpp Wed Feb 24 21:32:58 2016 (r296003) @@ -556,16 +556,42 @@ void PPCFrameLowering::replaceFPWithReal } } -bool PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, - bool UseAtEnd, - unsigned *ScratchRegister) const { +/* This function will do the following: + - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12 + respectively (defaults recommended by the ABI) and return true + - If MBB is not an entry block, initialize the register scavenger and look + for available registers. + - If the defaults (R0/R12) are available, return true + - If TwoUniqueRegsRequired is set to true, it looks for two unique + registers. Otherwise, look for a single available register. + - If the required registers are found, set SR1 and SR2 and return true. + - If the required registers are not found, set SR2 or both SR1 and SR2 to + PPC::NoRegister and return false. + + Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired + is not set, this function will attempt to find two different registers, but + still return true if only one register is available (and set SR1 == SR2). +*/ +bool +PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, + bool UseAtEnd, + bool TwoUniqueRegsRequired, + unsigned *SR1, + unsigned *SR2) const { RegScavenger RS; - unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0; + unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0; + unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; + + // Set the defaults for the two scratch registers. + if (SR1) + *SR1 = R0; - if (ScratchRegister) - *ScratchRegister = R0; + if (SR2) { + assert (SR1 && "Asking for the second scratch register but not the first?"); + *SR2 = R12; + } - // If MBB is an entry or exit block, use R0 as the scratch register + // If MBB is an entry or exit block, use R0 and R12 as the scratch registers. if ((UseAtEnd && MBB->isReturnBlock()) || (!UseAtEnd && (&MBB->getParent()->front() == MBB))) return true; @@ -573,8 +599,8 @@ bool PPCFrameLowering::findScratchRegist RS.enterBasicBlock(MBB); if (UseAtEnd && !MBB->empty()) { - // The scratch register will be used at the end of the block, so must consider - // all registers used within the block + // The scratch register will be used at the end of the block, so must + // consider all registers used within the block MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator(); // If no terminator, back iterator up to previous instruction. @@ -584,35 +610,86 @@ bool PPCFrameLowering::findScratchRegist if (MBBI != MBB->begin()) RS.forward(MBBI); } - - if (!RS.isRegUsed(R0)) + + // If the two registers are available, we're all good. + // Note that we only return here if both R0 and R12 are available because + // although the function may not require two unique registers, it may benefit + // from having two so we should try to provide them. + if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) return true; - unsigned Reg = RS.FindUnusedReg(Subtarget.isPPC64() ? &PPC::G8RCRegClass - : &PPC::GPRCRegClass); - - // Make sure the register scavenger was able to find an available register - // If not, use R0 but return false to indicate no register was available and - // R0 must be used (as recommended by the ABI) - if (Reg == 0) - return false; + // Get the list of callee-saved registers for the target. + const PPCRegisterInfo *RegInfo = + static_cast(Subtarget.getRegisterInfo()); + const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); - if (ScratchRegister) - *ScratchRegister = Reg; + // Get all the available registers in the block. + BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass : + &PPC::GPRCRegClass); + + // We shouldn't use callee-saved registers as scratch registers as they may be + // available when looking for a candidate block for shrink wrapping but not + // available when the actual prologue/epilogue is being emitted because they + // were added as live-in to the prologue block by PrologueEpilogueInserter. + for (int i = 0; CSRegs[i]; ++i) + BV.reset(CSRegs[i]); + + // Set the first scratch register to the first available one. + if (SR1) { + int FirstScratchReg = BV.find_first(); + *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg; + } + + // If there is another one available, set the second scratch register to that. + // Otherwise, set it to either PPC::NoRegister if this function requires two + // or to whatever SR1 is set to if this function doesn't require two. + if (SR2) { + int SecondScratchReg = BV.find_next(*SR1); + if (SecondScratchReg != -1) + *SR2 = SecondScratchReg; + else + *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1; + } + + // Now that we've done our best to provide both registers, double check + // whether we were unable to provide enough. + if (BV.count() < (TwoUniqueRegsRequired ? 2 : 1)) + return false; return true; } +// We need a scratch register for spilling LR and for spilling CR. By default, +// we use two scratch registers to hide latency. However, if only one scratch +// register is available, we can adjust for that by not overlapping the spill +// code. However, if we need to realign the stack (i.e. have a base pointer) +// and the stack frame is large, we need two scratch registers. +bool +PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const { + const PPCRegisterInfo *RegInfo = + static_cast(Subtarget.getRegisterInfo()); + MachineFunction &MF = *(MBB->getParent()); + bool HasBP = RegInfo->hasBasePointer(MF); + unsigned FrameSize = determineFrameLayout(MF, false); + int NegFrameSize = -FrameSize; + bool IsLargeFrame = !isInt<16>(NegFrameSize); + MachineFrameInfo *MFI = MF.getFrameInfo(); + unsigned MaxAlign = MFI->getMaxAlignment(); + + return IsLargeFrame && HasBP && MaxAlign > 1; +} + bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { MachineBasicBlock *TmpMBB = const_cast(&MBB); - return findScratchRegister(TmpMBB, false, nullptr); + return findScratchRegister(TmpMBB, false, + twoUniqueScratchRegsRequired(TmpMBB)); } bool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { MachineBasicBlock *TmpMBB = const_cast(&MBB); - return findScratchRegister(TmpMBB, true, nullptr); + return findScratchRegister(TmpMBB, true); } void PPCFrameLowering::emitPrologue(MachineFunction &MF, @@ -664,6 +741,7 @@ void PPCFrameLowering::emitPrologue(Mach PPCFunctionInfo *FI = MF.getInfo(); bool MustSaveLR = FI->mustSaveLR(); const SmallVectorImpl &MustSaveCRs = FI->getMustSaveCRs(); + bool MustSaveCR = !MustSaveCRs.empty(); // Do we have a frame pointer and/or base pointer for this function? bool HasFP = hasFP(MF); bool HasBP = RegInfo->hasBasePointer(MF); @@ -701,9 +779,15 @@ void PPCFrameLowering::emitPrologue(Mach assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); - findScratchRegister(&MBB, false, &ScratchReg); - assert(ScratchReg && "No scratch register!"); - + // Using the same bool variable as below to supress compiler warnings. + bool SingleScratchReg = + findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB), + &ScratchReg, &TempReg); + assert(SingleScratchReg && + "Required number of registers not available in this block"); + + SingleScratchReg = ScratchReg == TempReg; + int LROffset = getReturnSaveOffset(); int FPOffset = 0; @@ -748,13 +832,30 @@ void PPCFrameLowering::emitPrologue(Mach // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. bool isLargeFrame = !isInt<16>(NegFrameSize); + assert((isPPC64 || !MustSaveCR) && + "Prologue CR saving supported only in 64-bit mode"); + + // If we need to spill the CR and the LR but we don't have two separate + // registers available, we must spill them one at a time + if (MustSaveCR && SingleScratchReg && MustSaveLR) { + // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. + // If only one or two CR fields are clobbered, it could be more + // efficient to use mfocrf to selectively save just those fields. + MachineInstrBuilder MIB = + BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); + for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) + MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); + BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) + .addReg(TempReg, getKillRegState(true)) + .addImm(8) + .addReg(SPReg); + } + if (MustSaveLR) BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); - assert((isPPC64 || MustSaveCRs.empty()) && - "Prologue CR saving supported only in 64-bit mode"); - - if (!MustSaveCRs.empty()) { // will only occur for PPC64 + if (MustSaveCR && + !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. // If only one or two CR fields are clobbered, it could be more // efficient to use mfocrf to selectively save just those fields. @@ -792,7 +893,8 @@ void PPCFrameLowering::emitPrologue(Mach .addImm(LROffset) .addReg(SPReg); - if (!MustSaveCRs.empty()) // will only occur for PPC64 + if (MustSaveCR && + !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) .addReg(TempReg, getKillRegState(true)) .addImm(8) @@ -811,6 +913,7 @@ void PPCFrameLowering::emitPrologue(Mach .addReg(SPReg); } + // This condition must be kept in sync with canUseAsPrologue. if (HasBP && MaxAlign > 1) { if (isPPC64) BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) @@ -828,6 +931,7 @@ void PPCFrameLowering::emitPrologue(Mach .addReg(ScratchReg, RegState::Kill) .addImm(NegFrameSize); } else { + assert(!SingleScratchReg && "Only a single scratch reg available"); BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) .addImm(NegFrameSize >> 16); BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) @@ -951,7 +1055,7 @@ void PPCFrameLowering::emitPrologue(Mach // For SVR4, don't emit a move for the CR spill slot if we haven't // spilled CRs. if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) - && MustSaveCRs.empty()) + && !MustSaveCR) continue; // For 64-bit SVR4 when we have spilled CRs, the spill location @@ -1005,6 +1109,7 @@ void PPCFrameLowering::emitEpilogue(Mach PPCFunctionInfo *FI = MF.getInfo(); bool MustSaveLR = FI->mustSaveLR(); const SmallVectorImpl &MustSaveCRs = FI->getMustSaveCRs(); + bool MustSaveCR = !MustSaveCRs.empty(); // Do we have a frame pointer and/or base pointer for this function? bool HasFP = hasFP(MF); bool HasBP = RegInfo->hasBasePointer(MF); @@ -1026,14 +1131,19 @@ void PPCFrameLowering::emitEpilogue(Mach : PPC::ADDI ); const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 : PPC::ADD4 ); - + int LROffset = getReturnSaveOffset(); int FPOffset = 0; - findScratchRegister(&MBB, true, &ScratchReg); - assert(ScratchReg && "No scratch register!"); - + // Using the same bool variable as below to supress compiler warnings. + bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg, + &TempReg); + assert(SingleScratchReg && + "Could not find an available scratch register"); + + SingleScratchReg = ScratchReg == TempReg; + if (HasFP) { if (isSVR4ABI) { MachineFrameInfo *FFI = MF.getFrameInfo(); @@ -1130,15 +1240,27 @@ void PPCFrameLowering::emitEpilogue(Mach } } + assert((isPPC64 || !MustSaveCR) && + "Epilogue CR restoring supported only in 64-bit mode"); + + // If we need to save both the LR and the CR and we only have one available + // scratch register, we must do them one at a time. + if (MustSaveCR && SingleScratchReg && MustSaveLR) { + BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) + .addImm(8) + .addReg(SPReg); + for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) + BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) + .addReg(TempReg, getKillRegState(i == e-1)); + } + if (MustSaveLR) BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) .addImm(LROffset) .addReg(SPReg); - assert((isPPC64 || MustSaveCRs.empty()) && - "Epilogue CR restoring supported only in 64-bit mode"); - - if (!MustSaveCRs.empty()) // will only occur for PPC64 + if (MustSaveCR && + !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) .addImm(8) .addReg(SPReg); @@ -1160,7 +1282,8 @@ void PPCFrameLowering::emitEpilogue(Mach .addImm(BPOffset) .addReg(SPReg); - if (!MustSaveCRs.empty()) // will only occur for PPC64 + if (MustSaveCR && + !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) .addReg(TempReg, getKillRegState(i == e-1)); Modified: vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.h ============================================================================== --- vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.h Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.h Wed Feb 24 21:32:58 2016 (r296003) @@ -30,28 +30,41 @@ class PPCFrameLowering: public TargetFra const unsigned BasePointerSaveOffset; /** - * \brief Find a register that can be used in function prologue and epilogue + * \brief Find register[s] that can be used in function prologue and epilogue * - * Find a register that can be use as the scratch register in function + * Find register[s] that can be use as scratch register[s] in function * prologue and epilogue to save various registers (Link Register, Base - * Pointer, etc.). Prefer R0, if it is available. If it is not available, - * then choose a different register. + * Pointer, etc.). Prefer R0/R12, if available. Otherwise choose whatever + * register[s] are available. * - * This method will return true if an available register was found (including - * R0). If no available registers are found, the method returns false and sets - * ScratchRegister to R0, as per the recommendation in the ABI. + * This method will return true if it is able to find enough unique scratch + * registers (1 or 2 depending on the requirement). If it is unable to find + * enough available registers in the block, it will return false and set + * any passed output parameter that corresponds to a required unique register + * to PPC::NoRegister. * * \param[in] MBB The machine basic block to find an available register for * \param[in] UseAtEnd Specify whether the scratch register will be used at * the end of the basic block (i.e., will the scratch * register kill a register defined in the basic block) - * \param[out] ScratchRegister The scratch register to use - * \return true if a scratch register was found. false of a scratch register - * was not found and R0 is being used as the default. + * \param[in] TwoUniqueRegsRequired Specify whether this basic block will + * require two unique scratch registers. + * \param[out] SR1 The scratch register to use + * \param[out] SR2 The second scratch register. If this pointer is not null + * the function will attempt to set it to an available + * register regardless of whether there is a hard requirement + * for two unique scratch registers. + * \return true if the required number of registers was found. + * false if the required number of scratch register weren't available. + * If either output parameter refers to a required scratch register + * that isn't available, it will be set to an invalid value. */ bool findScratchRegister(MachineBasicBlock *MBB, bool UseAtEnd, - unsigned *ScratchRegister) const; + bool TwoUniqueRegsRequired = false, + unsigned *SR1 = nullptr, + unsigned *SR2 = nullptr) const; + bool twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const; public: PPCFrameLowering(const PPCSubtarget &STI); Modified: vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp Wed Feb 24 21:32:58 2016 (r296003) @@ -22228,6 +22228,35 @@ X86TargetLowering::EmitLoweredCatchPad(M } MachineBasicBlock * +X86TargetLowering::EmitLoweredTLSAddr(MachineInstr *MI, + MachineBasicBlock *BB) const { + // So, here we replace TLSADDR with the sequence: + // adjust_stackdown -> TLSADDR -> adjust_stackup. + // We need this because TLSADDR is lowered into calls + // inside MC, therefore without the two markers shrink-wrapping + // may push the prologue/epilogue pass them. + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); + DebugLoc DL = MI->getDebugLoc(); + MachineFunction &MF = *BB->getParent(); + + // Emit CALLSEQ_START right before the instruction. + unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); + MachineInstrBuilder CallseqStart = + BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0); + BB->insert(MachineBasicBlock::iterator(MI), CallseqStart); + + // Emit CALLSEQ_END right after the instruction. + // We don't call erase from parent because we want to keep the + // original instruction around. + unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); + MachineInstrBuilder CallseqEnd = + BuildMI(MF, DL, TII.get(AdjStackUp)).addImm(0).addImm(0); + BB->insertAfter(MachineBasicBlock::iterator(MI), CallseqEnd); + + return BB; +} + +MachineBasicBlock * X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, MachineBasicBlock *BB) const { // This is pretty easy. We're taking the value that we received from @@ -22607,6 +22636,11 @@ X86TargetLowering::EmitInstrWithCustomIn case X86::TCRETURNri64: case X86::TCRETURNmi64: return BB; + case X86::TLS_addr32: + case X86::TLS_addr64: + case X86::TLS_base_addr32: + case X86::TLS_base_addr64: + return EmitLoweredTLSAddr(MI, BB); case X86::WIN_ALLOCA: return EmitLoweredWinAlloca(MI, BB); case X86::CATCHRET: Modified: vendor/llvm/dist/lib/Target/X86/X86ISelLowering.h ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86ISelLowering.h Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/lib/Target/X86/X86ISelLowering.h Wed Feb 24 21:32:58 2016 (r296003) @@ -1129,6 +1129,9 @@ namespace llvm { MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr *MI, + MachineBasicBlock *BB) const; + MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, MachineBasicBlock *BB) const; Modified: vendor/llvm/dist/lib/Target/X86/X86InstrCompiler.td ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86InstrCompiler.td Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/lib/Target/X86/X86InstrCompiler.td Wed Feb 24 21:32:58 2016 (r296003) @@ -436,7 +436,7 @@ let Defs = [EAX, ECX, EDX, FP0, FP1, FP2 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], - Uses = [ESP] in { + usesCustomInserter = 1, Uses = [ESP] in { def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), "# TLS_addr32", [(X86tlsaddr tls32addr:$sym)]>, @@ -456,7 +456,7 @@ let Defs = [RAX, RCX, RDX, RSI, RDI, R8, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], - Uses = [RSP] in { + usesCustomInserter = 1, Uses = [RSP] in { def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), "# TLS_addr64", [(X86tlsaddr tls64addr:$sym)]>, Modified: vendor/llvm/dist/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll ============================================================================== --- vendor/llvm/dist/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll Wed Feb 24 21:32:58 2016 (r296003) @@ -522,10 +522,10 @@ bb1: ; CHECK-LABEL: realign_conditional2 ; Extra realignment in the prologue (performance issue). -; CHECK: tbz {{.*}} .[[LABEL:.*]] ; CHECK: sub x9, sp, #32 // =32 ; CHECK: and sp, x9, #0xffffffffffffffe0 ; CHECK: mov x19, sp +; CHECK: tbz {{.*}} .[[LABEL:.*]] ; Stack is realigned in a non-entry BB. ; CHECK: sub [[REG:x[01-9]+]], sp, #64 ; CHECK: and sp, [[REG]], #0xffffffffffffffe0 Modified: vendor/llvm/dist/test/CodeGen/AArch64/arm64-shrink-wrapping.ll ============================================================================== --- vendor/llvm/dist/test/CodeGen/AArch64/arm64-shrink-wrapping.ll Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/test/CodeGen/AArch64/arm64-shrink-wrapping.ll Wed Feb 24 21:32:58 2016 (r296003) @@ -630,3 +630,88 @@ loop2b: end: ret void } + +; Don't do shrink-wrapping when we need to re-align the stack pointer. +; See bug 26642. +; CHECK-LABEL: stack_realign: +; CHECK-NOT: lsl w[[LSL1:[0-9]+]], w0, w1 +; CHECK-NOT: lsl w[[LSL2:[0-9]+]], w1, w0 +; CHECK: stp x29, x30, [sp, #-16]! +; CHECK: mov x29, sp +; CHECK: sub x{{[0-9]+}}, sp, #16 +; CHECK-DAG: lsl w[[LSL1:[0-9]+]], w0, w1 +; CHECK-DAG: lsl w[[LSL2:[0-9]+]], w1, w0 +; CHECK-DAG: str w[[LSL1]], +; CHECK-DAG: str w[[LSL2]], + +define i32 @stack_realign(i32 %a, i32 %b, i32* %ptr1, i32* %ptr2) { + %tmp = alloca i32, align 32 + %shl1 = shl i32 %a, %b + %shl2 = shl i32 %b, %a + %tmp2 = icmp slt i32 %a, %b + br i1 %tmp2, label %true, label %false + +true: + store i32 %a, i32* %tmp, align 4 + %tmp4 = load i32, i32* %tmp + br label %false + +false: + %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ] + store i32 %shl1, i32* %ptr1 + store i32 %shl2, i32* %ptr2 + ret i32 %tmp.0 +} + +; Re-aligned stack pointer with all caller-save regs live. See bug +; 26642. In this case we currently avoid shrink wrapping because +; ensuring we have a scratch register to re-align the stack pointer is +; too complicated. Output should be the same for both enabled and +; disabled shrink wrapping. +; CHECK-LABEL: stack_realign2: +; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #-{{[0-9]+}}]! +; CHECK: add x29, sp, #{{[0-9]+}} +; CHECK: lsl {{w[0-9]+}}, w0, w1 + +define void @stack_realign2(i32 %a, i32 %b, i32* %ptr1, i32* %ptr2, i32* %ptr3, i32* %ptr4, i32* %ptr5, i32* %ptr6) { + %tmp = alloca i32, align 32 + %tmp1 = shl i32 %a, %b + %tmp2 = shl i32 %b, %a + %tmp3 = lshr i32 %a, %b + %tmp4 = lshr i32 %b, %a + %tmp5 = add i32 %b, %a + %tmp6 = sub i32 %b, %a + %tmp7 = add i32 %tmp1, %tmp2 + %tmp8 = sub i32 %tmp2, %tmp3 + %tmp9 = add i32 %tmp3, %tmp4 + %tmp10 = add i32 %tmp4, %tmp5 + %cmp = icmp slt i32 %a, %b + br i1 %cmp, label %true, label %false + +true: + store i32 %a, i32* %tmp, align 4 + call void asm sideeffect "nop", "~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28}"() nounwind + br label %false + +false: + store i32 %tmp1, i32* %ptr1, align 4 + store i32 %tmp2, i32* %ptr2, align 4 + store i32 %tmp3, i32* %ptr3, align 4 + store i32 %tmp4, i32* %ptr4, align 4 + store i32 %tmp5, i32* %ptr5, align 4 + store i32 %tmp6, i32* %ptr6, align 4 + %idx1 = getelementptr inbounds i32, i32* %ptr1, i64 1 + store i32 %a, i32* %idx1, align 4 + %idx2 = getelementptr inbounds i32, i32* %ptr1, i64 2 + store i32 %b, i32* %idx2, align 4 + %idx3 = getelementptr inbounds i32, i32* %ptr1, i64 3 + store i32 %tmp7, i32* %idx3, align 4 + %idx4 = getelementptr inbounds i32, i32* %ptr1, i64 4 + store i32 %tmp8, i32* %idx4, align 4 + %idx5 = getelementptr inbounds i32, i32* %ptr1, i64 5 + store i32 %tmp9, i32* %idx5, align 4 + %idx6 = getelementptr inbounds i32, i32* %ptr1, i64 6 + store i32 %tmp10, i32* %idx6, align 4 + + ret void +} Modified: vendor/llvm/dist/test/CodeGen/ARM/Windows/alloca.ll ============================================================================== --- vendor/llvm/dist/test/CodeGen/ARM/Windows/alloca.ll Wed Feb 24 21:19:44 2016 (r296002) +++ vendor/llvm/dist/test/CodeGen/ARM/Windows/alloca.ll Wed Feb 24 21:32:58 2016 (r296003) @@ -13,7 +13,9 @@ entry: } ; CHECK: bl num_entries -; CHECK: movs [[R1:r[0-9]+]], #7 +; Any register is actually valid here, but turns out we use lr, +; because we do not have the kill flag on R0. +; CHECK: mov.w [[R1:lr]], #7 ; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2 ; CHECK: bic [[R0]], [[R0]], #7 ; CHECK: lsrs r4, [[R0]], #2 Added: vendor/llvm/dist/test/CodeGen/PowerPC/pr26690.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/CodeGen/PowerPC/pr26690.ll Wed Feb 24 21:32:58 2016 (r296003) @@ -0,0 +1,118 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +%struct.anon = type { %struct.anon.0, %struct.anon.1 } +%struct.anon.0 = type { i32 } +%struct.anon.1 = type { i32 } + +@i = common global i32 0, align 4 +@b = common global i32* null, align 8 +@c = common global i32 0, align 4 +@a = common global i32 0, align 4 +@h = common global i32 0, align 4 +@g = common global i32 0, align 4 +@j = common global i32 0, align 4 +@f = common global %struct.anon zeroinitializer, align 4 +@d = common global i32 0, align 4 +@e = common global i32 0, align 4 + +; Function Attrs: norecurse nounwind +define signext i32 @fn1(i32* nocapture %p1, i32 signext %p2, i32* nocapture %p3) { +entry: + %0 = load i32, i32* @i, align 4, !tbaa !1 + %cond = icmp eq i32 %0, 8 + br i1 %cond, label %if.end16, label %while.cond.preheader + +while.cond.preheader: ; preds = %entry + %1 = load i32*, i32** @b, align 8, !tbaa !5 + %2 = load i32, i32* %1, align 4, !tbaa !1 + %tobool18 = icmp eq i32 %2, 0 + br i1 %tobool18, label %while.end, label %while.body.lr.ph + +while.body.lr.ph: ; preds = %while.cond.preheader + %.pre = load i32, i32* @c, align 4, !tbaa !1 + br label %while.body + +while.body: ; preds = %while.body.backedge, %while.body.lr.ph + switch i32 %.pre, label %while.body.backedge [ + i32 0, label %sw.bb1 + i32 8, label %sw.bb1 + i32 6, label %sw.bb1 + i32 24, label %while.cond.backedge + ] + +while.body.backedge: ; preds = %while.body, %while.cond.backedge + br label %while.body + +sw.bb1: ; preds = %while.body, %while.body, %while.body + store i32 2, i32* @a, align 4, !tbaa !1 + br label %while.cond.backedge + +while.cond.backedge: ; preds = %while.body, %sw.bb1 + store i32 4, i32* @a, align 4, !tbaa !1 + %.pre19 = load i32, i32* %1, align 4, !tbaa !1 + %tobool = icmp eq i32 %.pre19, 0 + br i1 %tobool, label %while.end.loopexit, label %while.body.backedge + +while.end.loopexit: ; preds = %while.cond.backedge + br label %while.end + +while.end: ; preds = %while.end.loopexit, %while.cond.preheader + %3 = load i32, i32* @h, align 4, !tbaa !1 + %mul = mul nsw i32 %0, %3 + %4 = load i32, i32* @g, align 4, !tbaa !1 + %mul4 = mul nsw i32 %mul, %4 + store i32 %mul4, i32* @j, align 4, !tbaa !1 + %5 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @f, i64 0, i32 0, i32 0), align 4, !tbaa !7 + %tobool5 = icmp eq i32 %5, 0 + br i1 %tobool5, label %if.end, label %if.then + +if.then: ; preds = %while.end + %div = sdiv i32 %5, %mul + store i32 %div, i32* @g, align 4, !tbaa !1 + br label %if.end + +if.end: ; preds = %while.end, %if.then + %6 = phi i32 [ %4, %while.end ], [ %div, %if.then ] + %7 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @f, i64 0, i32 1, i32 0), align 4, !tbaa !10 + %tobool7 = icmp ne i32 %7, 0 + %tobool8 = icmp ne i32 %mul4, 0 + %or.cond = and i1 %tobool7, %tobool8 + %tobool10 = icmp ne i32 %0, 0 + %or.cond17 = and i1 %or.cond, %tobool10 + br i1 %or.cond17, label %if.then11, label %if.end13 + +if.then11: ; preds = %if.end + store i32 %3, i32* @d, align 4, !tbaa !1 + %8 = load i32, i32* @e, align 4, !tbaa !1 + store i32 %8, i32* %p3, align 4, !tbaa !1 + %.pre20 = load i32, i32* @g, align 4, !tbaa !1 + br label %if.end13 + +if.end13: ; preds = %if.then11, %if.end + %9 = phi i32 [ %.pre20, %if.then11 ], [ %6, %if.end ] + %tobool14 = icmp eq i32 %9, 0 + br i1 %tobool14, label %if.end16, label %if.then15 + +if.then15: ; preds = %if.end13 + store i32 %p2, i32* %p1, align 4, !tbaa !1 + br label %if.end16 + +if.end16: ; preds = %entry, %if.end13, %if.then15 + ret i32 2 +} + +; CHECK: mfcr {{[0-9]+}} + +!llvm.ident = !{!0} + +!0 = !{!"clang version 3.9.0 (trunk 261520)"} +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} +!5 = !{!6, !6, i64 0} +!6 = !{!"any pointer", !3, i64 0} +!7 = !{!8, !2, i64 0} +!8 = !{!"", !9, i64 0, !9, i64 4} +!9 = !{!"", !2, i64 0} +!10 = !{!8, !2, i64 4} Added: vendor/llvm/dist/test/CodeGen/X86/i386-tlscall-fastregalloc.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/CodeGen/X86/i386-tlscall-fastregalloc.ll Wed Feb 24 21:32:58 2016 (r296003) @@ -0,0 +1,26 @@ +; RUN: llc %s -o - -O0 -regalloc=fast | FileCheck %s +target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128" +target triple = "i386-apple-macosx10.10" + +@c = external global i8, align 1 +@p = thread_local global i8* null, align 4 + +; Check that regalloc fast correctly preserves EAX that is set by the TLS call +; until the actual use. +; PR26485. +; +; CHECK-LABEL: f: +; Get p. +; CHECK: movl _p@{{[0-9a-zA-Z]+}}, [[P_ADDR:%[a-z]+]] +; CHECK-NEXT: calll *([[P_ADDR]]) +; At this point eax contiains the address of p. +; Load c address. +; Make sure we do not clobber eax. +; CHECK-NEXT: movl L_c{{[^,]*}}, [[C_ADDR:%e[b-z]x+]] +; Store c address into p. +; CHECK-NEXT: movl [[C_ADDR]], (%eax) +define void @f() #0 { +entry: + store i8* @c, i8** @p, align 4 + ret void +} Added: vendor/llvm/dist/test/CodeGen/X86/tls-shrink-wrapping.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/CodeGen/X86/tls-shrink-wrapping.ll Wed Feb 24 21:32:58 2016 (r296003) @@ -0,0 +1,60 @@ +; Testcase generated from the following code: +; extern __thread int i; +; void f(); +; int g(void) { +; if (i) { +; i = 0; +; f(); +; } +; return i; +; } +; We want to make sure that TLS variables are not accessed before +; the stack frame is set up. + +; RUN: llc < %s -relocation-model=pic | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-freebsd11.0" + +@i = external thread_local global i32, align 4 + +define i32 @g() #0 { +entry: + %tmp = load i32, i32* @i, align 4 + %tobool = icmp eq i32 %tmp, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + store i32 0, i32* @i, align 4 + tail call void (...) @f() #2 + %.pre = load i32, i32* @i, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + %tmp1 = phi i32 [ 0, %entry ], [ %.pre, %if.then ] + ret i32 %tmp1 +} + +; CHECK: g: # @g +; CHECK-NEXT: .cfi_startproc +; CHECK-NEXT: # BB#0: # %entry +; CHECK-NEXT: pushq %rbp +; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .Ltmp1: +; CHECK-NEXT: .cfi_offset %rbp, -16 +; CHECK-NEXT: movq %rsp, %rbp +; CHECK-NEXT: .Ltmp2: +; CHECK-NEXT: .cfi_def_cfa_register %rbp +; CHECK-NEXT: pushq %rbx +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .Ltmp3: +; CHECK-NEXT: .cfi_offset %rbx, -24 +; CHECK-NEXT: data16 +; CHECK-NEXT: leaq i@TLSGD(%rip), %rdi + +declare void @f(...) #1 + +attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind } From owner-svn-src-vendor@freebsd.org Wed Feb 24 21:33:21 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6C9CFAB3C33; Wed, 24 Feb 2016 21:33:21 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 226D71BCC; Wed, 24 Feb 2016 21:33:21 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1OLXKRO066529; Wed, 24 Feb 2016 21:33:20 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1OLXKh9066528; Wed, 24 Feb 2016 21:33:20 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602242133.u1OLXKh9066528@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 24 Feb 2016 21:33:20 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r296004 - vendor/llvm/llvm-release_38-r261684 X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Feb 2016 21:33:21 -0000 Author: dim Date: Wed Feb 24 21:33:19 2016 New Revision: 296004 URL: https://svnweb.freebsd.org/changeset/base/296004 Log: Tag llvm release_38 branch r261684. Added: vendor/llvm/llvm-release_38-r261684/ - copied from r296003, vendor/llvm/dist/ From owner-svn-src-vendor@freebsd.org Wed Feb 24 21:33:40 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 66CB9AB3C6D; Wed, 24 Feb 2016 21:33:40 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 3D0F51D06; Wed, 24 Feb 2016 21:33:40 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1OLXdDw066588; Wed, 24 Feb 2016 21:33:39 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1OLXc3W066583; Wed, 24 Feb 2016 21:33:38 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602242133.u1OLXc3W066583@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 24 Feb 2016 21:33:38 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r296005 - in vendor/clang/dist: docs lib/CodeGen lib/Sema test/CodeGen test/Sema X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Feb 2016 21:33:40 -0000 Author: dim Date: Wed Feb 24 21:33:38 2016 New Revision: 296005 URL: https://svnweb.freebsd.org/changeset/base/296005 Log: Vendor import of clang release_38 branch r261684: https://llvm.org/svn/llvm-project/cfe/branches/release_38@261684 Modified: vendor/clang/dist/docs/ReleaseNotes.rst vendor/clang/dist/lib/CodeGen/TargetInfo.cpp vendor/clang/dist/lib/Sema/SemaExpr.cpp vendor/clang/dist/test/CodeGen/ppc-varargs-struct.c vendor/clang/dist/test/Sema/generic-selection.c Modified: vendor/clang/dist/docs/ReleaseNotes.rst ============================================================================== --- vendor/clang/dist/docs/ReleaseNotes.rst Wed Feb 24 21:33:19 2016 (r296004) +++ vendor/clang/dist/docs/ReleaseNotes.rst Wed Feb 24 21:33:38 2016 (r296005) @@ -179,6 +179,33 @@ Several additional features/bugfixes hav - Improved diagnostics for function pointers. +OpenMP Support in Clang +--------------------- + +OpenMP 3.1 is fully supported and is enabled by default with -fopenmp +which now uses the clang OpenMP library instead of the GCC OpenMP library. +The runtime can be built in-tree. + +In addition to OpenMP 3.1, several important elements of the OpenMP 4.0/4.5 +are supported as well. We continue to aim to complete OpenMP 4.5 + +- ``map`` clause +- task dependencies +- ``num_teams`` clause +- ``thread_limit`` clause +- ``target`` and ``target data`` directive +- ``target`` directive with implicit data mapping +- ``target enter data`` and ``target exit data`` directive +- Array sections [2.4, Array Sections]. +- Directive name modifiers for ``if`` clause [2.12, if Clause]. +- ``linear`` clause can be used in loop-based directives [2.7.2, loop Construct]. +- ``simdlen`` clause [2.8, SIMD Construct]. +- ``hint`` clause [2.13.2, critical Construct]. +- Parsing/semantic analysis of all non-device directives introduced in OpenMP 4.5. + +The codegen for OpenMP constructs was significantly improved allowing us to produce much more stable and fast code. +Full test cases of IR are also implemented. + CUDA Support in Clang --------------------- Clang has experimental support for end-to-end CUDA compilation now: Modified: vendor/clang/dist/lib/CodeGen/TargetInfo.cpp ============================================================================== --- vendor/clang/dist/lib/CodeGen/TargetInfo.cpp Wed Feb 24 21:33:19 2016 (r296004) +++ vendor/clang/dist/lib/CodeGen/TargetInfo.cpp Wed Feb 24 21:33:38 2016 (r296005) @@ -3475,6 +3475,7 @@ public: Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList, QualType Ty) const { + const unsigned OverflowLimit = 8; if (const ComplexType *CTy = Ty->getAs()) { // TODO: Implement this. For now ignore. (void)CTy; @@ -3517,7 +3518,7 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co } llvm::Value *CC = - Builder.CreateICmpULT(NumRegs, Builder.getInt8(8), "cond"); + Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond"); llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs"); llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow"); @@ -3569,6 +3570,8 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co { CGF.EmitBlock(UsingOverflow); + Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr); + // Everything in the overflow area is rounded up to a size of at least 4. CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4); Modified: vendor/clang/dist/lib/Sema/SemaExpr.cpp ============================================================================== --- vendor/clang/dist/lib/Sema/SemaExpr.cpp Wed Feb 24 21:33:19 2016 (r296004) +++ vendor/clang/dist/lib/Sema/SemaExpr.cpp Wed Feb 24 21:33:38 2016 (r296005) @@ -1365,10 +1365,13 @@ Sema::CreateGenericSelectionExpr(SourceL // Decay and strip qualifiers for the controlling expression type, and handle // placeholder type replacement. See committee discussion from WG14 DR423. - ExprResult R = DefaultFunctionArrayLvalueConversion(ControllingExpr); - if (R.isInvalid()) - return ExprError(); - ControllingExpr = R.get(); + { + EnterExpressionEvaluationContext Unevaluated(*this, Sema::Unevaluated); + ExprResult R = DefaultFunctionArrayLvalueConversion(ControllingExpr); + if (R.isInvalid()) + return ExprError(); + ControllingExpr = R.get(); + } // The controlling expression is an unevaluated operand, so side effects are // likely unintended. Modified: vendor/clang/dist/test/CodeGen/ppc-varargs-struct.c ============================================================================== --- vendor/clang/dist/test/CodeGen/ppc-varargs-struct.c Wed Feb 24 21:33:19 2016 (r296004) +++ vendor/clang/dist/test/CodeGen/ppc-varargs-struct.c Wed Feb 24 21:33:38 2016 (r296005) @@ -37,6 +37,7 @@ void testva (int n, ...) // CHECK-PPC-NEXT: br label %[[CONT:[a-z0-9]+]] // // CHECK-PPC:[[USING_OVERFLOW]] +// CHECK-PPC-NEXT: store i8 8, i8* [[GPRPTR]], align 4 // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %argp.cur to i32 @@ -76,6 +77,7 @@ void testva (int n, ...) // CHECK-PPC-NEXT: br label %[[CONT:[a-z0-9]+]] // // CHECK-PPC:[[USING_OVERFLOW]] +// CHECK-PPC-NEXT: store i8 8, i8* [[GPRPTR]], align 4 // CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 // CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to i32* Modified: vendor/clang/dist/test/Sema/generic-selection.c ============================================================================== --- vendor/clang/dist/test/Sema/generic-selection.c Wed Feb 24 21:33:19 2016 (r296004) +++ vendor/clang/dist/test/Sema/generic-selection.c Wed Feb 24 21:33:38 2016 (r296005) @@ -31,4 +31,8 @@ void foo(int n) { const int i = 12; int a9[_Generic(i, int: 1, default: 2) == 1 ? 1 : -1]; + + // This is expected to not trigger any diagnostics because the controlling + // expression is not evaluated. + (void)_Generic(*(int *)0, int: 1); } From owner-svn-src-vendor@freebsd.org Wed Feb 24 21:33:58 2016 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6EFF8AB3CA3; Wed, 24 Feb 2016 21:33:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 24E0E1E66; Wed, 24 Feb 2016 21:33:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1OLXv5K066643; Wed, 24 Feb 2016 21:33:57 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1OLXvVR066642; Wed, 24 Feb 2016 21:33:57 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201602242133.u1OLXvVR066642@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 24 Feb 2016 21:33:57 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r296006 - vendor/clang/clang-release_38-r261684 X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Feb 2016 21:33:58 -0000 Author: dim Date: Wed Feb 24 21:33:56 2016 New Revision: 296006 URL: https://svnweb.freebsd.org/changeset/base/296006 Log: Tag clang release_38 branch r261684. Added: vendor/clang/clang-release_38-r261684/ - copied from r296005, vendor/clang/dist/