From owner-svn-src-head@freebsd.org Sun Aug 20 00:41:51 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1AED8DCDB9A; Sun, 20 Aug 2017 00:41:51 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id DECA26B9E3; Sun, 20 Aug 2017 00:41:50 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v7K0foOk011926; Sun, 20 Aug 2017 00:41:50 GMT (envelope-from cem@FreeBSD.org) Received: (from cem@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v7K0foic011925; Sun, 20 Aug 2017 00:41:50 GMT (envelope-from cem@FreeBSD.org) Message-Id: <201708200041.v7K0foic011925@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cem set sender to cem@FreeBSD.org using -f From: Conrad Meyer Date: Sun, 20 Aug 2017 00:41:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r322710 - head/sys/x86/cpufreq X-SVN-Group: head X-SVN-Commit-Author: cem X-SVN-Commit-Paths: head/sys/x86/cpufreq X-SVN-Commit-Revision: 322710 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 20 Aug 2017 00:41:51 -0000 Author: cem Date: Sun Aug 20 00:41:49 2017 New Revision: 322710 URL: https://svnweb.freebsd.org/changeset/base/322710 Log: hwpstate: Add support for family 17h pstate info from MSRs This information is normally available via acpi_perf, but in case it is not, add support for fetching the information via MSRs on AMD family 17h (Zen) processors. Zen uses a slightly different formula than previous generation AMD CPUs. This was inspired by, but does not fix, PR 221621. Reported by: Sean P. R. Reviewed by: mjoras@ Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12082 Modified: head/sys/x86/cpufreq/hwpstate.c Modified: head/sys/x86/cpufreq/hwpstate.c ============================================================================== --- head/sys/x86/cpufreq/hwpstate.c Sat Aug 19 23:13:33 2017 (r322709) +++ head/sys/x86/cpufreq/hwpstate.c Sun Aug 20 00:41:49 2017 (r322710) @@ -83,6 +83,10 @@ __FBSDID("$FreeBSD$"); #define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07) #define AMD_10H_11H_CUR_FID(msr) ((msr) & 0x3F) +#define AMD_17H_CUR_VID(msr) (((msr) >> 14) & 0xFF) +#define AMD_17H_CUR_DID(msr) (((msr) >> 8) & 0x3F) +#define AMD_17H_CUR_FID(msr) ((msr) & 0xFF) + #define HWPSTATE_DEBUG(dev, msg...) \ do{ \ if(hwpstate_verbose) \ @@ -426,6 +430,15 @@ hwpstate_get_info_from_msr(device_t dev) case 0x15: case 0x16: hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did; + break; + case 0x17: + did = AMD_17H_CUR_DID(msr); + if (did == 0) { + HWPSTATE_DEBUG(dev, "unexpected did: 0\n"); + did = 1; + } + fid = AMD_17H_CUR_FID(msr); + hwpstate_set[i].freq = (200 * fid) / did; break; default: HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family"