From owner-svn-src-projects@freebsd.org Mon May 22 19:06:41 2017 Return-Path: Delivered-To: svn-src-projects@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 5E2A2D79A1A for ; Mon, 22 May 2017 19:06:41 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 364DA1814; Mon, 22 May 2017 19:06:41 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v4MJ6ewm059527; Mon, 22 May 2017 19:06:40 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v4MJ6eAI059525; Mon, 22 May 2017 19:06:40 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201705221906.v4MJ6eAI059525@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Mon, 22 May 2017 19:06:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r318656 - in projects/clang500-import/lib/clang: . libllvm X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 May 2017 19:06:41 -0000 Author: dim Date: Mon May 22 19:06:39 2017 New Revision: 318656 URL: https://svnweb.freebsd.org/changeset/base/318656 Log: Following upstream trunk, enable the new global instruction selection (GlobalISel), cleanup some defines, and adjust the libllvm Makefile for this. Modified: projects/clang500-import/lib/clang/libllvm/Makefile projects/clang500-import/lib/clang/llvm.build.mk Modified: projects/clang500-import/lib/clang/libllvm/Makefile ============================================================================== --- projects/clang500-import/lib/clang/libllvm/Makefile Mon May 22 16:16:48 2017 (r318655) +++ projects/clang500-import/lib/clang/libllvm/Makefile Mon May 22 19:06:39 2017 (r318656) @@ -163,7 +163,19 @@ SRCS_MIN+= CodeGen/GCMetadata.cpp SRCS_MIN+= CodeGen/GCMetadataPrinter.cpp SRCS_MIN+= CodeGen/GCRootLowering.cpp SRCS_MIN+= CodeGen/GCStrategy.cpp +SRCS_MIN+= CodeGen/GlobalISel/CallLowering.cpp SRCS_MIN+= CodeGen/GlobalISel/GlobalISel.cpp +SRCS_MIN+= CodeGen/GlobalISel/IRTranslator.cpp +SRCS_MIN+= CodeGen/GlobalISel/InstructionSelect.cpp +SRCS_MIN+= CodeGen/GlobalISel/InstructionSelector.cpp +SRCS_MIN+= CodeGen/GlobalISel/Legalizer.cpp +SRCS_MIN+= CodeGen/GlobalISel/LegalizerHelper.cpp +SRCS_MIN+= CodeGen/GlobalISel/LegalizerInfo.cpp +SRCS_MIN+= CodeGen/GlobalISel/MachineIRBuilder.cpp +SRCS_MIN+= CodeGen/GlobalISel/RegBankSelect.cpp +SRCS_MIN+= CodeGen/GlobalISel/RegisterBank.cpp +SRCS_MIN+= CodeGen/GlobalISel/RegisterBankInfo.cpp +SRCS_MIN+= CodeGen/GlobalISel/Utils.cpp SRCS_MIN+= CodeGen/GlobalMerge.cpp SRCS_MIN+= CodeGen/IfConversion.cpp SRCS_MIN+= CodeGen/ImplicitNullChecks.cpp @@ -386,10 +398,10 @@ SRCS_EXT+= DebugInfo/PDB/Native/NativeRa SRCS_EXT+= DebugInfo/PDB/Native/NativeSession.cpp SRCS_EXT+= DebugInfo/PDB/Native/PDBFile.cpp SRCS_EXT+= DebugInfo/PDB/Native/PDBFileBuilder.cpp -SRCS_EXT+= DebugInfo/PDB/Native/PublicsStream.cpp -SRCS_EXT+= DebugInfo/PDB/Native/RawError.cpp SRCS_EXT+= DebugInfo/PDB/Native/PDBStringTable.cpp SRCS_EXT+= DebugInfo/PDB/Native/PDBStringTableBuilder.cpp +SRCS_EXT+= DebugInfo/PDB/Native/PublicsStream.cpp +SRCS_EXT+= DebugInfo/PDB/Native/RawError.cpp SRCS_EXT+= DebugInfo/PDB/Native/SymbolStream.cpp SRCS_EXT+= DebugInfo/PDB/Native/TpiHashing.cpp SRCS_EXT+= DebugInfo/PDB/Native/TpiStream.cpp @@ -737,6 +749,7 @@ SRCS_MIN+= Target/AArch64/AArch64A53Fix8 SRCS_MIN+= Target/AArch64/AArch64A57FPLoadBalancing.cpp SRCS_MIN+= Target/AArch64/AArch64AdvSIMDScalarPass.cpp SRCS_MIN+= Target/AArch64/AArch64AsmPrinter.cpp +SRCS_MIN+= Target/AArch64/AArch64CallLowering.cpp SRCS_MIN+= Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp SRCS_MIN+= Target/AArch64/AArch64CollectLOH.cpp SRCS_MIN+= Target/AArch64/AArch64ConditionOptimizer.cpp @@ -748,12 +761,15 @@ SRCS_MIN+= Target/AArch64/AArch64FrameLo SRCS_MIN+= Target/AArch64/AArch64ISelDAGToDAG.cpp SRCS_MIN+= Target/AArch64/AArch64ISelLowering.cpp SRCS_MIN+= Target/AArch64/AArch64InstrInfo.cpp +SRCS_MIN+= Target/AArch64/AArch64InstructionSelector.cpp +SRCS_MIN+= Target/AArch64/AArch64LegalizerInfo.cpp SRCS_MIN+= Target/AArch64/AArch64LoadStoreOptimizer.cpp SRCS_MIN+= Target/AArch64/AArch64MCInstLower.cpp SRCS_MIN+= Target/AArch64/AArch64MacroFusion.cpp SRCS_MIN+= Target/AArch64/AArch64PBQPRegAlloc.cpp SRCS_MIN+= Target/AArch64/AArch64PromoteConstant.cpp SRCS_MIN+= Target/AArch64/AArch64RedundantCopyElimination.cpp +SRCS_MIN+= Target/AArch64/AArch64RegisterBankInfo.cpp SRCS_MIN+= Target/AArch64/AArch64RegisterInfo.cpp SRCS_MIN+= Target/AArch64/AArch64SelectionDAGInfo.cpp SRCS_MIN+= Target/AArch64/AArch64StorePairSuppress.cpp @@ -781,6 +797,7 @@ SRCS_MIN+= Target/ARM/A15SDOptimizer.cpp SRCS_MIN+= Target/ARM/ARMAsmPrinter.cpp SRCS_MIN+= Target/ARM/ARMBaseInstrInfo.cpp SRCS_MIN+= Target/ARM/ARMBaseRegisterInfo.cpp +SRCS_MIN+= Target/ARM/ARMCallLowering.cpp SRCS_MIN+= Target/ARM/ARMComputeBlockSize.cpp SRCS_MIN+= Target/ARM/ARMConstantIslandPass.cpp SRCS_MIN+= Target/ARM/ARMConstantPoolValue.cpp @@ -791,10 +808,13 @@ SRCS_MIN+= Target/ARM/ARMHazardRecognize SRCS_MIN+= Target/ARM/ARMISelDAGToDAG.cpp SRCS_MIN+= Target/ARM/ARMISelLowering.cpp SRCS_MIN+= Target/ARM/ARMInstrInfo.cpp +SRCS_MIN+= Target/ARM/ARMInstructionSelector.cpp +SRCS_MIN+= Target/ARM/ARMLegalizerInfo.cpp SRCS_MIN+= Target/ARM/ARMLoadStoreOptimizer.cpp SRCS_MIN+= Target/ARM/ARMMCInstLower.cpp SRCS_MIN+= Target/ARM/ARMMachineFunctionInfo.cpp SRCS_MIN+= Target/ARM/ARMOptimizeBarriersPass.cpp +SRCS_MIN+= Target/ARM/ARMRegisterBankInfo.cpp SRCS_MIN+= Target/ARM/ARMRegisterInfo.cpp SRCS_MIN+= Target/ARM/ARMSelectionDAGInfo.cpp SRCS_MIN+= Target/ARM/ARMSubtarget.cpp @@ -963,6 +983,7 @@ SRCS_MIN+= Target/X86/TargetInfo/X86Targ SRCS_MIN+= Target/X86/Utils/X86ShuffleDecode.cpp SRCS_MIN+= Target/X86/X86AsmPrinter.cpp SRCS_MIN+= Target/X86/X86CallFrameOptimization.cpp +SRCS_MIN+= Target/X86/X86CallLowering.cpp SRCS_MIN+= Target/X86/X86CallingConv.cpp SRCS_MIN+= Target/X86/X86EvexToVex.cpp SRCS_MIN+= Target/X86/X86ExpandPseudo.cpp @@ -976,12 +997,15 @@ SRCS_MIN+= Target/X86/X86ISelDAGToDAG.cp SRCS_MIN+= Target/X86/X86ISelLowering.cpp SRCS_MIN+= Target/X86/X86InstrFMA3Info.cpp SRCS_MIN+= Target/X86/X86InstrInfo.cpp +SRCS_MIN+= Target/X86/X86InstructionSelector.cpp SRCS_MIN+= Target/X86/X86InterleavedAccess.cpp +SRCS_MIN+= Target/X86/X86LegalizerInfo.cpp SRCS_MIN+= Target/X86/X86MCInstLower.cpp SRCS_MIN+= Target/X86/X86MachineFunctionInfo.cpp SRCS_MIN+= Target/X86/X86MacroFusion.cpp SRCS_MIN+= Target/X86/X86OptimizeLEAs.cpp SRCS_MIN+= Target/X86/X86PadShortFunction.cpp +SRCS_MIN+= Target/X86/X86RegisterBankInfo.cpp SRCS_MIN+= Target/X86/X86RegisterInfo.cpp SRCS_MIN+= Target/X86/X86SelectionDAGInfo.cpp SRCS_MIN+= Target/X86/X86ShuffleDecodeConstantPool.cpp @@ -1251,6 +1275,7 @@ TGHDRS+= Options.inc DisassemblerTables/-gen-disassembler \ EVEX2VEXTables/-gen-x86-EVEX2VEX-tables \ FastISel/-gen-fast-isel \ + GlobalISel/-gen-global-isel \ InstrInfo/-gen-instr-info \ MCCodeEmitter/-gen-emitter \ MCPseudoLowering/-gen-pseudo-lowering \ @@ -1272,6 +1297,7 @@ TGHDRS+= AArch64GenCallingConv.inc TGHDRS+= AArch64GenDAGISel.inc TGHDRS+= AArch64GenDisassemblerTables.inc TGHDRS+= AArch64GenFastISel.inc +TGHDRS+= AArch64GenGlobalISel.inc TGHDRS+= AArch64GenInstrInfo.inc TGHDRS+= AArch64GenMCCodeEmitter.inc TGHDRS+= AArch64GenMCPseudoLowering.inc @@ -1285,6 +1311,7 @@ TGHDRS+= ARMGenCallingConv.inc TGHDRS+= ARMGenDAGISel.inc TGHDRS+= ARMGenDisassemblerTables.inc TGHDRS+= ARMGenFastISel.inc +TGHDRS+= ARMGenGlobalISel.inc TGHDRS+= ARMGenInstrInfo.inc TGHDRS+= ARMGenMCCodeEmitter.inc TGHDRS+= ARMGenMCPseudoLowering.inc @@ -1329,6 +1356,7 @@ TGHDRS+= X86GenDAGISel.inc TGHDRS+= X86GenDisassemblerTables.inc TGHDRS+= X86GenEVEX2VEXTables.inc TGHDRS+= X86GenFastISel.inc +TGHDRS+= X86GenGlobalISel.inc TGHDRS+= X86GenInstrInfo.inc TGHDRS+= X86GenRegisterBank.inc TGHDRS+= X86GenRegisterInfo.inc Modified: projects/clang500-import/lib/clang/llvm.build.mk ============================================================================== --- projects/clang500-import/lib/clang/llvm.build.mk Mon May 22 16:16:48 2017 (r318655) +++ projects/clang500-import/lib/clang/llvm.build.mk Mon May 22 19:06:39 2017 (r318656) @@ -12,8 +12,7 @@ CFLAGS+= -I${SRCTOP}/lib/clang/include CFLAGS+= -I${LLVM_SRCS}/include -CFLAGS+= -DLLVM_ON_UNIX -CFLAGS+= -DLLVM_ON_FREEBSD +CFLAGS+= -DLLVM_BUILD_GLOBAL_ISEL CFLAGS+= -D__STDC_LIMIT_MACROS CFLAGS+= -D__STDC_CONSTANT_MACROS #CFLAGS+= -DNDEBUG