Date: Sun, 24 Dec 2017 01:00:09 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r327122 - in vendor/llvm/dist: docs docs/tutorial examples/Kaleidoscope examples/Kaleidoscope/Chapter9 include/llvm include/llvm-c include/llvm/Analysis include/llvm/BinaryFormat includ... Message-ID: <201712240100.vBO109Ga073783@repo.freebsd.org>
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Author: dim Date: Sun Dec 24 01:00:08 2017 New Revision: 327122 URL: https://svnweb.freebsd.org/changeset/base/327122 Log: Vendor import of llvm trunk r321414: https://llvm.org/svn/llvm-project/llvm/trunk@321414 Added: vendor/llvm/dist/include/llvm/BinaryFormat/WasmRelocs.def vendor/llvm/dist/include/llvm/CodeGen/LiveStacks.h (contents, props changed) vendor/llvm/dist/include/llvm/CodeGen/SDNodeProperties.td vendor/llvm/dist/lib/CodeGen/LiveStacks.cpp (contents, props changed) vendor/llvm/dist/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir vendor/llvm/dist/test/CodeGen/AArch64/chkstk.ll vendor/llvm/dist/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll vendor/llvm/dist/test/CodeGen/ARM/su-addsub-overflow.ll vendor/llvm/dist/test/CodeGen/ARM/usat.ll vendor/llvm/dist/test/CodeGen/BPF/objdump_imm_hex.ll vendor/llvm/dist/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll vendor/llvm/dist/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll vendor/llvm/dist/test/CodeGen/Hexagon/autohvx/isel-select-const.ll vendor/llvm/dist/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll vendor/llvm/dist/test/CodeGen/Mips/long-call-mcount.ll vendor/llvm/dist/test/CodeGen/Mips/sll-micromips-r6-encoding.mir vendor/llvm/dist/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll vendor/llvm/dist/test/CodeGen/Thumb2/t2sizereduction.mir vendor/llvm/dist/test/DebugInfo/X86/dwarfdump-str-offsets-invalid-6.s (contents, props changed) vendor/llvm/dist/test/MC/AMDGPU/invalid-instructions-spellcheck.s (contents, props changed) vendor/llvm/dist/test/MC/ARM/dfb-neg.s (contents, props changed) vendor/llvm/dist/test/MC/ARM/dfb.s (contents, props changed) vendor/llvm/dist/test/MC/Disassembler/ARM/dfb-arm.txt (contents, props changed) vendor/llvm/dist/test/MC/Disassembler/ARM/dfb-thumb.txt (contents, props changed) vendor/llvm/dist/test/MC/X86/CLFLUSHOPT-32.s (contents, props changed) vendor/llvm/dist/test/MC/X86/CLFLUSHOPT-64.s (contents, props changed) vendor/llvm/dist/test/MC/X86/CLFSH-32.s (contents, props changed) vendor/llvm/dist/test/MC/X86/CLFSH-64.s (contents, props changed) vendor/llvm/dist/test/Transforms/CallSiteSplitting/callsite-no-or-structure.ll vendor/llvm/dist/test/Transforms/CallSiteSplitting/callsite-no-splitting.ll vendor/llvm/dist/test/Transforms/Inline/AArch64/binop.ll vendor/llvm/dist/test/Transforms/Inline/ARM/inline-fp.ll vendor/llvm/dist/test/Transforms/LoopVectorize/legal_preheader_check.ll vendor/llvm/dist/test/Transforms/MemCpyOpt/memcpy-invoke-memcpy.ll vendor/llvm/dist/test/Transforms/MemCpyOpt/merge-into-memset.ll vendor/llvm/dist/test/Transforms/MemCpyOpt/mixed-sizes.ll vendor/llvm/dist/test/Transforms/MemCpyOpt/nonlocal-memcpy-memcpy.ll vendor/llvm/dist/test/Transforms/SimplifyCFG/X86/if-conversion.ll vendor/llvm/dist/test/tools/llvm-objcopy/add-section-remove.test vendor/llvm/dist/test/tools/llvm-objcopy/add-section.test vendor/llvm/dist/utils/TableGen/SDNodeProperties.cpp (contents, props changed) vendor/llvm/dist/utils/TableGen/SDNodeProperties.h (contents, props changed) Deleted: vendor/llvm/dist/include/llvm/BinaryFormat/WasmRelocs/WebAssembly.def vendor/llvm/dist/include/llvm/CodeGen/LiveStackAnalysis.h vendor/llvm/dist/lib/CodeGen/LiveStackAnalysis.cpp vendor/llvm/dist/test/Transforms/Inline/inline-fp.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/jumbled-load-shuffle-placement.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/jumbled-load-used-in-phi.ll Modified: vendor/llvm/dist/docs/Extensions.rst vendor/llvm/dist/docs/MIRLangRef.rst vendor/llvm/dist/docs/tutorial/LangImpl09.rst vendor/llvm/dist/examples/Kaleidoscope/CMakeLists.txt vendor/llvm/dist/examples/Kaleidoscope/Chapter9/toy.cpp vendor/llvm/dist/include/llvm-c/lto.h vendor/llvm/dist/include/llvm/Analysis/AliasAnalysis.h vendor/llvm/dist/include/llvm/Analysis/AliasAnalysisEvaluator.h vendor/llvm/dist/include/llvm/Analysis/LoopAccessAnalysis.h vendor/llvm/dist/include/llvm/Analysis/MemoryDependenceAnalysis.h vendor/llvm/dist/include/llvm/Analysis/ProfileSummaryInfo.h vendor/llvm/dist/include/llvm/Analysis/ScalarEvolutionExpander.h vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfo.h vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfoImpl.h vendor/llvm/dist/include/llvm/BinaryFormat/Wasm.h vendor/llvm/dist/include/llvm/CodeGen/BasicTTIImpl.h vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/InstructionSelector.h vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h vendor/llvm/dist/include/llvm/CodeGen/MachineOperand.h vendor/llvm/dist/include/llvm/CodeGen/RuntimeLibcalls.def vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h vendor/llvm/dist/include/llvm/CodeGen/TargetLowering.h vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFUnit.h vendor/llvm/dist/include/llvm/FuzzMutate/IRMutator.h vendor/llvm/dist/include/llvm/IR/Function.h vendor/llvm/dist/include/llvm/IR/Intrinsics.td vendor/llvm/dist/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h vendor/llvm/dist/include/llvm/MC/MCAsmInfo.h vendor/llvm/dist/include/llvm/MC/MCStreamer.h vendor/llvm/dist/include/llvm/Object/Wasm.h vendor/llvm/dist/include/llvm/Support/CachePruning.h vendor/llvm/dist/include/llvm/Support/MemoryBuffer.h vendor/llvm/dist/include/llvm/Support/YAMLTraits.h vendor/llvm/dist/include/llvm/Target/TargetMachine.h vendor/llvm/dist/include/llvm/Target/TargetSelectionDAG.td vendor/llvm/dist/include/llvm/Transforms/Instrumentation.h vendor/llvm/dist/include/llvm/Transforms/Utils/CallPromotionUtils.h vendor/llvm/dist/include/llvm/module.modulemap vendor/llvm/dist/lib/Analysis/AliasAnalysis.cpp vendor/llvm/dist/lib/Analysis/AliasAnalysisEvaluator.cpp vendor/llvm/dist/lib/Analysis/BasicAliasAnalysis.cpp vendor/llvm/dist/lib/Analysis/CFGPrinter.cpp vendor/llvm/dist/lib/Analysis/GlobalsModRef.cpp vendor/llvm/dist/lib/Analysis/InlineCost.cpp vendor/llvm/dist/lib/Analysis/LoopAccessAnalysis.cpp vendor/llvm/dist/lib/Analysis/MemoryDependenceAnalysis.cpp vendor/llvm/dist/lib/Analysis/MemorySSA.cpp vendor/llvm/dist/lib/Analysis/ModuleSummaryAnalysis.cpp vendor/llvm/dist/lib/Analysis/ProfileSummaryInfo.cpp vendor/llvm/dist/lib/Analysis/ScalarEvolution.cpp vendor/llvm/dist/lib/Analysis/TargetTransformInfo.cpp vendor/llvm/dist/lib/Analysis/TypeBasedAliasAnalysis.cpp vendor/llvm/dist/lib/Bitcode/Writer/BitcodeWriter.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp vendor/llvm/dist/lib/CodeGen/CMakeLists.txt vendor/llvm/dist/lib/CodeGen/CodeGenPrepare.cpp vendor/llvm/dist/lib/CodeGen/GlobalISel/LegalizerHelper.cpp vendor/llvm/dist/lib/CodeGen/InlineSpiller.cpp vendor/llvm/dist/lib/CodeGen/LLVMTargetMachine.cpp vendor/llvm/dist/lib/CodeGen/MIRPrinter.cpp vendor/llvm/dist/lib/CodeGen/MachineBlockPlacement.cpp vendor/llvm/dist/lib/CodeGen/MachineOperand.cpp vendor/llvm/dist/lib/CodeGen/MachineVerifier.cpp vendor/llvm/dist/lib/CodeGen/README.txt vendor/llvm/dist/lib/CodeGen/RegAllocBasic.cpp vendor/llvm/dist/lib/CodeGen/RegAllocGreedy.cpp vendor/llvm/dist/lib/CodeGen/RegAllocPBQP.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp vendor/llvm/dist/lib/CodeGen/StackSlotColoring.cpp vendor/llvm/dist/lib/CodeGen/TargetLoweringBase.cpp vendor/llvm/dist/lib/CodeGen/VirtRegMap.cpp vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFContext.cpp vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFUnit.cpp vendor/llvm/dist/lib/Demangle/ItaniumDemangle.cpp vendor/llvm/dist/lib/FuzzMutate/IRMutator.cpp vendor/llvm/dist/lib/IR/ConstantFold.cpp vendor/llvm/dist/lib/IR/Function.cpp vendor/llvm/dist/lib/IR/Value.cpp vendor/llvm/dist/lib/MC/MCAsmStreamer.cpp vendor/llvm/dist/lib/MC/MCStreamer.cpp vendor/llvm/dist/lib/MC/WasmObjectWriter.cpp vendor/llvm/dist/lib/Object/ELF.cpp vendor/llvm/dist/lib/Object/WasmObjectFile.cpp vendor/llvm/dist/lib/Object/WindowsResource.cpp vendor/llvm/dist/lib/ObjectYAML/WasmYAML.cpp vendor/llvm/dist/lib/Passes/LLVMBuild.txt vendor/llvm/dist/lib/Support/APFloat.cpp vendor/llvm/dist/lib/Support/CachePruning.cpp vendor/llvm/dist/lib/Support/MemoryBuffer.cpp vendor/llvm/dist/lib/Support/StringRef.cpp vendor/llvm/dist/lib/Support/TargetParser.cpp vendor/llvm/dist/lib/Support/YAMLTraits.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64AsmPrinter.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64FastISel.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64Subtarget.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64Subtarget.h vendor/llvm/dist/lib/Target/AArch64/AArch64SystemOperands.td vendor/llvm/dist/lib/Target/AArch64/AArch64TargetMachine.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64TargetMachine.h vendor/llvm/dist/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUISelLowering.h vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUTargetMachine.h vendor/llvm/dist/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp vendor/llvm/dist/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp vendor/llvm/dist/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h vendor/llvm/dist/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.td vendor/llvm/dist/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp vendor/llvm/dist/lib/Target/ARC/ARCTargetMachine.cpp vendor/llvm/dist/lib/Target/ARC/ARCTargetMachine.h vendor/llvm/dist/lib/Target/ARM/ARM.h vendor/llvm/dist/lib/Target/ARM/ARM.td vendor/llvm/dist/lib/Target/ARM/ARMFastISel.cpp vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.h vendor/llvm/dist/lib/Target/ARM/ARMInstrInfo.td vendor/llvm/dist/lib/Target/ARM/ARMInstrThumb2.td vendor/llvm/dist/lib/Target/ARM/ARMInstructionSelector.cpp vendor/llvm/dist/lib/Target/ARM/ARMLegalizerInfo.cpp vendor/llvm/dist/lib/Target/ARM/ARMRegisterBankInfo.cpp vendor/llvm/dist/lib/Target/ARM/ARMSubtarget.cpp vendor/llvm/dist/lib/Target/ARM/ARMSubtarget.h vendor/llvm/dist/lib/Target/ARM/ARMTargetMachine.cpp vendor/llvm/dist/lib/Target/ARM/ARMTargetMachine.h vendor/llvm/dist/lib/Target/ARM/ARMTargetTransformInfo.cpp vendor/llvm/dist/lib/Target/ARM/ARMTargetTransformInfo.h vendor/llvm/dist/lib/Target/ARM/AsmParser/ARMAsmParser.cpp vendor/llvm/dist/lib/Target/ARM/Disassembler/ARMDisassembler.cpp vendor/llvm/dist/lib/Target/ARM/Thumb2SizeReduction.cpp vendor/llvm/dist/lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonISelLowering.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonISelLowering.h vendor/llvm/dist/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonPatterns.td vendor/llvm/dist/lib/Target/Hexagon/HexagonRegisterInfo.td vendor/llvm/dist/lib/Target/Hexagon/HexagonSubtarget.h vendor/llvm/dist/lib/Target/Hexagon/HexagonTargetMachine.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonTargetMachine.h vendor/llvm/dist/lib/Target/Lanai/LanaiTargetMachine.cpp vendor/llvm/dist/lib/Target/Lanai/LanaiTargetMachine.h vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp vendor/llvm/dist/lib/Target/Mips/MipsRegisterInfo.td vendor/llvm/dist/lib/Target/Mips/MipsTargetMachine.cpp vendor/llvm/dist/lib/Target/Mips/MipsTargetMachine.h vendor/llvm/dist/lib/Target/NVPTX/NVPTXTargetMachine.cpp vendor/llvm/dist/lib/Target/NVPTX/NVPTXTargetMachine.h vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCISelLowering.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCMIPeephole.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCTargetMachine.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCTargetMachine.h vendor/llvm/dist/lib/Target/SystemZ/SystemZTargetMachine.cpp vendor/llvm/dist/lib/Target/SystemZ/SystemZTargetMachine.h vendor/llvm/dist/lib/Target/TargetMachine.cpp vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyTargetMachine.h vendor/llvm/dist/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp vendor/llvm/dist/lib/Target/X86/X86.td vendor/llvm/dist/lib/Target/X86/X86DomainReassignment.cpp vendor/llvm/dist/lib/Target/X86/X86ISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist/lib/Target/X86/X86Instr3DNow.td vendor/llvm/dist/lib/Target/X86/X86InstrFormats.td vendor/llvm/dist/lib/Target/X86/X86InstrInfo.td vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td vendor/llvm/dist/lib/Target/X86/X86SelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/X86/X86Subtarget.cpp vendor/llvm/dist/lib/Target/X86/X86Subtarget.h vendor/llvm/dist/lib/Target/X86/X86TargetMachine.cpp vendor/llvm/dist/lib/Target/X86/X86TargetMachine.h vendor/llvm/dist/lib/Target/XCore/XCoreTargetMachine.cpp vendor/llvm/dist/lib/Target/XCore/XCoreTargetMachine.h vendor/llvm/dist/lib/Transforms/IPO/PartialInlining.cpp vendor/llvm/dist/lib/Transforms/IPO/SampleProfile.cpp vendor/llvm/dist/lib/Transforms/IPO/WholeProgramDevirt.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCalls.cpp vendor/llvm/dist/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp vendor/llvm/dist/lib/Transforms/Scalar/CallSiteSplitting.cpp vendor/llvm/dist/lib/Transforms/Scalar/JumpThreading.cpp vendor/llvm/dist/lib/Transforms/Scalar/LoopSink.cpp vendor/llvm/dist/lib/Transforms/Scalar/LoopUnrollPass.cpp vendor/llvm/dist/lib/Transforms/Scalar/MemCpyOptimizer.cpp vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp vendor/llvm/dist/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp vendor/llvm/dist/lib/Transforms/Utils/CallPromotionUtils.cpp vendor/llvm/dist/lib/Transforms/Utils/LoopUnrollPeel.cpp vendor/llvm/dist/lib/Transforms/Utils/SimplifyCFG.cpp vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp vendor/llvm/dist/lib/Transforms/Vectorize/SLPVectorizer.cpp vendor/llvm/dist/test/Analysis/BasicAA/args-rets-allocas-loads.ll vendor/llvm/dist/test/Analysis/BasicAA/call-attrs.ll vendor/llvm/dist/test/Analysis/BasicAA/cs-cs-arm.ll vendor/llvm/dist/test/Analysis/BasicAA/cs-cs.ll vendor/llvm/dist/test/Analysis/MemorySSA/volatile-clobber.ll vendor/llvm/dist/test/Analysis/ValueTracking/memory-dereferenceable.ll vendor/llvm/dist/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll vendor/llvm/dist/test/CodeGen/AArch64/GlobalISel/translate-gep.ll vendor/llvm/dist/test/CodeGen/AArch64/arm64-jumptable.ll vendor/llvm/dist/test/CodeGen/AArch64/arm64-memset-to-bzero.ll vendor/llvm/dist/test/CodeGen/AArch64/arm64-neon-2velem.ll vendor/llvm/dist/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll vendor/llvm/dist/test/CodeGen/AArch64/ldst-paired-aliasing.ll vendor/llvm/dist/test/CodeGen/AMDGPU/amdgpu.private-memory.ll vendor/llvm/dist/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir vendor/llvm/dist/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir vendor/llvm/dist/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir vendor/llvm/dist/test/CodeGen/ARM/avoid-cpsr-rmw.ll vendor/llvm/dist/test/CodeGen/Hexagon/expand-vstorerw-undef.ll vendor/llvm/dist/test/CodeGen/Hexagon/v60-cur.ll vendor/llvm/dist/test/CodeGen/Hexagon/vect/vect-infloop.ll vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/extractelement.ll vendor/llvm/dist/test/CodeGen/PowerPC/cmp_elimination.ll vendor/llvm/dist/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll vendor/llvm/dist/test/CodeGen/X86/avg-mask.ll vendor/llvm/dist/test/CodeGen/X86/avg.ll vendor/llvm/dist/test/CodeGen/X86/avx512-calling-conv.ll vendor/llvm/dist/test/CodeGen/X86/avx512-ext.ll vendor/llvm/dist/test/CodeGen/X86/avx512-extract-subvector-load-store.ll vendor/llvm/dist/test/CodeGen/X86/avx512-insert-extract.ll vendor/llvm/dist/test/CodeGen/X86/avx512-insert-extract_i1.ll vendor/llvm/dist/test/CodeGen/X86/avx512-mask-op.ll vendor/llvm/dist/test/CodeGen/X86/avx512-schedule.ll vendor/llvm/dist/test/CodeGen/X86/avx512-shuffles/partial_permute.ll vendor/llvm/dist/test/CodeGen/X86/avx512-skx-insert-subvec.ll vendor/llvm/dist/test/CodeGen/X86/avx512-vec-cmp.ll vendor/llvm/dist/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll vendor/llvm/dist/test/CodeGen/X86/bitcast-and-setcc-128.ll vendor/llvm/dist/test/CodeGen/X86/bitcast-setcc-128.ll vendor/llvm/dist/test/CodeGen/X86/combine-and.ll vendor/llvm/dist/test/CodeGen/X86/combine-or.ll vendor/llvm/dist/test/CodeGen/X86/darwin-bzero.ll vendor/llvm/dist/test/CodeGen/X86/extractelement-index.ll vendor/llvm/dist/test/CodeGen/X86/fma-fneg-combine.ll vendor/llvm/dist/test/CodeGen/X86/fmsubadd-combine.ll vendor/llvm/dist/test/CodeGen/X86/fold-vector-sext-crash.ll vendor/llvm/dist/test/CodeGen/X86/horizontal-reduce-smax.ll vendor/llvm/dist/test/CodeGen/X86/horizontal-reduce-smin.ll vendor/llvm/dist/test/CodeGen/X86/horizontal-reduce-umax.ll vendor/llvm/dist/test/CodeGen/X86/horizontal-reduce-umin.ll vendor/llvm/dist/test/CodeGen/X86/known-bits-vector.ll vendor/llvm/dist/test/CodeGen/X86/machinesink-merge-debuginfo.ll vendor/llvm/dist/test/CodeGen/X86/machinesink-null-debuginfo.ll vendor/llvm/dist/test/CodeGen/X86/masked_gather_scatter.ll vendor/llvm/dist/test/CodeGen/X86/popcnt.ll vendor/llvm/dist/test/CodeGen/X86/prefetch.ll vendor/llvm/dist/test/CodeGen/X86/shuffle-strided-with-offset-128.ll vendor/llvm/dist/test/CodeGen/X86/shuffle-strided-with-offset-256.ll vendor/llvm/dist/test/CodeGen/X86/shuffle-strided-with-offset-512.ll vendor/llvm/dist/test/CodeGen/X86/shuffle-vs-trunc-128.ll vendor/llvm/dist/test/CodeGen/X86/shuffle-vs-trunc-256.ll vendor/llvm/dist/test/CodeGen/X86/shuffle-vs-trunc-512.ll vendor/llvm/dist/test/CodeGen/X86/var-permute-256.ll vendor/llvm/dist/test/CodeGen/X86/var-permute-512.ll vendor/llvm/dist/test/CodeGen/X86/vector-compare-results.ll vendor/llvm/dist/test/CodeGen/X86/vector-half-conversions.ll vendor/llvm/dist/test/CodeGen/X86/vector-rotate-128.ll vendor/llvm/dist/test/CodeGen/X86/vector-shift-ashr-128.ll vendor/llvm/dist/test/CodeGen/X86/vector-shift-lshr-128.ll vendor/llvm/dist/test/CodeGen/X86/vector-shift-shl-128.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-128-v16.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-128-v8.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v16.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v32.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v4.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v8.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-512-v32.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-v1.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-variable-128.ll vendor/llvm/dist/test/CodeGen/X86/vector-trunc.ll vendor/llvm/dist/test/CodeGen/X86/vector-zext.ll vendor/llvm/dist/test/CodeGen/X86/vselect.ll vendor/llvm/dist/test/DebugInfo/X86/dwarfdump-str-offsets-dwp.s vendor/llvm/dist/test/DebugInfo/X86/dwarfdump-str-offsets-invalid-3.s vendor/llvm/dist/test/DebugInfo/X86/dwarfdump-str-offsets-invalid-4.s vendor/llvm/dist/test/DebugInfo/X86/dwarfdump-str-offsets-macho.s vendor/llvm/dist/test/DebugInfo/X86/dwarfdump-str-offsets.s vendor/llvm/dist/test/Instrumentation/HWAddressSanitizer/basic.ll vendor/llvm/dist/test/Instrumentation/HWAddressSanitizer/with-calls.ll vendor/llvm/dist/test/MC/AArch64/arm64-system-encoding.s vendor/llvm/dist/test/MC/AArch64/basic-a64-diagnostics.s vendor/llvm/dist/test/MC/AArch64/dot-req.s vendor/llvm/dist/test/MC/AMDGPU/ds.s vendor/llvm/dist/test/MC/AMDGPU/expressions.s vendor/llvm/dist/test/MC/AMDGPU/trap.s vendor/llvm/dist/test/MC/AMDGPU/vop1-gfx9-err.s vendor/llvm/dist/test/MC/AMDGPU/vop3p-err.s vendor/llvm/dist/test/MC/COFF/align-nops.s vendor/llvm/dist/test/MC/Disassembler/AArch64/basic-a64-instructions.txt vendor/llvm/dist/test/MC/Disassembler/AMDGPU/ds_vi.txt vendor/llvm/dist/test/MC/Disassembler/AMDGPU/trap_gfx9.txt vendor/llvm/dist/test/MC/Disassembler/AMDGPU/trap_vi.txt vendor/llvm/dist/test/MC/Disassembler/X86/x86-32.txt vendor/llvm/dist/test/MC/ELF/align-nops.s vendor/llvm/dist/test/MC/MachO/x86_32-optimal_nop.s vendor/llvm/dist/test/MC/Mips/eva/invalid.s vendor/llvm/dist/test/MC/WebAssembly/weak-alias.ll vendor/llvm/dist/test/MC/X86/3DNow.s vendor/llvm/dist/test/MC/X86/AlignedBundling/different-sections.s vendor/llvm/dist/test/MC/X86/AlignedBundling/long-nop-pad.s vendor/llvm/dist/test/MC/X86/AlignedBundling/misaligned-bundle-group.s vendor/llvm/dist/test/MC/X86/AlignedBundling/misaligned-bundle.s vendor/llvm/dist/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s vendor/llvm/dist/test/MC/X86/AlignedBundling/pad-bundle-groups.s vendor/llvm/dist/test/MC/X86/AlignedBundling/relax-in-bundle-group.s vendor/llvm/dist/test/MC/X86/AlignedBundling/single-inst-bundling.s vendor/llvm/dist/test/MC/X86/x86_long_nop.s vendor/llvm/dist/test/TableGen/GlobalISelEmitter.td vendor/llvm/dist/test/TableGen/intrinsic-long-name.td vendor/llvm/dist/test/TableGen/intrinsic-struct.td vendor/llvm/dist/test/TableGen/intrinsic-varargs.td vendor/llvm/dist/test/ThinLTO/X86/cache.ll vendor/llvm/dist/test/Transforms/CodeGenPrepare/section.ll vendor/llvm/dist/test/Transforms/GVN/tbaa.ll vendor/llvm/dist/test/Transforms/Inline/redundant-loads.ll vendor/llvm/dist/test/Transforms/InstCombine/2011-09-03-Trampoline.ll vendor/llvm/dist/test/Transforms/JumpThreading/guards.ll vendor/llvm/dist/test/Transforms/NewGVN/tbaa.ll vendor/llvm/dist/test/Transforms/PGOProfile/icp_covariant_call_return.ll vendor/llvm/dist/test/Transforms/PGOProfile/icp_covariant_invoke_return.ll vendor/llvm/dist/test/Transforms/PGOProfile/icp_invoke.ll vendor/llvm/dist/test/Transforms/PGOProfile/icp_invoke_nouse.ll vendor/llvm/dist/test/Transforms/PGOProfile/icp_vararg.ll vendor/llvm/dist/test/Transforms/PGOProfile/indirect_call_promotion.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/jumbled-load-multiuse.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/jumbled-load.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/store-jumbled.ll vendor/llvm/dist/test/Transforms/SampleProfile/entry_counts.ll vendor/llvm/dist/test/tools/llvm-cvtres/machine.test vendor/llvm/dist/test/tools/llvm-cvtres/symbols.test vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/lookup.s vendor/llvm/dist/test/tools/llvm-readobj/mips-got.test vendor/llvm/dist/test/tools/llvm-readobj/mips-plt.test vendor/llvm/dist/tools/llvm-dwarfdump/llvm-dwarfdump.cpp vendor/llvm/dist/tools/llvm-lto/llvm-lto.cpp vendor/llvm/dist/tools/llvm-objcopy/Object.cpp vendor/llvm/dist/tools/llvm-objcopy/Object.h vendor/llvm/dist/tools/llvm-objcopy/llvm-objcopy.cpp vendor/llvm/dist/tools/llvm-readobj/ELFDumper.cpp vendor/llvm/dist/tools/llvm-readobj/WasmDumper.cpp vendor/llvm/dist/tools/opt-viewer/optrecord.py vendor/llvm/dist/unittests/ADT/APFloatTest.cpp vendor/llvm/dist/unittests/ADT/StringRefTest.cpp vendor/llvm/dist/unittests/CodeGen/MachineOperandTest.cpp vendor/llvm/dist/unittests/ExecutionEngine/Orc/CMakeLists.txt vendor/llvm/dist/unittests/Support/CachePruningTest.cpp vendor/llvm/dist/unittests/Support/MemoryBufferTest.cpp vendor/llvm/dist/unittests/Support/TargetParserTest.cpp vendor/llvm/dist/unittests/Support/YAMLIOTest.cpp vendor/llvm/dist/utils/TableGen/CMakeLists.txt vendor/llvm/dist/utils/TableGen/CodeGenDAGPatterns.cpp vendor/llvm/dist/utils/TableGen/CodeGenDAGPatterns.h vendor/llvm/dist/utils/TableGen/CodeGenIntrinsics.h vendor/llvm/dist/utils/TableGen/CodeGenTarget.cpp vendor/llvm/dist/utils/TableGen/CodeGenTarget.h vendor/llvm/dist/utils/TableGen/GlobalISelEmitter.cpp vendor/llvm/dist/utils/TableGen/IntrinsicEmitter.cpp vendor/llvm/dist/utils/docker/build_docker_image.sh vendor/llvm/dist/utils/docker/scripts/build_install_llvm.sh vendor/llvm/dist/utils/git-svn/git-llvm vendor/llvm/dist/utils/update_mir_test_checks.py Modified: vendor/llvm/dist/docs/Extensions.rst ============================================================================== --- vendor/llvm/dist/docs/Extensions.rst Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/docs/Extensions.rst Sun Dec 24 01:00:08 2017 (r327122) @@ -288,3 +288,31 @@ standard stack probe emission. The MSVC environment does not emit code for VLAs currently. +Windows on ARM64 +---------------- + +Stack Probe Emission +^^^^^^^^^^^^^^^^^^^^ + +The reference implementation (Microsoft Visual Studio 2017) emits stack probes +in the following fashion: + +.. code-block:: gas + + mov x15, #constant + bl __chkstk + sub sp, sp, x15, lsl #4 + +However, this has the limitation of 256 MiB (±128MiB). In order to accommodate +larger binaries, LLVM supports the use of ``-mcode-model=large`` to allow a 8GiB +(±4GiB) range via a slight deviation. It will generate an indirect jump as +follows: + +.. code-block:: gas + + mov x15, #constant + adrp x16, __chkstk + add x16, x16, :lo12:__chkstk + blr x16 + sub sp, sp, x15, lsl #4 + Modified: vendor/llvm/dist/docs/MIRLangRef.rst ============================================================================== --- vendor/llvm/dist/docs/MIRLangRef.rst Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/docs/MIRLangRef.rst Sun Dec 24 01:00:08 2017 (r327122) @@ -692,6 +692,50 @@ The syntax is: EH_LABEL <mcsymbol Ltmp1> +CFIIndex Operands +^^^^^^^^^^^^^^^^^ + +A CFI Index operand is holding an index into a per-function side-table, +``MachineFunction::getFrameInstructions()``, which references all the frame +instructions in a ``MachineFunction``. A ``CFI_INSTRUCTION`` may look like it +contains multiple operands, but the only operand it contains is the CFI Index. +The other operands are tracked by the ``MCCFIInstruction`` object. + +The syntax is: + +.. code-block:: text + + CFI_INSTRUCTION offset %w30, -16 + +which may be emitted later in the MC layer as: + +.. code-block:: text + + .cfi_offset w30, -16 + +IntrinsicID Operands +^^^^^^^^^^^^^^^^^^^^ + +An Intrinsic ID operand contains a generic intrinsic ID or a target-specific ID. + +The syntax for the ``returnaddress`` intrinsic is: + +.. code-block:: text + + %x0 = COPY intrinsic(@llvm.returnaddress) + +Predicate Operands +^^^^^^^^^^^^^^^^^^ + +A Predicate operand contains an IR predicate from ``CmpInst::Predicate``, like +``ICMP_EQ``, etc. + +For an int eq predicate ``ICMP_EQ``, the syntax is: + +.. code-block:: text + + %2:gpr(s32) = G_ICMP intpred(eq), %0, %1 + .. TODO: Describe the parsers default behaviour when optional YAML attributes are missing. .. TODO: Describe the syntax for the bundled instructions. @@ -702,7 +746,6 @@ The syntax is: .. TODO: Describe the syntax of the stack object machine operands and their YAML definitions. .. TODO: Describe the syntax of the block address machine operands. -.. TODO: Describe the syntax of the CFI index machine operands. .. TODO: Describe the syntax of the metadata machine operands, and the instructions debug location attribute. .. TODO: Describe the syntax of the register live out machine operands. Modified: vendor/llvm/dist/docs/tutorial/LangImpl09.rst ============================================================================== --- vendor/llvm/dist/docs/tutorial/LangImpl09.rst Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/docs/tutorial/LangImpl09.rst Sun Dec 24 01:00:08 2017 (r327122) @@ -197,7 +197,7 @@ expressions: if (DblTy) return DblTy; - DblTy = DBuilder->createBasicType("double", 64, 64, dwarf::DW_ATE_float); + DblTy = DBuilder->createBasicType("double", 64, dwarf::DW_ATE_float); return DblTy; } @@ -208,7 +208,8 @@ And then later on in ``main`` when we're constructing DBuilder = new DIBuilder(*TheModule); KSDbgInfo.TheCU = DBuilder->createCompileUnit( - dwarf::DW_LANG_C, "fib.ks", ".", "Kaleidoscope Compiler", 0, "", 0); + dwarf::DW_LANG_C, DBuilder->createFile("fib.ks", "."), + "Kaleidoscope Compiler", 0, "", 0); There are a couple of things to note here. First, while we're producing a compile unit for a language called Kaleidoscope we used the language Modified: vendor/llvm/dist/examples/Kaleidoscope/CMakeLists.txt ============================================================================== --- vendor/llvm/dist/examples/Kaleidoscope/CMakeLists.txt Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/examples/Kaleidoscope/CMakeLists.txt Sun Dec 24 01:00:08 2017 (r327122) @@ -14,3 +14,4 @@ add_subdirectory(Chapter5) add_subdirectory(Chapter6) add_subdirectory(Chapter7) add_subdirectory(Chapter8) +add_subdirectory(Chapter9) Modified: vendor/llvm/dist/examples/Kaleidoscope/Chapter9/toy.cpp ============================================================================== --- vendor/llvm/dist/examples/Kaleidoscope/Chapter9/toy.cpp Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/examples/Kaleidoscope/Chapter9/toy.cpp Sun Dec 24 01:00:08 2017 (r327122) @@ -823,7 +823,7 @@ DIType *DebugInfo::getDoubleTy() { if (DblTy) return DblTy; - DblTy = DBuilder->createBasicType("double", 64, 64, dwarf::DW_ATE_float); + DblTy = DBuilder->createBasicType("double", 64, dwarf::DW_ATE_float); return DblTy; } @@ -1436,7 +1436,8 @@ int main() { // Currently down as "fib.ks" as a filename since we're redirecting stdin // but we'd like actual source locations. KSDbgInfo.TheCU = DBuilder->createCompileUnit( - dwarf::DW_LANG_C, "fib.ks", ".", "Kaleidoscope Compiler", 0, "", 0); + dwarf::DW_LANG_C, DBuilder->createFile("fib.ks", "."), + "Kaleidoscope Compiler", 0, "", 0); // Run the main "interpreter loop" now. MainLoop(); Modified: vendor/llvm/dist/include/llvm-c/lto.h ============================================================================== --- vendor/llvm/dist/include/llvm-c/lto.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm-c/lto.h Sun Dec 24 01:00:08 2017 (r327122) @@ -757,17 +757,17 @@ extern void thinlto_codegen_add_cross_referenced_symbo * @ingroup LLVMCTLTO * * These entry points control the ThinLTO cache. The cache is intended to - * support incremental build, and thus needs to be persistent accross build. - * The client enabled the cache by supplying a path to an existing directory. + * support incremental builds, and thus needs to be persistent across builds. + * The client enables the cache by supplying a path to an existing directory. * The code generator will use this to store objects files that may be reused * during a subsequent build. * To avoid filling the disk space, a few knobs are provided: - * - The pruning interval limit the frequency at which the garbage collector - * will try to scan the cache directory to prune it from expired entries. - * Setting to -1 disable the pruning (default). + * - The pruning interval limits the frequency at which the garbage collector + * will try to scan the cache directory to prune expired entries. + * Setting to a negative number disables the pruning. * - The pruning expiration time indicates to the garbage collector how old an * entry needs to be to be removed. - * - Finally, the garbage collector can be instructed to prune the cache till + * - Finally, the garbage collector can be instructed to prune the cache until * the occupied space goes below a threshold. * @{ */ @@ -782,7 +782,7 @@ extern void thinlto_codegen_set_cache_dir(thinlto_code const char *cache_dir); /** - * Sets the cache pruning interval (in seconds). A negative value disable the + * Sets the cache pruning interval (in seconds). A negative value disables the * pruning. An unspecified default value will be applied, and a value of 0 will * be ignored. * Modified: vendor/llvm/dist/include/llvm/Analysis/AliasAnalysis.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/AliasAnalysis.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/Analysis/AliasAnalysis.h Sun Dec 24 01:00:08 2017 (r327122) @@ -95,46 +95,81 @@ enum AliasResult { /// /// This is no access at all, a modification, a reference, or both /// a modification and a reference. These are specifically structured such that -/// they form a two bit matrix and bit-tests for 'mod' or 'ref' +/// they form a three bit matrix and bit-tests for 'mod' or 'ref' or 'must' /// work with any of the possible values. - enum class ModRefInfo { + /// Must is provided for completeness, but no routines will return only + /// Must today. See definition of Must below. + Must = 0, + /// The access may reference the value stored in memory, + /// a mustAlias relation was found, and no mayAlias or partialAlias found. + MustRef = 1, + /// The access may modify the value stored in memory, + /// a mustAlias relation was found, and no mayAlias or partialAlias found. + MustMod = 2, + /// The access may reference, modify or both the value stored in memory, + /// a mustAlias relation was found, and no mayAlias or partialAlias found. + MustModRef = MustRef | MustMod, /// The access neither references nor modifies the value stored in memory. - NoModRef = 0, + NoModRef = 4, /// The access may reference the value stored in memory. - Ref = 1, + Ref = NoModRef | MustRef, /// The access may modify the value stored in memory. - Mod = 2, + Mod = NoModRef | MustMod, /// The access may reference and may modify the value stored in memory. ModRef = Ref | Mod, + + /// About Must: + /// Must is set in a best effort manner. + /// We usually do not try our best to infer Must, instead it is merely + /// another piece of "free" information that is presented when available. + /// Must set means there was certainly a MustAlias found. For calls, + /// where multiple arguments are checked (argmemonly), this translates to + /// only MustAlias or NoAlias was found. + /// Must is not set for RAR accesses, even if the two locations must + /// alias. The reason is that two read accesses translate to an early return + /// of NoModRef. An additional alias check to set Must may be + /// expensive. Other cases may also not set Must(e.g. callCapturesBefore). + /// We refer to Must being *set* when the most significant bit is *cleared*. + /// Conversely we *clear* Must information by *setting* the Must bit to 1. }; LLVM_NODISCARD inline bool isNoModRef(const ModRefInfo MRI) { - return MRI == ModRefInfo::NoModRef; + return (static_cast<int>(MRI) & static_cast<int>(ModRefInfo::MustModRef)) == + static_cast<int>(ModRefInfo::Must); } LLVM_NODISCARD inline bool isModOrRefSet(const ModRefInfo MRI) { - return static_cast<int>(MRI) & static_cast<int>(ModRefInfo::ModRef); + return static_cast<int>(MRI) & static_cast<int>(ModRefInfo::MustModRef); } LLVM_NODISCARD inline bool isModAndRefSet(const ModRefInfo MRI) { - return (static_cast<int>(MRI) & static_cast<int>(ModRefInfo::ModRef)) == - static_cast<int>(ModRefInfo::ModRef); + return (static_cast<int>(MRI) & static_cast<int>(ModRefInfo::MustModRef)) == + static_cast<int>(ModRefInfo::MustModRef); } LLVM_NODISCARD inline bool isModSet(const ModRefInfo MRI) { - return static_cast<int>(MRI) & static_cast<int>(ModRefInfo::Mod); + return static_cast<int>(MRI) & static_cast<int>(ModRefInfo::MustMod); } LLVM_NODISCARD inline bool isRefSet(const ModRefInfo MRI) { - return static_cast<int>(MRI) & static_cast<int>(ModRefInfo::Ref); + return static_cast<int>(MRI) & static_cast<int>(ModRefInfo::MustRef); } +LLVM_NODISCARD inline bool isMustSet(const ModRefInfo MRI) { + return !(static_cast<int>(MRI) & static_cast<int>(ModRefInfo::NoModRef)); +} LLVM_NODISCARD inline ModRefInfo setMod(const ModRefInfo MRI) { - return ModRefInfo(static_cast<int>(MRI) | static_cast<int>(ModRefInfo::Mod)); + return ModRefInfo(static_cast<int>(MRI) | + static_cast<int>(ModRefInfo::MustMod)); } LLVM_NODISCARD inline ModRefInfo setRef(const ModRefInfo MRI) { - return ModRefInfo(static_cast<int>(MRI) | static_cast<int>(ModRefInfo::Ref)); + return ModRefInfo(static_cast<int>(MRI) | + static_cast<int>(ModRefInfo::MustRef)); } +LLVM_NODISCARD inline ModRefInfo setMust(const ModRefInfo MRI) { + return ModRefInfo(static_cast<int>(MRI) & + static_cast<int>(ModRefInfo::MustModRef)); +} LLVM_NODISCARD inline ModRefInfo setModAndRef(const ModRefInfo MRI) { return ModRefInfo(static_cast<int>(MRI) | - static_cast<int>(ModRefInfo::ModRef)); + static_cast<int>(ModRefInfo::MustModRef)); } LLVM_NODISCARD inline ModRefInfo clearMod(const ModRefInfo MRI) { return ModRefInfo(static_cast<int>(MRI) & static_cast<int>(ModRefInfo::Ref)); @@ -142,6 +177,10 @@ LLVM_NODISCARD inline ModRefInfo clearMod(const ModRef LLVM_NODISCARD inline ModRefInfo clearRef(const ModRefInfo MRI) { return ModRefInfo(static_cast<int>(MRI) & static_cast<int>(ModRefInfo::Mod)); } +LLVM_NODISCARD inline ModRefInfo clearMust(const ModRefInfo MRI) { + return ModRefInfo(static_cast<int>(MRI) | + static_cast<int>(ModRefInfo::NoModRef)); +} LLVM_NODISCARD inline ModRefInfo unionModRef(const ModRefInfo MRI1, const ModRefInfo MRI2) { return ModRefInfo(static_cast<int>(MRI1) | static_cast<int>(MRI2)); @@ -160,11 +199,11 @@ enum FunctionModRefLocation { /// Base case is no access to memory. FMRL_Nowhere = 0, /// Access to memory via argument pointers. - FMRL_ArgumentPointees = 4, + FMRL_ArgumentPointees = 8, /// Memory that is inaccessible via LLVM IR. - FMRL_InaccessibleMem = 8, + FMRL_InaccessibleMem = 16, /// Access to any memory. - FMRL_Anywhere = 16 | FMRL_InaccessibleMem | FMRL_ArgumentPointees + FMRL_Anywhere = 32 | FMRL_InaccessibleMem | FMRL_ArgumentPointees }; /// Summary of how a function affects memory in the program. @@ -344,7 +383,7 @@ class AAResults { (public) /// result's bits are set to indicate the allowed aliasing ModRef kinds. Note /// that these bits do not necessarily account for the overall behavior of /// the function, but rather only provide additional per-argument - /// information. + /// information. This never sets ModRefInfo::Must. ModRefInfo getArgModRefInfo(ImmutableCallSite CS, unsigned ArgIdx); /// Return the behavior of the given call site. @@ -624,6 +663,8 @@ class AAResults { (public) /// or reads the specified memory location \p MemLoc before instruction \p I /// in a BasicBlock. An ordered basic block \p OBB can be used to speed up /// instruction ordering queries inside the BasicBlock containing \p I. + /// Early exits in callCapturesBefore may lead to ModRefInfo::Must not being + /// set. ModRefInfo callCapturesBefore(const Instruction *I, const MemoryLocation &MemLoc, DominatorTree *DT, OrderedBasicBlock *OBB = nullptr); Modified: vendor/llvm/dist/include/llvm/Analysis/AliasAnalysisEvaluator.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/AliasAnalysisEvaluator.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/Analysis/AliasAnalysisEvaluator.h Sun Dec 24 01:00:08 2017 (r327122) @@ -35,19 +35,23 @@ class AAEvaluator : public PassInfoMixin<AAEvaluator> int64_t FunctionCount; int64_t NoAliasCount, MayAliasCount, PartialAliasCount, MustAliasCount; int64_t NoModRefCount, ModCount, RefCount, ModRefCount; + int64_t MustCount, MustRefCount, MustModCount, MustModRefCount; public: AAEvaluator() : FunctionCount(), NoAliasCount(), MayAliasCount(), PartialAliasCount(), MustAliasCount(), NoModRefCount(), ModCount(), RefCount(), - ModRefCount() {} + ModRefCount(), MustCount(), MustRefCount(), MustModCount(), + MustModRefCount() {} AAEvaluator(AAEvaluator &&Arg) : FunctionCount(Arg.FunctionCount), NoAliasCount(Arg.NoAliasCount), MayAliasCount(Arg.MayAliasCount), PartialAliasCount(Arg.PartialAliasCount), MustAliasCount(Arg.MustAliasCount), NoModRefCount(Arg.NoModRefCount), ModCount(Arg.ModCount), RefCount(Arg.RefCount), - ModRefCount(Arg.ModRefCount) { + ModRefCount(Arg.ModRefCount), MustCount(Arg.MustCount), + MustRefCount(Arg.MustRefCount), MustModCount(Arg.MustModCount), + MustModRefCount(Arg.MustModRefCount) { Arg.FunctionCount = 0; } ~AAEvaluator(); Modified: vendor/llvm/dist/include/llvm/Analysis/LoopAccessAnalysis.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/LoopAccessAnalysis.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/Analysis/LoopAccessAnalysis.h Sun Dec 24 01:00:08 2017 (r327122) @@ -667,21 +667,6 @@ int64_t getPtrStride(PredicatedScalarEvolution &PSE, V const ValueToValueMap &StridesMap = ValueToValueMap(), bool Assume = false, bool ShouldCheckWrap = true); -/// \brief Attempt to sort the 'loads' in \p VL and return the sorted values in -/// \p Sorted. -/// -/// Returns 'false' if sorting is not legal or feasible, otherwise returns -/// 'true'. If \p Mask is not null, it also returns the \p Mask which is the -/// shuffle mask for actual memory access order. -/// -/// For example, for a given VL of memory accesses in program order, a[i+2], -/// a[i+0], a[i+1] and a[i+3], this function will sort the VL and save the -/// sorted value in 'Sorted' as a[i+0], a[i+1], a[i+2], a[i+3] and saves the -/// mask for actual memory accesses in program order in 'Mask' as <2,0,1,3> -bool sortLoadAccesses(ArrayRef<Value *> VL, const DataLayout &DL, - ScalarEvolution &SE, SmallVectorImpl<Value *> &Sorted, - SmallVectorImpl<unsigned> *Mask = nullptr); - /// \brief Returns true if the memory operations \p A and \p B are consecutive. /// This is a simple API that does not depend on the analysis pass. bool isConsecutiveAccess(Value *A, Value *B, const DataLayout &DL, Modified: vendor/llvm/dist/include/llvm/Analysis/MemoryDependenceAnalysis.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/MemoryDependenceAnalysis.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/Analysis/MemoryDependenceAnalysis.h Sun Dec 24 01:00:08 2017 (r327122) @@ -407,6 +407,12 @@ class MemoryDependenceResults { (public) void getNonLocalPointerDependency(Instruction *QueryInst, SmallVectorImpl<NonLocalDepResult> &Result); + /// Perform a dependency query specifically for QueryInst's access to Loc. + /// The other comments for getNonLocalPointerDependency apply here as well. + void getNonLocalPointerDependencyFrom(Instruction *QueryInst, + const MemoryLocation &Loc, bool isLoad, + SmallVectorImpl<NonLocalDepResult> &Result); + /// Removes an instruction from the dependence analysis, updating the /// dependence of instructions that previously depended on it. void removeInstruction(Instruction *InstToRemove); Modified: vendor/llvm/dist/include/llvm/Analysis/ProfileSummaryInfo.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/ProfileSummaryInfo.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/Analysis/ProfileSummaryInfo.h Sun Dec 24 01:00:08 2017 (r327122) @@ -92,12 +92,12 @@ class ProfileSummaryInfo { (public) bool hasHugeWorkingSetSize(); /// \brief Returns true if \p F has hot function entry. bool isFunctionEntryHot(const Function *F); - /// Returns true if \p F has hot function entry or hot call edge. - bool isFunctionHotInCallGraph(const Function *F); + /// Returns true if \p F contains hot code. + bool isFunctionHotInCallGraph(const Function *F, BlockFrequencyInfo &BFI); /// \brief Returns true if \p F has cold function entry. bool isFunctionEntryCold(const Function *F); - /// Returns true if \p F has cold function entry or cold call edge. - bool isFunctionColdInCallGraph(const Function *F); + /// Returns true if \p F contains only cold code. + bool isFunctionColdInCallGraph(const Function *F, BlockFrequencyInfo &BFI); /// \brief Returns true if \p F is a hot function. bool isHotCount(uint64_t C); /// \brief Returns true if count \p C is considered cold. Modified: vendor/llvm/dist/include/llvm/Analysis/ScalarEvolutionExpander.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/ScalarEvolutionExpander.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/Analysis/ScalarEvolutionExpander.h Sun Dec 24 01:00:08 2017 (r327122) @@ -47,7 +47,7 @@ namespace llvm { ScalarEvolution &SE; const DataLayout &DL; - // New instructions receive a name to identifies them with the current pass. + // New instructions receive a name to identify them with the current pass. const char* IVName; // InsertedExpressions caches Values for reuse, so must track RAUW. Modified: vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfo.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfo.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfo.h Sun Dec 24 01:00:08 2017 (r327122) @@ -646,6 +646,9 @@ class TargetTransformInfo { (public) /// \brief Additional properties of an operand's values. enum OperandValueProperties { OP_None = 0, OP_PowerOf2 = 1 }; + /// \return True if target can execute instructions out of order. + bool isOutOfOrder() const; + /// \return The number of scalar or vector registers that the target has. /// If 'Vectors' is true, it returns the number of vector registers. If it is /// set to false, it returns the number of scalar registers. @@ -1018,6 +1021,7 @@ class TargetTransformInfo::Concept { (public) Type *Ty) = 0; virtual int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) = 0; + virtual bool isOutOfOrder() const = 0; virtual unsigned getNumberOfRegisters(bool Vector) = 0; virtual unsigned getRegisterBitWidth(bool Vector) const = 0; virtual unsigned getMinVectorRegisterBitWidth() = 0; @@ -1294,6 +1298,9 @@ class TargetTransformInfo::Model final : public Target int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) override { return Impl.getIntImmCost(IID, Idx, Imm, Ty); + } + bool isOutOfOrder() const override { + return Impl.isOutOfOrder(); } unsigned getNumberOfRegisters(bool Vector) override { return Impl.getNumberOfRegisters(Vector); Modified: vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfoImpl.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfoImpl.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfoImpl.h Sun Dec 24 01:00:08 2017 (r327122) @@ -337,6 +337,8 @@ class TargetTransformInfoImplBase { (public) return TTI::TCC_Free; } + bool isOutOfOrder() const { return false; } + unsigned getNumberOfRegisters(bool Vector) { return 8; } unsigned getRegisterBitWidth(bool Vector) const { return 32; } Modified: vendor/llvm/dist/include/llvm/BinaryFormat/Wasm.h ============================================================================== --- vendor/llvm/dist/include/llvm/BinaryFormat/Wasm.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/BinaryFormat/Wasm.h Sun Dec 24 01:00:08 2017 (r327122) @@ -208,7 +208,7 @@ const unsigned WASM_SYMBOL_VISIBILITY_HIDDEN = 0x4; #define WASM_RELOC(name, value) name = value, enum : unsigned { -#include "WasmRelocs/WebAssembly.def" +#include "WasmRelocs.def" }; #undef WASM_RELOC Added: vendor/llvm/dist/include/llvm/BinaryFormat/WasmRelocs.def ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/include/llvm/BinaryFormat/WasmRelocs.def Sun Dec 24 01:00:08 2017 (r327122) @@ -0,0 +1,13 @@ + +#ifndef WASM_RELOC +#error "WASM_RELOC must be defined" +#endif + +WASM_RELOC(R_WEBASSEMBLY_FUNCTION_INDEX_LEB, 0) +WASM_RELOC(R_WEBASSEMBLY_TABLE_INDEX_SLEB, 1) +WASM_RELOC(R_WEBASSEMBLY_TABLE_INDEX_I32, 2) +WASM_RELOC(R_WEBASSEMBLY_MEMORY_ADDR_LEB, 3) +WASM_RELOC(R_WEBASSEMBLY_MEMORY_ADDR_SLEB, 4) +WASM_RELOC(R_WEBASSEMBLY_MEMORY_ADDR_I32, 5) +WASM_RELOC(R_WEBASSEMBLY_TYPE_INDEX_LEB, 6) +WASM_RELOC(R_WEBASSEMBLY_GLOBAL_INDEX_LEB, 7) Modified: vendor/llvm/dist/include/llvm/CodeGen/BasicTTIImpl.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/BasicTTIImpl.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/CodeGen/BasicTTIImpl.h Sun Dec 24 01:00:08 2017 (r327122) @@ -302,9 +302,13 @@ class BasicTTIImplBase : public TargetTransformInfoImp } unsigned getFPOpCost(Type *Ty) { - // By default, FP instructions are no more expensive since they are - // implemented in HW. Target specific TTI can override this. - return TargetTransformInfo::TCC_Basic; + // Check whether FADD is available, as a proxy for floating-point in + // general. + const TargetLoweringBase *TLI = getTLI(); + EVT VT = TLI->getValueType(DL, Ty); + if (TLI->isOperationLegalOrCustomOrPromote(ISD::FADD, VT)) + return TargetTransformInfo::TCC_Basic; + return TargetTransformInfo::TCC_Expensive; } unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) { @@ -396,6 +400,10 @@ class BasicTTIImplBase : public TargetTransformInfoImp return getST()->getSchedModel().DefaultLoadLatency; return BaseT::getInstructionLatency(I); + } + + bool isOutOfOrder() const { + return getST()->getSchedModel().isOutOfOrder(); } /// @} Modified: vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/InstructionSelector.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/InstructionSelector.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/InstructionSelector.h Sun Dec 24 01:00:08 2017 (r327122) @@ -282,10 +282,6 @@ enum { /// Provides the logic to select generic machine instructions. class InstructionSelector { public: - using I64ImmediatePredicateFn = bool (*)(int64_t); - using APIntImmediatePredicateFn = bool (*)(const APInt &); - using APFloatImmediatePredicateFn = bool (*)(const APFloat &); - virtual ~InstructionSelector() = default; /// Select the (possibly generic) instruction \p I to only use target-specific @@ -319,9 +315,6 @@ class InstructionSelector { (public) struct MatcherInfoTy { const LLT *TypeObjects; const PredicateBitset *FeatureBitsets; - const I64ImmediatePredicateFn *I64ImmPredicateFns; - const APIntImmediatePredicateFn *APIntImmPredicateFns; - const APFloatImmediatePredicateFn *APFloatImmPredicateFns; const ComplexMatcherMemFn *ComplexPredicates; }; @@ -339,6 +332,16 @@ class InstructionSelector { (public) MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const; + + virtual bool testImmPredicate_I64(unsigned, int64_t) const { + llvm_unreachable("Subclasses must override this to use tablegen"); + } + virtual bool testImmPredicate_APInt(unsigned, const APInt &) const { + llvm_unreachable("Subclasses must override this to use tablegen"); + } + virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const { + llvm_unreachable("Subclasses must override this to use tablegen"); + } /// Constrain a register operand of an instruction \p I to a specified /// register class. This could involve inserting COPYs before (for uses) or Modified: vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h Sun Dec 24 01:00:08 2017 (r327122) @@ -181,7 +181,7 @@ bool InstructionSelector::executeMatchTable( else llvm_unreachable("Expected Imm or CImm operand"); - if (!MatcherInfo.I64ImmPredicateFns[Predicate](Value)) + if (!testImmPredicate_I64(Predicate, Value)) if (handleReject() == RejectAndGiveUp) return false; break; @@ -202,7 +202,7 @@ bool InstructionSelector::executeMatchTable( else llvm_unreachable("Expected Imm or CImm operand"); - if (!MatcherInfo.APIntImmPredicateFns[Predicate](Value)) + if (!testImmPredicate_APInt(Predicate, Value)) if (handleReject() == RejectAndGiveUp) return false; break; @@ -221,7 +221,7 @@ bool InstructionSelector::executeMatchTable( assert(Predicate > GIPFP_APFloat_Invalid && "Expected a valid predicate"); APFloat Value = State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF(); - if (!MatcherInfo.APFloatImmPredicateFns[Predicate](Value)) + if (!testImmPredicate_APFloat(Predicate, Value)) if (handleReject() == RejectAndGiveUp) return false; break; Added: vendor/llvm/dist/include/llvm/CodeGen/LiveStacks.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/include/llvm/CodeGen/LiveStacks.h Sun Dec 24 01:00:08 2017 (r327122) @@ -0,0 +1,103 @@ +//===- LiveStacks.h - Live Stack Slot Analysis ------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the live stack slot analysis pass. It is analogous to +// live interval analysis except it's analyzing liveness of stack slots rather +// than registers. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_LIVESTACKS_H +#define LLVM_CODEGEN_LIVESTACKS_H + +#include "llvm/CodeGen/LiveInterval.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/Pass.h" +#include <cassert> +#include <map> +#include <unordered_map> + +namespace llvm { + +class TargetRegisterClass; +class TargetRegisterInfo; + +class LiveStacks : public MachineFunctionPass { + const TargetRegisterInfo *TRI; + + /// Special pool allocator for VNInfo's (LiveInterval val#). + /// + VNInfo::Allocator VNInfoAllocator; + + /// S2IMap - Stack slot indices to live interval mapping. + using SS2IntervalMap = std::unordered_map<int, LiveInterval>; + SS2IntervalMap S2IMap; + + /// S2RCMap - Stack slot indices to register class mapping. + std::map<int, const TargetRegisterClass *> S2RCMap; + +public: + static char ID; // Pass identification, replacement for typeid + + LiveStacks() : MachineFunctionPass(ID) { + initializeLiveStacksPass(*PassRegistry::getPassRegistry()); + } + + using iterator = SS2IntervalMap::iterator; + using const_iterator = SS2IntervalMap::const_iterator; + + const_iterator begin() const { return S2IMap.begin(); } + const_iterator end() const { return S2IMap.end(); } + iterator begin() { return S2IMap.begin(); } + iterator end() { return S2IMap.end(); } + + unsigned getNumIntervals() const { return (unsigned)S2IMap.size(); } + + LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC); + + LiveInterval &getInterval(int Slot) { + assert(Slot >= 0 && "Spill slot indice must be >= 0"); + SS2IntervalMap::iterator I = S2IMap.find(Slot); + assert(I != S2IMap.end() && "Interval does not exist for stack slot"); + return I->second; + } + + const LiveInterval &getInterval(int Slot) const { + assert(Slot >= 0 && "Spill slot indice must be >= 0"); + SS2IntervalMap::const_iterator I = S2IMap.find(Slot); + assert(I != S2IMap.end() && "Interval does not exist for stack slot"); + return I->second; + } + + bool hasInterval(int Slot) const { return S2IMap.count(Slot); } + + const TargetRegisterClass *getIntervalRegClass(int Slot) const { + assert(Slot >= 0 && "Spill slot indice must be >= 0"); + std::map<int, const TargetRegisterClass *>::const_iterator I = + S2RCMap.find(Slot); + assert(I != S2RCMap.end() && + "Register class info does not exist for stack slot"); + return I->second; + } + + VNInfo::Allocator &getVNInfoAllocator() { return VNInfoAllocator; } + + void getAnalysisUsage(AnalysisUsage &AU) const override; + void releaseMemory() override; + + /// runOnMachineFunction - pass entry point + bool runOnMachineFunction(MachineFunction &) override; + + /// print - Implement the dump method. + void print(raw_ostream &O, const Module * = nullptr) const override; +}; + +} // end namespace llvm + +#endif Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineOperand.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/MachineOperand.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/CodeGen/MachineOperand.h Sun Dec 24 01:00:08 2017 (r327122) @@ -29,6 +29,7 @@ class GlobalValue; class MachineBasicBlock; class MachineInstr; class MachineRegisterInfo; +class MCCFIInstruction; class MDNode; class ModuleSlotTracker; class TargetMachine; @@ -249,6 +250,12 @@ class MachineOperand { (public) /// Print a stack object reference. static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name); + + /// Print the offset with explicit +/- signs. + static void printOperandOffset(raw_ostream &OS, int64_t Offset); + + /// Print an IRSlotNumber. + static void printIRSlotNumber(raw_ostream &OS, int Slot); /// Print the MachineOperand to \p os. /// Providing a valid \p TRI and \p IntrinsicInfo results in a more Modified: vendor/llvm/dist/include/llvm/CodeGen/RuntimeLibcalls.def ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/RuntimeLibcalls.def Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/CodeGen/RuntimeLibcalls.def Sun Dec 24 01:00:08 2017 (r327122) @@ -165,6 +165,8 @@ HANDLE_LIBCALL(SINCOS_F64, nullptr) HANDLE_LIBCALL(SINCOS_F80, nullptr) HANDLE_LIBCALL(SINCOS_F128, nullptr) HANDLE_LIBCALL(SINCOS_PPCF128, nullptr) +HANDLE_LIBCALL(SINCOS_STRET_F32, nullptr) +HANDLE_LIBCALL(SINCOS_STRET_F64, nullptr) HANDLE_LIBCALL(POW_F32, "powf") HANDLE_LIBCALL(POW_F64, "pow") HANDLE_LIBCALL(POW_F80, "powl") @@ -334,6 +336,7 @@ HANDLE_LIBCALL(O_PPCF128, "__gcc_qunord") HANDLE_LIBCALL(MEMCPY, "memcpy") HANDLE_LIBCALL(MEMMOVE, "memmove") HANDLE_LIBCALL(MEMSET, "memset") +HANDLE_LIBCALL(BZERO, nullptr) // Element-wise unordered-atomic memory of different sizes HANDLE_LIBCALL(MEMCPY_ELEMENT_UNORDERED_ATOMIC_1, "__llvm_memcpy_element_unordered_atomic_1") Added: vendor/llvm/dist/include/llvm/CodeGen/SDNodeProperties.td ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/include/llvm/CodeGen/SDNodeProperties.td Sun Dec 24 01:00:08 2017 (r327122) @@ -0,0 +1,34 @@ +//===- SDNodeProperties.td - Common code for DAG isels ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +class SDNodeProperty; + +// Selection DAG Pattern Operations +class SDPatternOperator { + list<SDNodeProperty> Properties = []; +} + +//===----------------------------------------------------------------------===// +// Selection DAG Node Properties. +// +// Note: These are hard coded into tblgen. +// +def SDNPCommutative : SDNodeProperty; // X op Y == Y op X +def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) +def SDNPHasChain : SDNodeProperty; // R/W chain operand and result +def SDNPOutGlue : SDNodeProperty; // Write a flag result +def SDNPInGlue : SDNodeProperty; // Read a flag operand +def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand +def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. +def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. +def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. +def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand +def SDNPVariadic : SDNodeProperty; // Node has variable arguments. +def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match +def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent Modified: vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h Sun Dec 24 01:00:08 2017 (r327122) @@ -189,8 +189,8 @@ class SDValue { (public) inline bool isUndef() const; inline unsigned getMachineOpcode() const; inline const DebugLoc &getDebugLoc() const; - inline void dump() const; - inline void dumpr() const; + inline void dump(const SelectionDAG *G = nullptr) const; + inline void dumpr(const SelectionDAG *G = nullptr) const; /// Return true if this operand (which must be a chain) reaches the /// specified operand without crossing any side-effecting instructions. @@ -1089,12 +1089,12 @@ inline const DebugLoc &SDValue::getDebugLoc() const { return Node->getDebugLoc(); } -inline void SDValue::dump() const { - return Node->dump(); +inline void SDValue::dump(const SelectionDAG *G) const { + return Node->dump(G); } -inline void SDValue::dumpr() const { - return Node->dumpr(); +inline void SDValue::dumpr(const SelectionDAG *G) const { + return Node->dumpr(G); } // Define inline functions from the SDUse class. Modified: vendor/llvm/dist/include/llvm/CodeGen/TargetLowering.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/TargetLowering.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/CodeGen/TargetLowering.h Sun Dec 24 01:00:08 2017 (r327122) @@ -824,8 +824,8 @@ class TargetLoweringBase { (public) /// also combined within this function. Currently, the minimum size check is /// performed in findJumpTable() in SelectionDAGBuiler and /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl. - bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, - uint64_t Range) const { + virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, + uint64_t Range) const { const bool OptForSize = SI->getParent()->getParent()->optForSize(); const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize); const unsigned MaxJumpTableSize = @@ -1276,7 +1276,7 @@ class TargetLoweringBase { (public) } /// Return lower limit for number of blocks in a jump table. - unsigned getMinimumJumpTableEntries() const; + virtual unsigned getMinimumJumpTableEntries() const; /// Return lower limit of the density in a jump table. unsigned getMinimumJumpTableDensity(bool OptForSize) const; @@ -2429,7 +2429,7 @@ class TargetLoweringBase { (public) PromoteToType; /// Stores the name each libcall. - const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; + const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1]; /// The ISD::CondCode that should be used to test the result of each of the /// comparison libcall against zero. @@ -2437,6 +2437,9 @@ class TargetLoweringBase { (public) /// Stores the CallingConv that should be used for each libcall. CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; + + /// Set default libcall names and calling conventions. + void InitLibcalls(const Triple &TT); protected: /// Return true if the extension represented by \p I is free. Modified: vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFUnit.h ============================================================================== --- vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFUnit.h Sat Dec 23 22:58:19 2017 (r327121) +++ vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFUnit.h Sun Dec 24 01:00:08 2017 (r327122) @@ -165,6 +165,29 @@ struct BaseAddress { uint64_t SectionIndex; }; +/// Represents a unit's contribution to the string offsets table. +struct StrOffsetsContributionDescriptor { + uint64_t Base = 0; + uint64_t Size = 0; + /// Format and version. + DWARFFormParams FormParams = {0, 0, dwarf::DwarfFormat::DWARF32}; + + StrOffsetsContributionDescriptor(uint64_t Base, uint64_t Size, + uint8_t Version, dwarf::DwarfFormat Format) + : Base(Base), Size(Size), FormParams({Version, 0, Format}) {} + + uint8_t getVersion() const { return FormParams.Version; } + dwarf::DwarfFormat getFormat() const { return FormParams.Format; } + uint8_t getDwarfOffsetByteSize() const { + return FormParams.getDwarfOffsetByteSize(); + } + /// Determine whether a contribution to the string offsets table is + /// consistent with the relevant section size and that its length is + /// a multiple of the size of one of its entries. + Optional<StrOffsetsContributionDescriptor> + validateContributionSize(DWARFDataExtractor &DA); +}; + class DWARFUnit { DWARFContext &Context; /// Section containing this DWARFUnit. @@ -176,7 +199,6 @@ class DWARFUnit { const DWARFSection &LineSection; StringRef StringSection; const DWARFSection &StringOffsetSection; - uint64_t StringOffsetSectionBase = 0; const DWARFSection *AddrOffsetSection; uint32_t AddrOffsetSectionBase = 0; bool isLittleEndian; @@ -185,6 +207,9 @@ class DWARFUnit { // Version, address size, and DWARF format. DWARFFormParams FormParams; + /// Start, length, and DWARF format of the unit's contribution to the string + /// offsets table (DWARF v5). + Optional<StrOffsetsContributionDescriptor> StringOffsetsTableContribution; uint32_t Offset; uint32_t Length; @@ -195,11 +220,41 @@ class DWARFUnit { /// The compile unit debug information entry items. std::vector<DWARFDebugInfoEntry> DieArray; - /// Map from range's start address to end address and corresponding DIE. - /// IntervalMap does not support range removal, as a result, we use the - /// std::map::upper_bound for address range lookup. - std::map<uint64_t, std::pair<uint64_t, DWARFDie>> AddrDieMap; + /// The vector of inlined subroutine DIEs that we can map directly to from + /// their subprogram below. + std::vector<DWARFDie> InlinedSubroutineDIEs; + /// A type representing a subprogram DIE and a map (built using a sorted + /// vector) into that subprogram's inlined subroutine DIEs. + struct SubprogramDIEAddrInfo { + DWARFDie SubprogramDIE; + + uint64_t SubprogramBasePC; + + /// A vector sorted to allow mapping from a relative PC to the inlined + /// subroutine DIE with the most specific address range covering that PC. + /// + /// The PCs are relative to the `SubprogramBasePC`. + /// + /// The vector is sorted in ascending order of the first int which + /// represents the relative PC for an interval in the map. The second int + /// represents the index into the `InlinedSubroutineDIEs` vector of the DIE + /// that interval maps to. An index of '-1` indicates an empty mapping. The + /// interval covered is from the `.first` relative PC to the next entry's + /// `.first` relative PC. + std::vector<std::pair<uint32_t, int32_t>> InlinedSubroutineDIEAddrMap; + }; + + /// Vector of the subprogram DIEs and their subroutine address maps. + std::vector<SubprogramDIEAddrInfo> SubprogramDIEAddrInfos; + + /// A vector sorted to allow mapping from a PC to the subprogram DIE (and + /// associated addr map) index. Subprograms with overlapping PC ranges aren't + /// supported here. Nothing will crash, but the mapping may be inaccurate. + /// This vector may also contain "empty" ranges marked by an address with + /// a DIE index of '-1'. + std::vector<std::pair<uint64_t, int64_t>> SubprogramDIEAddrMap; + using die_iterator_range = iterator_range<std::vector<DWARFDebugInfoEntry>::iterator>; @@ -219,6 +274,21 @@ class DWARFUnit { /// Size in bytes of the unit header. virtual uint32_t getHeaderSize() const { return getVersion() <= 4 ? 11 : 12; } + /// Find the unit's contribution to the string offsets table and determine its + /// length and form. The given offset is expected to be derived from the unit + /// DIE's DW_AT_str_offsets_base attribute. + Optional<StrOffsetsContributionDescriptor> + determineStringOffsetsTableContribution(DWARFDataExtractor &DA, + uint64_t Offset); + + /// Find the unit's contribution to the string offsets table and determine its + /// length and form. The given offset is expected to be 0 in a dwo file or, + /// in a dwp file, the start of the unit's contribution to the string offsets + /// table section (as determined by the index table). + Optional<StrOffsetsContributionDescriptor> + determineStringOffsetsTableContributionDWO(DWARFDataExtractor &DA, + uint64_t Offset); + public: DWARFUnit(DWARFContext &Context, const DWARFSection &Section, const DWARFDebugAbbrev *DA, const DWARFSection *RS, StringRef SS, @@ -242,9 +312,6 @@ class DWARFUnit { AddrOffsetSectionBase = Base; } - /// Recursively update address to Die map. - void updateAddressDieMap(DWARFDie Die); - void setRangesSection(const DWARFSection *RS, uint32_t Base) { RangeSection = RS; RangeSectionBase = Base; @@ -272,6 +339,10 @@ class DWARFUnit { uint32_t getNextUnitOffset() const { return Offset + Length + 4; } uint32_t getLength() const { return Length; } + const Optional<StrOffsetsContributionDescriptor> & + getStringOffsetsTableContribution() const { + return StringOffsetsTableContribution; + } const DWARFFormParams &getFormParams() const { return FormParams; } uint16_t getVersion() const { return FormParams.Version; } dwarf::DwarfFormat getFormat() const { return FormParams.Format; } @@ -281,6 +352,16 @@ class DWARFUnit { return FormParams.getDwarfOffsetByteSize(); } + uint8_t getDwarfStringOffsetsByteSize() const { + assert(StringOffsetsTableContribution); + return StringOffsetsTableContribution->getDwarfOffsetByteSize(); + } + + uint64_t getStringOffsetsBase() const { + assert(StringOffsetsTableContribution); + return StringOffsetsTableContribution->Base; + } + const DWARFAbbreviationDeclarationSet *getAbbreviations() const; uint8_t getUnitType() const { return UnitType; } @@ -426,6 +507,9 @@ class DWARFUnit { /// parseDWO - Parses .dwo file for current compile unit. Returns true if /// it was actually constructed. *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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