Date: Mon, 13 Aug 2018 16:20:46 -0500 From: Jason Harmening <jason.harmening@gmail.com> To: freebsd-mips@freebsd.org Subject: MIPS pmap questions Message-ID: <CAM=8qakP7BaUZF=_rZRtQFpSAF1v6GQ6OTwoAmtGXXjD=JBU_A@mail.gmail.com>
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Hi all, There are couple of mips-related things that've been on my todo-list for about 3 years now (!), and I've finally found some time to dig into them. But I have a couple of related questions: 1) I'd like to implement the mips equivalent of r312610 <https://svnweb.freebsd.org/base?view=revision&revision=312610>; for arm or r310481 for i386. That seems like it would be easy enough to do, but looking through the pmap code I see that pmap_map_lmem*() completely disables local interrupts. That seems a bit heavyweight; other architectures use either critical_enter() or sched_pin() + a mutex for per-CPU operations like this. Does anyone know why it was done this way (maybe something related to TLB interrupt handling)? 2) I'd also like to improve the flexibility of busdma by using pmap_quick* for bouncing and cache maintenance, as done for arm way back in r289759 <https://svnweb.freebsd.org/base?view=revision&revision=289759>. That can increase the possibility of having multiple mappings of the same physical page, and I vaguely remember someone on -developers or -arch pointing out that the mips pmap doesn't handle that correctly for all processor variants. In particular, it sounded like some MIPS processors have VIVT caches of sufficient geometry to alias, but the pmap doesn't accommodate that, e.g. by marking mappings of multiply-mapped pages as uncacheable through the PV list. Am I just mis-remembering, or is this something that still needs to be addressed? Thanks, Jason
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