From nobody Sun Sep 3 12:02:53 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rdr4r6vJVz4s1cZ for ; Sun, 3 Sep 2023 12:03:08 +0000 (UTC) (envelope-from tomek@cedro.info) Received: from mail-yb1-xb2d.google.com (mail-yb1-xb2d.google.com [IPv6:2607:f8b0:4864:20::b2d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Rdr4r5JyLz3KFJ for ; Sun, 3 Sep 2023 12:03:08 +0000 (UTC) (envelope-from tomek@cedro.info) Authentication-Results: mx1.freebsd.org; none Received: by mail-yb1-xb2d.google.com with SMTP id 3f1490d57ef6-d7ecdb99b7aso482066276.3 for ; Sun, 03 Sep 2023 05:03:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cedro.info; s=google; t=1693742587; x=1694347387; darn=freebsd.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=NcrzoYxtqoAfvc9EjknvGSDQWuXjBLddeeUdCsJ5ssM=; b=bBtwWTe0fqEONP0d5Ngr3FcWFmwY1+u5jLSEpjVjcbyxWEEZvDpBpnOVBQoeOZCwC3 6bpRsnriA02EDhK1Xwk8s/rDZsua3UNOn4vPtBaXwo5AKwxDAb9Gf3tr4eVxH2k4cnA9 RTnwVTdGXb2M7SceFB0UuSfpWz+5yqR9dQuC2jbmkQsQ2ZxvvpzJy/5sogWlkWTBYaDB h2fgAVAE3HGtPBpY4z03FmqOj0NtBOPiZH9yqNP/6qh5j5I1pfsPEKApGUsRgV7d8A97 WkEADCB0pOuMOtQjR9rmPChj5RJOPcgSLG8VjYbhq4T/A+Mni9vLodoch20QLC/SPtVR AHFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693742587; x=1694347387; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NcrzoYxtqoAfvc9EjknvGSDQWuXjBLddeeUdCsJ5ssM=; b=QRwpQv8IaapqSQPfCs89T6hZxDLuxmdRylbogbBhahwh5XmM//3Hp8yqTb+RALeAaE 9ovxgwoLMBqfxWCHE8WtjmEfcnH9C7Q6shpxLPgCrHNbGB6Q/h84fDqmwc3QmuT9Q3x6 D0ePcVO5BcRs7qoI4cBzy5MySUZicnsTPrJoxMGjzlvwACjqu+9FslspSN/gXkzCSVZY pL2TbItEjwAXhfnvgbrZilAtaOn7XqxQCOQMDZRm1OTFj9ZbwyuTMUoxKebuEAy00N7o CUgGfDpTDHYtTCnSFhXSqrpNq0PHYsOFIAoVbWvacIEcv9h+udzb8I8cmfesYM9O8MKC D2cQ== X-Gm-Message-State: AOJu0Yxd40f3CScEBJk5B8dDZIjEQwBYMyJyLZ/EoQARzVsAl2N1vs/X JmqeSssJI9pHIjqVRG8kI9ouRPNm2oWx8MSq8s8= X-Google-Smtp-Source: AGHT+IFh4qSqApyKFB+SfMJIzBJtFViQu6ssw4G/6zofiFKuQy6uvcwp3NmbE4MYJJ45hltZZCcLzg== X-Received: by 2002:a25:734a:0:b0:d12:25d:fd5f with SMTP id o71-20020a25734a000000b00d12025dfd5fmr7813525ybc.5.1693742587664; Sun, 03 Sep 2023 05:03:07 -0700 (PDT) Received: from mail-yw1-f181.google.com (mail-yw1-f181.google.com. [209.85.128.181]) by smtp.gmail.com with ESMTPSA id j143-20020a252395000000b00d7badcab84esm1847580ybj.9.2023.09.03.05.03.06 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 03 Sep 2023 05:03:07 -0700 (PDT) Received: by mail-yw1-f181.google.com with SMTP id 00721157ae682-59254e181a2so5101157b3.1 for ; Sun, 03 Sep 2023 05:03:06 -0700 (PDT) X-Received: by 2002:a25:688c:0:b0:d7a:c4dc:e7b3 with SMTP id d134-20020a25688c000000b00d7ac4dce7b3mr7157340ybc.61.1693742586609; Sun, 03 Sep 2023 05:03:06 -0700 (PDT) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 References: <6952b7fd-f90f-2677-1997-d0c708cb559e@yahoo.com> <455dc69a-dd15-18d9-8e93-91bbff3997e4@madpilot.net> In-Reply-To: From: Tomek CEDRO Date: Sun, 3 Sep 2023 14:02:53 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: Very slow scp performance comparing to Linux To: Wojciech Puchar Cc: Wei Hu , Guido Falsi , Mikhail Zakharov , FreeBSD Hackers Content-Type: multipart/alternative; boundary="00000000000037451e0604732df5" X-Spamd-Bar: ---- X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:15169, ipnet:2607:f8b0::/32, country:US] X-Rspamd-Queue-Id: 4Rdr4r5JyLz3KFJ --00000000000037451e0604732df5 Content-Type: text/plain; charset="UTF-8" On Sat, Sep 2, 2023, 22:12 Wojciech Puchar wrote: > linux filesystem caching is just stupid, optimized to show up good in > benchmarks. > > It just accepts writes as long as there is available memory, without > writing anything to disk, then if it cannot do it anymore or some time > passed, schedules huge amount of writes, often stalling whole system. > > This is how it was almost 20 years ago when i was still using linux, seems > like didn't change much. > > Just think how much data loss and inconsistency would occur if there will > be crash or power loss after "writing" 100000 files of 10GB which can > easily be done in short time as linux just doesn't block writing process > at all and fill memory. > > Since i started using FreeBSD UFS, many machines, lighter of heavier > workload, always mixed workload, i never ever have more that a few files > loss on power outage. > Exactly! I was recently surprised when my friend using Linux copied around 4GB file to my pendrive, it showed over 200MB/s and was rapid fast but then we had to wait for background operation to complete for over an hour with absolutely no information on progress/completion. This is why I prefer FreeBSD :-) -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > --00000000000037451e0604732df5 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Sat, Sep = 2, 2023, 22:12 Wojciech Puchar=C2=A0 wrote:
linux filesystem caching is just stupid, optimized to show up good in
benchmarks.

It just accepts writes as long as there is available memory, without
writing anything to disk, then if it cannot do it anymore or some time
passed, schedules huge amount of writes, often stalling whole system.

This is how it was almost 20 years ago when i was still using linux, seems =
like didn't change much.

Just think how much data loss and inconsistency would occur if there will <= br> be crash or power loss after "writing" 100000 files of 10GB which= can
easily be done in short time as linux just doesn't block writing proces= s
at all and fill memory.

Since i started using FreeBSD UFS, many machines, lighter of heavier
workload, always mixed workload, i never ever have more that a few files loss on power outage.

Exactly! I was recently surprised when my friend using= Linux copied around 4GB file to my pendrive, it showed over 200MB/s and wa= s rapid fast but then we had to wait for background operation to complete f= or over an hour with absolutely no information on progress/completion. This= is why I prefer FreeBSD :-)

--00000000000037451e0604732df5-- From nobody Sun Sep 3 14:00:56 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rdthx2g4wz4rfcH for ; Sun, 3 Sep 2023 14:01:05 +0000 (UTC) (envelope-from wojtek@puchar.net) Received: from puchar.net (puchar.net [194.1.144.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4Rdthw4t8Mz4Dmf for ; Sun, 3 Sep 2023 14:01:04 +0000 (UTC) (envelope-from wojtek@puchar.net) Authentication-Results: mx1.freebsd.org; none Received: Received: from 127.0.0.1 (localhost [127.0.0.1]) by puchar.net (8.15.2/8.17.1) with ESMTPS id 383E0wKk088983 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 3 Sep 2023 16:00:58 +0200 (CEST) (envelope-from wojtek@puchar.net) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=puchar.net; s=default; t=1693749659; bh=V0BpIqLEgFFbmskPAW97n2zL+/ZIYQps5Yypkg+6NaY=; h=Date:From:To:cc:Subject:In-Reply-To:References; b=tnlDp+62d4Mz7sq7OAKY7wGSjRS1+JW32EhES8VUd5NLfKtGk6B3C+jHBQdjAoT2d 5Mnyaow1Ne1TAsBUAgW3T8mStvetDKpWU0pHvVa5trliM8nGAmGkLeGGJcjVdc/jSh 9Y22giXK8B3PyhlluaZvPBTGdYvnLzHPp5QkS7rQ= Received: from wojtek.intra (localhost [127.0.0.1]) by wojtek.intra (8.16.1/8.16.1) with ESMTP id 383E0vYi053732; Sun, 3 Sep 2023 16:00:57 +0200 (CEST) (envelope-from wojtek@puchar.net) Received: from localhost (wojtek@localhost) by wojtek.intra (8.16.1/8.16.1/Submit) with ESMTP id 383E0uPL053729; Sun, 3 Sep 2023 16:00:57 +0200 (CEST) (envelope-from wojtek@puchar.net) X-Authentication-Warning: wojtek.intra: wojtek owned process doing -bs Date: Sun, 3 Sep 2023 16:00:56 +0200 (CEST) From: Wojciech Puchar To: Tomek CEDRO cc: Wei Hu , Guido Falsi , Mikhail Zakharov , FreeBSD Hackers Subject: Re: Very slow scp performance comparing to Linux In-Reply-To: Message-ID: <6e18bdce-31c6-e0e7-eb5c-52d0911574e@puchar.net> References: <6952b7fd-f90f-2677-1997-d0c708cb559e@yahoo.com> <455dc69a-dd15-18d9-8e93-91bbff3997e4@madpilot.net> List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed X-Spamd-Bar: ---- X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:43476, ipnet:194.1.144.0/24, country:PL] X-Rspamd-Queue-Id: 4Rdthw4t8Mz4Dmf > Since i started using FreeBSD UFS, many machines, lighter of heavier > workload, always mixed workload, i never ever have more that a few files > loss on power outage. > > > Exactly! I was recently surprised when my friend using Linux copied around 4GB file to my pendrive, it showed over 200MB/s and was > rapid fast but then we had to wait for background operation to complete for over an hour with absolutely no information on More funny it could stall the whole system or at least good part of it. Pendrive is extreme example but it still exist for any media. Now think what it would be if you run large multiservice server running hundreds of different services and thousands of processes and you get power failure. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PUZP153MB0788.APCP153.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: dd562deb-9041-4dfe-484d-08dbad2fa211 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Sep 2023 10:13:49.6934 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: FLa5jJxF1jdE5G3IeL0fJfUEyR2RItXoZDZXr9XfyDKLXCYdZZkh148SQxlSZhCWsr6FcubfCNQlZw9KmSDpCrGyW5q2FzRxkRPWm4POCjI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYP153MB0975 X-Spamd-Bar: -------- X-Spamd-Result: default: False [-9.00 / 15.00]; WHITELIST_SPF_DKIM(-3.00)[microsoft.com:d:+,microsoft.com:s:+]; ARC_ALLOW(-1.00)[microsoft.com:s=arcselector9901:i=1]; DWL_DNSWL_LOW(-1.00)[microsoft.com:dkim]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-1.000]; DMARC_POLICY_ALLOW(-0.50)[microsoft.com,reject]; R_SPF_ALLOW(-0.20)[+ip4:52.100.0.0/14]; R_DKIM_ALLOW(-0.20)[microsoft.com:s=selector2]; MIME_GOOD(-0.10)[text/plain]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org,freebsd-arm@FreeBSD.org]; ASN(0.00)[asn:8075, ipnet:52.96.0.0/12, country:US]; FROM_EQ_ENVFROM(0.00)[]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_MATCH_ENVRCPT_SOME(0.00)[]; DKIM_TRACE(0.00)[microsoft.com:+]; FROM_HAS_DN(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[52.101.128.19:from]; RCPT_COUNT_THREE(0.00)[3]; RCVD_COUNT_TWO(0.00)[2]; TO_DN_SOME(0.00)[]; TO_DN_EQ_ADDR_SOME(0.00)[] X-Rspamd-Queue-Id: 4RfPcP4RbXz3Gxg Hi I am working on bringing FreeBSD on Azure ARM64. When I am rebooting the Fr= eeBSD arm64 in Azure public preview, we are hitting following panic sometime for page fault: db_trace_self_wrapper() at db_trace_self_wrapper+0x30 vpanic() at vpanic+0x13c panic() at panic+0x44 data_abort() at data_abort+0x30c handle_el1h_sync() at handle_el1h_sync+0x14 --- exception, esr 0x8600000e (null)() at 0xffffa0000c93bb00 add_route() at add_route+0xc4 add_route_flags() at add_route_flags+0x1b0 rib_add_route() at rib_add_route+0x324 ifa_maintain_loopback_route() at ifa_maintain_loopback_route+0xf4 in6_update_ifa() at in6_update_ifa+0x994 in6_ifattach() at in6_ifattach+0x1bc in6_if_up() at in6_if_up+0x90 if_up() at if_up+0xd8 ifhwioctl() at ifhwioctl+0xb7c ifioctl() at ifioctl+0x860 kern_ioctl() at kern_ioctl+0x2dc sys_ioctl() at sys_ioctl+0x118 do_el0_sync() at do_el0_sync+0x520 handle_el0_sync() at handle_el0_sync+0x44 The panic is coming when add_route is called for loopback interface ipv6 at= tachment. Upon more investigating it looks like the panic happens in rib_notify() . Please let me know how to debug it further to find the RC. I have already opened a bug to track it : https://bugs.freebsd.org/bugzilla= /show_bug.cgi?id=3D272666 Regards, Souradeep From nobody Mon Sep 4 10:49:30 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RfQQJ2lFxz4ryhR for ; Mon, 4 Sep 2023 10:50:16 +0000 (UTC) (envelope-from c@bow.st) Received: from comms.drone (in.bow.st [71.19.146.166]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4RfQQG2QDmz3PQw; Mon, 4 Sep 2023 10:50:14 +0000 (UTC) (envelope-from c@bow.st) Authentication-Results: mx1.freebsd.org; dkim=none; spf=pass (mx1.freebsd.org: domain of c@bow.st designates 71.19.146.166 as permitted sender) smtp.mailfrom=c@bow.st; dmarc=none Received: from homebase (unknown [IPv6:fe80::ff1d:976a:a7e4:ee6a]) by comms.drone (Postfix) with ESMTPSA id B0178FCDC; Mon, 4 Sep 2023 10:50:03 +0000 (UTC) From: "Mathew\, Cherry G.*" To: "Mathew\, Cherry G.*" Cc: Alexander Leidinger , adridg@freebsd.org, freebsd-hackers@freebsd.org Subject: Re: ARC model specified in spinroot/promela References: <85jzt96qjz.fsf@bow.st> <9c424a574cdd39fc879c9ed9192556c0@Leidinger.net> <858r9o6ee0.fsf@bow.st> <85pm304dzi.fsf@bow.st> Date: Mon, 04 Sep 2023 10:49:30 +0000 In-Reply-To: <85pm304dzi.fsf@bow.st> (Cherry G. Mathew's message of "Sat, 02 Sep 2023 18:38:41 +0000") Message-ID: <85a5u22oxx.fsf@bow.st> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (berkeley-unix) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain X-Spamd-Bar: - X-Spamd-Result: default: False [-1.69 / 15.00]; HFILTER_HELO_IP_A(1.00)[comms.drone]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.99)[-0.993]; NEURAL_HAM_MEDIUM(-0.80)[-0.799]; HFILTER_HELO_NORES_A_OR_MX(0.30)[comms.drone]; R_SPF_ALLOW(-0.20)[+mx]; MIME_GOOD(-0.10)[text/plain]; ONCE_RECEIVED(0.10)[]; TO_DN_SOME(0.00)[]; R_DKIM_NA(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; RCVD_TLS_ALL(0.00)[]; ASN(0.00)[asn:47066, ipnet:71.19.146.0/24, country:US]; FROM_HAS_DN(0.00)[]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org]; ARC_NA(0.00)[]; RCPT_COUNT_THREE(0.00)[4]; RCVD_COUNT_ONE(0.00)[1]; DMARC_NA(0.00)[bow.st]; TO_MATCH_ENVRCPT_SOME(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 4RfQQG2QDmz3PQw >>>>> Mathew, Cherry G * writes: [...] > So there's room for improvement in my Makefile to: > 1) Explore multithreaded/CPU > 2) Understand state space explosion scale - it is exponential to > the number of processes, I've fixed it to run in a loop - will > report back once I have good progress also with the model > extraction part. > 3) My model has errors - I'm glad to see that the error reporting > is the same in my new optimised loop, as in the RAM hungry version > you ran. > Thanks once again - this is very helpful. I will report back once > I have more progress. Hi Again, So just wanted to report back with a patch (absolute patch, not relative, so please nuke your existing arc/ if you tried the old one and apply in a clean new subdirectory) on the following: - implemented a loop method to drive the ARC() function runs in a second at most. - the model verification caught a logical error in my model! It was causing an unbounded growth in the T2 directory list. - expanded the invariants to include several ones described in the paper. - cleaned up the "UI" a bit - now you can directly run the verifier using: "make clean spin-run" Since the objective here is to demonstrate the dev methodology, I've left the verifier with a couple of unexplored code/state-paths. See comments in arc.drv for more on how to fix that. (I will look into this later). The next step is to write the equivalent C code, compile it with a simple test "driver" (ideally ATF, but since this is standalone for the moment, I'll use something simpler, just to illustrate the concept), and then hook it into spin's "modex" tool, to extract the implicit model. Once this is done, we'll have a full cycle of design->implement->verify and this will demonstrate the DDD (Design Driven Development) methodology I'd love to hear your thoughts about. Many Thanks in advance for any ideas, thoughts, critiques, bugs, etc. -- ~cherry diff -urN arc.null/arc.drv arc/arc.drv --- arc.null/arc.drv 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.drv 2023-09-04 10:32:34.042373574 +0000 @@ -0,0 +1,52 @@ +/* Spin process model for Adaptive Replacement Cache algorithm. Written by cherry */ + +/* Note: What we're attempting in this driver file, is to generate an + * input trace that would exercise all code-paths of the model specified + * in arc.pml + * + * Feeding a static trace to the algorithm in array _x[N_ITEMS] is a + * acceptable alternative. + */ +#include "arc.pmh" + +#define N_ITEMS (2 * C) /* Number of distinct cache items to test with */ +#define ITEM_REPS (C / 4) /* Max repeat item requests */ +#define N_ITERATIONS 3 + +hidden arc_item _x[N_ITEMS]; /* Input state is irrelevant from a verification PoV */ +hidden int _x_iid = 0; +hidden int _item_rep = 0; +hidden byte _iterations = 0; + +/* Drive the procs */ +init { + + atomic { + do + :: + _iterations < N_ITERATIONS -> + + _x_iid = 0; + do + :: _x_iid < N_ITEMS -> + init_arc_item(_x[_x_iid], _x_iid, false); + _item_rep = 0; + do + :: _item_rep < (_x_iid % ITEM_REPS) -> + ARC(_x[_x_iid]); + _item_rep++; + :: _item_rep >= (_x_iid % ITEM_REPS) -> + break; + od + _x_iid++; + :: _x_iid >= N_ITEMS -> + break; + od + _iterations++; + :: + _iterations >= N_ITERATIONS -> + break; + od + } + +} diff -urN arc.null/arc.inv arc/arc.inv --- arc.null/arc.inv 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.inv 2023-09-04 09:20:20.224107390 +0000 @@ -0,0 +1,59 @@ +/* $NetBSD$ */ + +/* These are Linear Temporal Logic invariants (and constraints) + * applied over the statespace created by the promela + * specification. Correctness is implied by Logical consistency. + */ +ltl +{ + /* Liveness - all threads, except control must finally exit */ + eventually always (_nr_pr == 1) && + /* c.f Section I. B, on page 3 of paper */ + always ((lengthof(T1) + + lengthof(B1) + + lengthof(T2) + + lengthof(B2)) <= (2 * C)) && + + /* Reading together Section III. A., on page 7, and + * Section III. B., on pages 7,8 + */ + always ((lengthof(T1) + lengthof(B1)) <= C) && + always ((lengthof(T2) + lengthof(B2)) < (2 * C)) && + + /* Section III. B, Remark III.1 */ + always ((lengthof(T1) + lengthof(T2)) <= C) && + + /* TODO: III B, A.1 */ + + /* III B, A.2 */ + always (((lengthof(T1) + + lengthof(B1) + + lengthof(T2) + + lengthof(B2)) < C) + implies ((lengthof(B1) == 0) && + lengthof(B2) == 0)) && + + /* III B, A.3 */ + always (((lengthof(T1) + + lengthof(B1) + + lengthof(T2) + + lengthof(B2)) >= C) + implies ((lengthof(T1) + + lengthof(T2) == C))) && + + /* TODO: III B, A.4 */ + + /* TODO: III B, A.5 */ + + /* IV A. */ + always (p <= C) && + + /* Not strictly true, but these force us to generate a "good" + * input trace via arc.drv + */ + + eventually /* always ? */ ((lengthof(T1) == p) && lengthof(T2) == (C - p)) && + + eventually (p > 0) + +} diff -urN arc.null/arc.pmh arc/arc.pmh --- arc.null/arc.pmh 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.pmh 2023-09-04 10:27:50.069213153 +0000 @@ -0,0 +1,59 @@ +/* Spin process model for Adaptive Replacement Cache algorithm. Written by cherry */ + +#ifndef _ARC_INC +#define _ARC_INC + +/* XXX: Move these into a set of library includes ? */ +/* XXX: Equivalence verification */ +/* Note: CAS implemented in an atomic {} block */ +#define mutex_enter(_mutex) \ + atomic { \ + (_mutex == 0) -> _mutex = 1; \ + } + +#define mutex_exit(_mutex) \ + atomic { \ + assert(_mutex == 1); \ + (_mutex == 1) -> _mutex = 0; \ + } + +bit sc_lock; + +#define C 64 /* Cache size - use judiciously - adds to statespace */ + +typedef arc_item { + int iid; /* Unique identifier for item */ + bool cached; +}; + +/* Note that we use the arc_item.iid as the member lookup handle to reduce state space */ +typedef arc_list { + chan item_list = [ 2 * C ] of { int }; /* A list of page items */ +}; + +#define lengthof(_arc_list) len(_arc_list.item_list) +#define memberof(_arc_list, _arc_item) _arc_list.item_list??[eval(_arc_item.iid)] +#define addMRU(_arc_list, _arc_item) _arc_list.item_list!_arc_item.iid +#define readLRU(_arc_list, _arc_item) _arc_list.item_list?<_arc_item.iid> +#define delLRU(_arc_list) _arc_list.item_list?_ +#define delitem(_arc_list, _arc_item) _arc_list.item_list??eval(_arc_item.iid) +#define refreshitemto(_src_arc_list, _dest_arc_list, _arc_item) \ + d_step { \ + delitem(_src_arc_list, _arc_item); \ + addMRU(_dst_arc_list, _arc_item); \ + } +#define refreshitem(_arc_list, _arc_item) refreshitemto(_arc_list, _arc_list, _arc_item) + +#define cachefetch(_arc_item) _arc_item.cached = true +#define cacheremove(_arc_item) _arc_item.cached = false + +#define min(a, b) ((a < b) -> a : b) +#define max(a, b) ((a > b) -> a : b) + +#define init_arc_item(_arc_item, _iid, _cached) \ + d_step { \ + _arc_item.iid = _iid; \ + _arc_item.cached = _cached; \ + } + +#endif /* _ARC_INC_ */ \ No newline at end of file diff -urN arc.null/arc.pml arc/arc.pml --- arc.null/arc.pml 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.pml 2023-09-04 10:15:53.767411900 +0000 @@ -0,0 +1,216 @@ +/* Spin process model for Adaptive Replacement Cache algorithm. Written by cherry */ + +/* + * We implement the following algorithm from page 10, Figure 4. + * https://www.usenix.org/legacy/events/fast03/tech/full_papers/megiddo/megiddo.pdf + * + * + * ARC(c) + * + * INPUT: The request stream x1,x2,....,xt,.... + * INITIALIZATION: Set p = 0 and set the LRU lists T1, B1, T2, and B2 to empty. + * + * For every t>=1 and any xt, one and only one of the following four cases must occur. + * Case I: xt is in T1 or T2. A cache hit has occurred in ARC(c) and DBL(2c). + * Move xt to MRU position in T2. + * + * Case II: xt is in B1. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = min { p + d1,c } + * where d1 = { 1 if |B1| >= |B2|, |B2|/|B1| otherwise + * + * REPLACE(xt, p). Move xt from B1 to the MRU position in T2 (also fetch xt to the cache). + * + * Case III: xt is in B2. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = max { p - d2,0 } + * where d2 = { 1 if |B2| >= |B1|, |B1|/|B2| otherwise + * + * REPLACE(xt, p). Move xt from B2 to the MRU position in T2 (also fetch xt to the cache). + * + * Case IV: xt is not in T1 U B1 U T2 U B2. A cache miss has occurred in ARC(c) and DBL(2c). + * Case A: L1 = T1 U B1 has exactly c pages. + * If (|T1| < c) + * Delete LRU page in B1. REPLACE(xt,p). + * else + * Here B1 is empty. Delete LRU page in T1 (also remove it from the cache). + * endif + * Case B: L1 = T1 U B1 has less than c pages. + * If (|T1| + |T2| + |B1| + |B2| >= c) + * Delete LRU page in B2, if (|T1| + |T2| + |B1| + |B2| = 2c). + * REPLACE(xt, p). + * endif + * + * Finally, fetch xt to the cache and move it to MRU position in T1. + * + * Subroutine REPLACE(xt,p) + * If ( (|T1| is not empty) and ((|T1| exceeds the target p) or (xt is in B2 and |T1| = p)) ) + * Delete the LRU page in T1 (also remove it from the cache), and move it to MRU position in B1. + * else + * Delete the LRU page in T2 (also remove it from the cache), and move it to MRU position in B2. + * endif + */ + +#include "arc.pmh" + +#define IID_INVAL -1 /* XXX: move to header ? */ + +/* Temp variable to hold LRU item */ +hidden arc_item LRUitem; + +/* Adaptation "delta" variables */ +int d1, d2; +int p = 0; + +/* Declare arc lists - "shadow/ghost cache directories" */ +arc_list B1, B2, T1, T2; + +inline REPLACE(/* arc_item */ x_t, /* int */ p) +{ + /* + * Since LRUitem is declared in scope p_ARC, we expect it to be only accessible from there and REPLACE() + * as REPLACE() is only expected to be called from p_ARC. + * XXX: May need to revisit due to Modex related limitations. + */ + init_arc_item(LRUitem, IID_INVAL, false); + + if + :: + (lengthof(T1) != 0) && + ((lengthof(T1) > p) || (memberof(B2, x_t) && (lengthof(T1) == p))) + -> + d_step { + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + addMRU(B1, LRUitem); + } + + :: + else + -> + d_step { + readLRU(T2, LRUitem); + delLRU(T2); + cacheremove(LRUitem); + addMRU(B2, LRUitem); + } + fi +} + +inline ARC(/* arc_item */ x_t) +{ + if + :: /* Case I */ + memberof(T1, x_t) + -> + d_step { + delitem(T1, x_t); + addMRU(T2, x_t); + } + :: /* Case I */ + memberof(T2, x_t) + -> + d_step { + delitem(T2, x_t); + addMRU(T2, x_t); + } + :: /* Case II */ + memberof(B1, x_t) + -> + d1 = ((lengthof(B1) >= lengthof(B2)) -> 1 : (lengthof(B2)/lengthof(B1))); + p = min((p + d1), C); + + REPLACE(x_t, p); + d_step { + delitem(B1, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + :: /* Case III */ + memberof(B2, x_t) + -> + d2 = ((lengthof(B2) >= lengthof(B1)) -> 1 : (lengthof(B1)/lengthof(B2))); + p = max(p - d2, 0); + + REPLACE(x_t, p); + d_step { + delitem(B2, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + :: /* Case IV */ + !(memberof(T1, x_t) || + memberof(B1, x_t) || + memberof(T2, x_t) || + memberof(B2, x_t)) + -> + if + :: /* Case A */ + ((lengthof(T1) + lengthof(B1)) == C) + -> + if + :: + (lengthof(T1) < C) + -> + delLRU(B1); + REPLACE(x_t, p); + :: + else + -> + assert(lengthof(B1) == 0); + d_step { + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + } + fi + :: /* Case B */ + ((lengthof(T1) + lengthof(B1)) < C) + -> + if + :: + ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) >= C) + -> + if + :: + ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) == (2 * C)) + -> + delLRU(B2); + :: + else + -> + skip; + fi + REPLACE(x_t, p); + :: + else + -> + skip; + fi + :: + else + -> + skip; + fi + cachefetch(x_t); + addMRU(T1, x_t); + fi + +} + +#if 0 /* Resolve this after modex extract foo */ +proctype p_arc(arc_item x_t) +{ + /* Serialise entry */ + mutex_enter(sc_lock); + + ARC(x_t); + + mutex_exit(sc_lock); +} +#endif diff -urN arc.null/Makefile arc/Makefile --- arc.null/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ arc/Makefile 2023-09-04 10:29:48.141325923 +0000 @@ -0,0 +1,72 @@ +# This set of spinroot related files were written by cherry +# in the Gregorian Calendar year AD.2023, in the month +# of February that year. +# +# We have two specification files and a properties file +# +# The properties file contains "constraint" sections +# such as ltl or never claims (either or, not both). +# The specification is divided into two files: +# the file with suffix '.drv' is a "driver" which +# instantiates processes that will ultimately "drive" the +# models under test. +# The file with the suffix '.pml' contains the process +# model code, which, is intended to be the formal specification +# for the code we are interested in writing in C. +# +# We process these files in slightly different ways during +# the dev cycle, but broadly speaking, the idea is to create +# a file called 'spinmodel.pml' which contains the final +# model file that is fed to spin. +# +# Note that when we use the model extractor tool "modex" to +# extract the 'specification' from C code written to implement +# the model defined above. We use a 'harness' file (see file with +# suffix '.prx' below. +# +# Once the harness has been run, spinmodel.pml should be +# synthesised and processed as usual. +# +# The broad idea is that software dev starts by writing the spec +# first, validating the model, and then implementing the model in +# C, after which we come back to extract the model from the C file +# and cross check our implementation using spin. +# +# If things go well, the constraints specified in the '.ltl' file +# should hold exactly for both the handwritten model, and the +# extracted one. + +spin-gen: arc.pml arc.drv arc.inv + cp arc.pml model #mimic modex + cat model > spinmodel.pml;cat arc.drv >> spinmodel.pml;cat arc.inv >> spinmodel.pml; + spin -am spinmodel.pml + +spin-build: spin-gen + cc -DVECTORSZ=65536 -o pan pan.c + +all: spin-gen spin-build + +# Verification related targets. +spin-run: spin-build + ./pan -a #Generate arc.pml.trail on error + +# You run the trace only if the spin run above failed and created a trail +spin-trace: spinmodel.pml.trail + spin -t spinmodel.pml -p -g # -p (statements) -g (globals) -l (locals) -s (send) -r (recv) + ./pan -r spinmodel.pml.trail -g + +# Housekeeping +spin-gen-clean: + rm -f spinmodel.pml # Our consolidated model file + rm -f _spin_nvr.tmp # Never claim file + rm -f model # Intermediate "model" file + rm -f pan.* # Spin generated source files + +spin-build-clean: + rm -f pan + +spin-run-clean: + rm -f spinmodel.pml.trail + +clean: spin-gen-clean spin-build-clean spin-run-clean + rm -f *~ From nobody Mon Sep 4 14:41:04 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RfWXf55vLz4rtlR for ; Mon, 4 Sep 2023 14:41:06 +0000 (UTC) (envelope-from des@freebsd.org) Received: from smtp.freebsd.org (smtp.freebsd.org [96.47.72.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "smtp.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RfWXf245Sz3FDF; Mon, 4 Sep 2023 14:41:06 +0000 (UTC) (envelope-from des@freebsd.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1693838466; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NTozw6KCJv2+RP5gVRRQSnLUBx7zQMzdeV/SqbDEc8I=; b=NFD5eO4Nh4UU6rQnLvxCWT7aOiaFlpruQF6JxnILZkxFf47unFZrgJSaBAydUYmJjazBWu EfvrLVzLRoWWuFtgaA+6NXZbDzvHos3PJ3Am2xKvQYdMFTbfLYA4C5ARkNvjojCUao16y2 uKQZzBkvmNzru4qQntfyK7l9RRtEWwPxGhNQQkmy5qGIJnZAaE5Xflq4bX/GqQ5wuR8Z6B 98rYRBPSAODlzHjuRbBbUhtboa65I5cOxyiR8thORd31fWwtqGHYTDGQaf4ZjyN2uBeKcx 8g3FbL6kOBHG3Z0xHTvEFihrBtnoE+0IZet6UFBi/CPaBgjWLKOHnBsJyMbh+A== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1693838466; a=rsa-sha256; cv=none; b=dDzxa72OhinGqU72QrGATn9+i7ceJtZjh4gW6q/CKk4c/NLk4ErI2mxxbEony7XiEQFLhO 5LprL5KwBMAVcIGrfOqrBeabXQQnqJOLS8Fx36VFsE4cmJpK6MEbVAD6G1PdtjpxZiCHp7 3BZrbl+8mo/dkybFGkMxydjFjZ3ytAFW/CYMIuR/ZMZ3amOHtjTUINZmuiJIhNxoQuk42f fan/5NQGRm1WaJ6pPKnVVk5W971KhSDNv2vhb/R+5yBRJeq03jQuj3Qj4WL33CrvjG5EuZ 5+dqIU/R+YI4tCMyGBz8E0Bn8oRWeksmE0XNGqxTPS+MosPfBqfC5CpTbLMxeA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1693838466; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NTozw6KCJv2+RP5gVRRQSnLUBx7zQMzdeV/SqbDEc8I=; b=lITlWXXqFhl7gGtXh0P6cqQu02Yva3o7ciEDmCFF1FTLWsxLPsz7npzagHkektdlvvqXRv ZttmW4tI4mfV5i1HMWOKeVwzsSCvwWyeMYtIZynqRw5CxuTaANhd/bbJL7FeJ2dkM6xGTl u9pLRxICqtN7QSE7fiKyYgIcKvggpQJ2iAK0PF/9X+5WIPb6hx9HClxc6QenjArijFm8KF v/X7gXMx408x7fqwjSaSta/Z8+2dHcdDhn8JogYxROI4lpo+AdpKFJFjm6tOS5Kt+8kuSY W8Bd7cbWtQWESHSJNFriapuR772yweqF2TR7X2ENza6r9LOpWtV4geC1hCQuww== Received: from ltc.des.no (unknown [IPv6:2001:4647:d671:0:36e8:94ff:feca:9834]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) (Authenticated sender: des) by smtp.freebsd.org (Postfix) with ESMTPSA id 4RfWXf0Nd3zqdL; Mon, 4 Sep 2023 14:41:06 +0000 (UTC) (envelope-from des@freebsd.org) Received: by ltc.des.no (Postfix, from userid 1001) id BE9464C8E9; Mon, 4 Sep 2023 16:41:04 +0200 (CEST) From: =?utf-8?Q?Dag-Erling_Sm=C3=B8rgrav?= To: "Mathew, Cherry G.*" Cc: freebsd-hackers@freebsd.org Subject: Re: ARC model specified in spinroot/promela In-Reply-To: <85jzt96qjz.fsf@bow.st> (Cherry G. Mathew's message of "Sat, 02 Sep 2023 06:24:16 +0000") References: <85jzt96qjz.fsf@bow.st> User-Agent: Gnus/5.13 (Gnus v5.13) Date: Mon, 04 Sep 2023 16:41:04 +0200 Message-ID: <86a5u2t30f.fsf@ltc.des.no> List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable "Mathew, Cherry G.*" writes: > I'm hoping that someone can help me complete the current run, as I don't > have the computing resources required to run the full model (about 16GB > RAM). 16 GB is not a huge amount of memory. Would it help if you had access to a jail or VM with enough memory to run the model yourself? DES --=20 Dag-Erling Sm=C3=B8rgrav - des@FreeBSD.org From nobody Mon Sep 4 15:32:41 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RfXhD158Cz4sHdg; Mon, 4 Sep 2023 15:32:44 +0000 (UTC) (envelope-from kevans@FreeBSD.org) Received: from smtp.freebsd.org (smtp.freebsd.org [96.47.72.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "smtp.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RfXhD0f2dz3TKv; Mon, 4 Sep 2023 15:32:44 +0000 (UTC) (envelope-from kevans@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1693841564; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WnMfo/YdMJSmNHHjRE4rIpFGDmSIEwOltYFTzlE5W2s=; b=cSaK2fjXWznCF1/T/GkOq4ov3Mt3eFaNb3BaW4DtEXZWMqLuh6gXsXn0jv9vzaYW1xklXs uELpBL9EFDOvbhnU3zxcgi+gVxOR1cBz3f83lcEpOGOxzACoeO286DK6FFn+3Kt34G3b5G Ra1fqTe3Jp8n4v9nECxGxjUUniFlWso7UH40bNdGYHhfPFIPbq+jX7gyp8+w6xQD1xWNJk BWpoyEUOEI/aoQLQJgXhi8zcOPmVydtbdVX6IFtCIa8f/UhfCQ1kfpirjuT0GvJ9Bd2NJg CDvwDKAGLLqFO1KfiS2MWHW2VqWvZF932rTLxrymZngFVaGxqfTA5X5RWIHU1A== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1693841564; a=rsa-sha256; cv=none; b=fdh5jazgox3MohRxSFmIQeToM+eNo4vcFRPgkM61TAHxYTYZu2tIhoHk8DNhI+7W4u0TOw QWIaFmizmWNMoltyZ7f2eP4nnI0VENdgG0uqbPlzkWph1HIRoyMgi7PvqTNAdruraGaUdK F/+cT174tSwCJAcWuzPOd++8QPv/02XjVNAjIbklRHOk1M3cjjpjAk9pN46/9BW2+RG1gZ 0E6XCwyVMfepEyD08+uNsYzU17TSpEdq8sH7uyhZ7mv61ZEkguUW6aHsVVWGs/i1cR/1v0 QRR5oyM90dQf9D19npCWHRIx2bEQw7UEBUVAuLGHH+UwMlbXtMS+ufiSlwy02Q== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1693841564; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WnMfo/YdMJSmNHHjRE4rIpFGDmSIEwOltYFTzlE5W2s=; b=oL1++Tjy5VmwMMirG2NSkF0viKYtf6lXFisNgP+SHvxYy16337DXhoFeigLMMyGv2vGayW I5RVmP9twiaWKW6MPXR1pfXrm8QTiC+c49WKUmOW7iWM1MzVI2RXTFj+IsiytYtXLDzujR WXZQWbsq3+C4yxioXFUfdPVPCxDI98KF4XjPHlAvwKPz21DsoIfy2Y8jb0Xyd5FZj5iaC7 W9LnXlpbm6VxLqn0ma6gP6QeehLboLzYPqL1bvMZZiAbgspDxPTX04J4ZiXdUf4NkjeMwL Xu5T/m2pKGFmKfDtIdMracxO0y6zC4cQqANqTYOVhHtv1UgoAs529fvfITBulw== Received: from [10.9.4.95] (unknown [209.182.120.176]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) (Authenticated sender: kevans/mail) by smtp.freebsd.org (Postfix) with ESMTPSA id 4RfXhC4BTSzrH9; Mon, 4 Sep 2023 15:32:43 +0000 (UTC) (envelope-from kevans@FreeBSD.org) Message-ID: Date: Mon, 4 Sep 2023 10:32:41 -0500 List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: FreeBSD arm64 Azure panic during reboot in add_route Content-Language: en-US To: Souradeep Chakrabarti , "freebsd-hackers@FreeBSD.org" , "freebsd-arm@FreeBSD.org" Cc: Wei Hu References: From: Kyle Evans In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/4/23 05:13, Souradeep Chakrabarti wrote: > Hi > I am working on bringing FreeBSD on Azure ARM64. When I am rebooting the FreeBSD arm64 in Azure public preview, > we are hitting following panic sometime for page fault: > db_trace_self_wrapper() at db_trace_self_wrapper+0x30 > vpanic() at vpanic+0x13c > panic() at panic+0x44 > data_abort() at data_abort+0x30c > handle_el1h_sync() at handle_el1h_sync+0x14 > --- exception, esr 0x8600000e > (null)() at 0xffffa0000c93bb00 > add_route() at add_route+0xc4 > add_route_flags() at add_route_flags+0x1b0 > rib_add_route() at rib_add_route+0x324 > ifa_maintain_loopback_route() at ifa_maintain_loopback_route+0xf4 > in6_update_ifa() at in6_update_ifa+0x994 > in6_ifattach() at in6_ifattach+0x1bc > in6_if_up() at in6_if_up+0x90 > if_up() at if_up+0xd8 > ifhwioctl() at ifhwioctl+0xb7c > ifioctl() at ifioctl+0x860 > kern_ioctl() at kern_ioctl+0x2dc > sys_ioctl() at sys_ioctl+0x118 > do_el0_sync() at do_el0_sync+0x520 > handle_el0_sync() at handle_el0_sync+0x44 > > The panic is coming when add_route is called for loopback interface ipv6 attachment. > Upon more investigating it looks like the panic happens in rib_notify() . > > Please let me know how to debug it further to find the RC. > I have already opened a bug to track it : https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=272666 > Hi, I note that Andy has an unanswered question in that PR (comment #9) from 2023/08/14. Do you have a coredump from this that you can poke around in easily with kgdb? Thanks, Kyle Evans From nobody Mon Sep 4 15:59:41 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RfYJ50P6Cz4rJ4Y for ; Mon, 4 Sep 2023 16:00:21 +0000 (UTC) (envelope-from c@bow.st) Received: from comms.drone (in.bow.st [71.19.146.166]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4RfYJ40FWLz3d0w; Mon, 4 Sep 2023 16:00:20 +0000 (UTC) (envelope-from c@bow.st) Authentication-Results: mx1.freebsd.org; dkim=none; spf=pass (mx1.freebsd.org: domain of c@bow.st designates 71.19.146.166 as permitted sender) smtp.mailfrom=c@bow.st; dmarc=none Received: from homebase (unknown [IPv6:fe80::ff1d:976a:a7e4:ee6a]) by comms.drone (Postfix) with ESMTPSA id 9E18CFCB5; Mon, 4 Sep 2023 16:00:14 +0000 (UTC) From: "Mathew\, Cherry G.*" To: Dag-Erling =?utf-8?Q?Sm=C3=B8rgrav?= Cc: freebsd-hackers@freebsd.org Subject: Re: ARC model specified in spinroot/promela References: <85jzt96qjz.fsf@bow.st> <86a5u2t30f.fsf@ltc.des.no> Date: Mon, 04 Sep 2023 15:59:41 +0000 In-Reply-To: <86a5u2t30f.fsf@ltc.des.no> ("Dag-Erling \=\?utf-8\?Q\?Sm\=C3\=B8rg\?\= \=\?utf-8\?Q\?rav\=22's\?\= message of "Mon, 04 Sep 2023 16:41:04 +0200") Message-ID: <85il8qrksy.fsf@bow.st> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (berkeley-unix) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spamd-Bar: / X-Spamd-Result: default: False [-0.11 / 15.00]; HFILTER_HELO_IP_A(1.00)[comms.drone]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.88)[-0.881]; NEURAL_SPAM_MEDIUM(0.67)[0.668]; HFILTER_HELO_NORES_A_OR_MX(0.30)[comms.drone]; R_SPF_ALLOW(-0.20)[+mx]; MIME_GOOD(-0.10)[text/plain]; ONCE_RECEIVED(0.10)[]; TO_DN_SOME(0.00)[]; R_DKIM_NA(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_ONE(0.00)[1]; MIME_TRACE(0.00)[0:+]; RCVD_TLS_ALL(0.00)[]; ASN(0.00)[asn:47066, ipnet:71.19.146.0/24, country:US]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org]; RCPT_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; DMARC_NA(0.00)[bow.st]; BLOCKLISTDE_FAIL(0.00)[71.19.146.166:server fail]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 4RfYJ40FWLz3d0w >>>>> Dag-Erling Sm=C3=B8rgrav writes: > "Mathew, Cherry G.*" writes: >> I'm hoping that someone can help me complete the current run, as >> I don't have the computing resources required to run the full >> model (about 16GB RAM). > 16 GB is not a huge amount of memory. Would it help if you had > access to a jail or VM with enough memory to run the model > yourself? Hi DES, You probably caught up on the rest of the thread - I figured out a way to reduce the state space explosion (it's got to do with how spin/promela semantics map to regular function style languages) - in the end, it all came down to just around a second runtime. I think the complexity will remain there, until I improve it for re-entrancy/concurrency/multi-threaded use. (currently the code/model assumes no re-entry). I will fall back on your offer if it becomes unmanageable then. Many Thanks, --=20 ~cherry From nobody Mon Sep 4 19:15:42 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rfddn6Btsz4ryGG for ; Mon, 4 Sep 2023 19:15:57 +0000 (UTC) (envelope-from tomek@cedro.info) Received: from mail-yw1-x112d.google.com (mail-yw1-x112d.google.com [IPv6:2607:f8b0:4864:20::112d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Rfddn1CWJz4GQc for ; Mon, 4 Sep 2023 19:15:57 +0000 (UTC) (envelope-from tomek@cedro.info) Authentication-Results: mx1.freebsd.org; dkim=pass header.d=cedro.info header.s=google header.b=ex698rdu; spf=none (mx1.freebsd.org: domain of tomek@cedro.info has no SPF policy when checking 2607:f8b0:4864:20::112d) smtp.mailfrom=tomek@cedro.info; dmarc=none Received: by mail-yw1-x112d.google.com with SMTP id 00721157ae682-58dfe2d5b9aso23307457b3.1 for ; Mon, 04 Sep 2023 12:15:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cedro.info; s=google; t=1693854955; x=1694459755; darn=freebsd.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=2BTErTFzchVhLBOjcMX1j2J5ItoshO4LI1qia6cRq0c=; b=ex698rduB6MZqSJks/TxO2IcGPq7+F0ihjnjzHStt4RKF1Cmu+CwLJgJNajnc32+yr F/CjtA1gSDt29U4d1oz9xv5nMSxPMfDP1NINjRX6rHmukP1Qh3J3FzpWaqb+ZcMxfRgo ssN6mkErAJFlGSAzfnZDp3RqWVYm2ZmjYrg2YMo2dX65c4CsNeYjPMBOyU5Wa0TLqfd1 5WbijHIIADFPRr4kajB6Ivi+wgh9EZNgnSz+Qy8CVj35YVrW40JNci4O+09TzRXR8yZM +sn9gUY46fRbgxfLiIi87QGIzAFmtp7/iHNefuowzik90/wwcEm6ugVsNZ9gJ+XvwFck CMKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693854955; x=1694459755; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2BTErTFzchVhLBOjcMX1j2J5ItoshO4LI1qia6cRq0c=; b=COaEDHEHdKe5ShHdV5VQSvRM6ROx4EWcWv1Gnop5AVEn0WzXWOQWoYl/99YCxBGA8d E8LUr6eOB4UREjykntC0FpLaMqHNpSco8xOzBWHrLFDYNWRToNee8Z7MGZUfBfnjscuL Iap6TN4jAQbVeeJ43MPdmuglHEJg/H/ubVpFOYe3ZVaaJEa6Ftt/fpBgSGsl4EQ7x5qW 3Q7gpxwhixy6IyvGfZc6V47nodIRnF+6et5oixEKXjkuCi1E57TmYE9nCpRO27DRFoya 8H3wmhmDCDfUPfKDKUocE8XWStOheLdxQgukOepd4rJbYv+K0ZFUy3S1rxlAE5AdTATN riog== X-Gm-Message-State: AOJu0Yw1jK0B+i+xJxzS+CHh2NFTxkAdKCJeUA2YHwviliueIdDKbFAn 3Fi5qmLBgKJ7Lp9VA72PDTpEsq/l0uOJj+xyIxc= X-Google-Smtp-Source: AGHT+IFtBmdFIS7M17EzQxOSzeEak6aYh3C5VH9HqLuPTRs4SuGDyXDKADOsAX9CrAIZSty8HtyJtg== X-Received: by 2002:a0d:eb10:0:b0:577:3f8c:fc60 with SMTP id u16-20020a0deb10000000b005773f8cfc60mr14707265ywe.1.1693854955449; Mon, 04 Sep 2023 12:15:55 -0700 (PDT) Received: from mail-yb1-f173.google.com (mail-yb1-f173.google.com. [209.85.219.173]) by smtp.gmail.com with ESMTPSA id y194-20020a0dd6cb000000b005950e1bbf11sm2739049ywd.60.2023.09.04.12.15.54 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Sep 2023 12:15:54 -0700 (PDT) Received: by mail-yb1-f173.google.com with SMTP id 3f1490d57ef6-d74a012e613so2311472276.1 for ; Mon, 04 Sep 2023 12:15:54 -0700 (PDT) X-Received: by 2002:a25:5cd:0:b0:d78:477e:442d with SMTP id 196-20020a2505cd000000b00d78477e442dmr13326857ybf.8.1693854954331; Mon, 04 Sep 2023 12:15:54 -0700 (PDT) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 References: <2D466F3C-527C-4EE1-8C3D-3E8CDD8D547F@yahoo.com> <543FBABC-C75A-4AB0-BFB6-1C7C15ECBA4E@longcount.org> <96A99928-4E8E-4AB1-BF3A-D026B280EC0E@yahoo.com> In-Reply-To: From: Tomek CEDRO Date: Mon, 4 Sep 2023 21:15:42 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: Very slow scp performance comparing to Linux [dd to /dev/null shows substantial FreeBSD vs. Ubuntu differences for bs=1k (or 1K) and bs=512] To: Wei Hu Cc: Mark Millard , Mark Saad , FreeBSD Hackers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spamd-Bar: --- X-Spamd-Result: default: False [-3.30 / 15.00]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-0.999]; R_DKIM_ALLOW(-0.20)[cedro.info:s=google]; MIME_GOOD(-0.10)[text/plain]; R_SPF_NA(0.00)[no SPF record]; RCVD_IN_DNSWL_NONE(0.00)[2607:f8b0:4864:20::112d:from,209.85.219.173:received]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org]; RCVD_VIA_SMTP_AUTH(0.00)[]; MIME_TRACE(0.00)[0:+]; FROM_EQ_ENVFROM(0.00)[]; RCVD_TLS_LAST(0.00)[]; DKIM_TRACE(0.00)[cedro.info:+]; TO_MATCH_ENVRCPT_SOME(0.00)[]; ASN(0.00)[asn:15169, ipnet:2607:f8b0::/32, country:US]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; TO_DN_ALL(0.00)[]; RCPT_COUNT_THREE(0.00)[4]; DMARC_NA(0.00)[cedro.info]; PREVIOUSLY_DELIVERED(0.00)[freebsd-hackers@freebsd.org]; RCVD_COUNT_THREE(0.00)[3]; FREEMAIL_CC(0.00)[yahoo.com,longcount.org,freebsd.org] X-Rspamd-Queue-Id: 4Rfddn1CWJz4GQc On Thu, Aug 31, 2023 at 9:56=E2=80=AFAM Wei Hu wrote: > Yes, the network perf gap is not as big as I originally thought. Seems di= fferent > factors contribute to the slowness of scp on FreeBSD. Network stack is on= ly one > of them. Note that Netflix uses FreeBSD because of _better_ network performance over Linux.. also better long term maintenance that comes from better organization, self-compatibility, and more stable kernel API that does not change every minor release ;-) Try the OS on a bare metal hardware, compare the results, use what fits you best. If the results are similar then find a problem in the VM hypervisor. If you think of a long term project and comfortable maintenance use FreeBSD even if you need to improve the driver it will pay back quite soon. --=20 CeDeROM, SQ7MHZ, http://www.tomek.cedro.info From nobody Mon Sep 4 19:47:27 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RffMN4D5Gz4sTfr for ; Mon, 4 Sep 2023 19:48:32 +0000 (UTC) (envelope-from Alexander@Leidinger.net) Received: from mailgate.Leidinger.net (mailgate.leidinger.net [IPv6:2a00:1828:2000:313::1:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature ECDSA (P-256) client-digest SHA256) (Client CN "mailgate.leidinger.net", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RffMN18fzz4R0w; Mon, 4 Sep 2023 19:48:32 +0000 (UTC) (envelope-from Alexander@Leidinger.net) Authentication-Results: mx1.freebsd.org; none Received: from webmail2.leidinger.net (roundcube.Leidinger.net [192.168.1.123]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (Client did not present a certificate) (Authenticated sender: Alexander@Leidinger.net) by outgoing.leidinger.net (Postfix) with ESMTPSA id C80F04571; Mon, 4 Sep 2023 21:47:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=leidinger.net; s=outgoing-alex; t=1693856897; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Bd9R3bVsArga+cpgqU3XhUNvBCdYC9UT36lugVRLjAQ=; b=WL/DX61S2TexX3eq9Jt/nHdPdMOiI0hEnXMkjmj5VCEE3DT5/joePEGDzklc1OKNRIOPl1 12lJ4jT7eVJJc8YgapDJQS5awkcbyXxCOrB5shxCfc/8x2tdCXvRe/cb+l9cVvJXC1b1jH EEM86M7Mu+W0ZnLLu8RUx4owkoAHeHilWkXuHuQjfc0wAQWNjnMYJM7L/tyFXr8jJ144/g 7bJ1vgIq93B6PNxgVwrutV8hG1QRq4Sy4W/xpFL2B5yxcp3uC6hjc95m9/t4YENZkzpY5B C2h9bkDq2K6WedMo/PqsnlQFk4N3+EUZPPlZy1O+V8/47zBalLQ3BYE20kkwKg== List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Date: Mon, 04 Sep 2023 21:47:27 +0200 From: Alexander Leidinger To: "Mathew, Cherry G.*" Cc: adridg@freebsd.org, freebsd-hackers@freebsd.org Subject: Re: ARC model specified in spinroot/promela In-Reply-To: <85a5u22oxx.fsf@bow.st> References: <85jzt96qjz.fsf@bow.st> <9c424a574cdd39fc879c9ed9192556c0@Leidinger.net> <858r9o6ee0.fsf@bow.st> <85pm304dzi.fsf@bow.st> <85a5u22oxx.fsf@bow.st> Message-ID: <1e3a17e39094a9630eebce9f91f00e30@Leidinger.net> X-Sender: Alexander@Leidinger.net Content-Type: multipart/signed; protocol="application/pgp-signature"; boundary="=_485de4d893b5ac7101fde483e9b6fbed"; micalg=pgp-sha256 X-Spamd-Bar: ---- X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:34240, ipnet:2a00:1828::/32, country:DE] X-Rspamd-Queue-Id: 4RffMN18fzz4R0w This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --=_485de4d893b5ac7101fde483e9b6fbed Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=US-ASCII; format=flowed Am 2023-09-04 12:49, schrieb Mathew, Cherry G.*: >>>>>> Mathew, Cherry G * writes: > > [...] > > > So there's room for improvement in my Makefile to: > > > 1) Explore multithreaded/CPU > > 2) Understand state space explosion scale - it is exponential to > > the number of processes, I've fixed it to run in a loop - will > > report back once I have good progress also with the model > > extraction part. > > 3) My model has errors - I'm glad to see that the error reporting > > is the same in my new optimised loop, as in the RAM hungry > version > > you ran. > > > Thanks once again - this is very helpful. I will report back once > > I have more progress. > > Hi Again, > > So just wanted to report back with a patch (absolute patch, not > relative, > so please nuke your existing arc/ if you tried the old one and apply in > a clean new subdirectory) on the following: # make spin-run cp arc.pml model #mimic modex cat model > spinmodel.pml;cat arc.drv >> spinmodel.pml;cat arc.inv >> spinmodel.pml; spin -am spinmodel.pml ltl ltl_0: (((((((((<> ([] ((_nr_pr==1)))) && ([] (((((len(T1.item_list)+len(B1.item_list))+len(T2.item_list))+len(B2.item_list))<=(2*64))))) && ([] (((len(T1.item_list)+len(B1.item_list))<=64)))) && ([] (((len(T2.item_list)+len(B2.item_list))<(2*64))))) && ([] (((len(T1.item_list)+len(T2.item_list))<=64)))) && ([] ((! (((((len(T1.item_list)+len(B1.item_list))+len(T2.item_list))+len(B2.item_list))<64))) || (((len(B1.item_list)==0)) && ((len(B2.item_list)==0)))))) && ([] ((! (((((len(T1.item_list)+len(B1.item_list))+len(T2.item_list))+len(B2.item_list))>=64))) || (((len(T1.item_list)+len(T2.item_list))==64))))) && ([] ((p<=64)))) && (<> (((len(T1.item_list)==p)) && ((len(T2.item_list)==(64-p)))))) && (<> ((p>0))) cc -DVECTORSZ=65536 -o pan pan.c ./pan -a #Generate arc.pml.trail on error error: max search depth too small (Spin Version 6.5.0 -- 1 July 2019) + Partial Order Reduction Full statespace search for: never claim + (ltl_0) assertion violations + (if within scope of claim) acceptance cycles + (fairness disabled) invalid end states - (disabled by never claim) State-vector 2124 byte, depth reached 9999, errors: 0 1 states, stored 11 states, matched 12 transitions (= stored+matched) 109989 atomic steps hash conflicts: 0 (resolved) Stats on memory usage (in Megabytes): 0.002 equivalent memory usage for states (stored*(State-vector + overhead)) 12.456 actual memory usage for states 128.000 memory used for hash table (-w24) 0.534 memory used for DFS stack (-m10000) 5.686 memory lost to fragmentation 140.500 total actual memory usage unreached in init spinmodel.pml:80, state 28, "D_STEP80" spinmodel.pml:80, state 53, "D_STEP80" spinmodel.pml:154, state 70, "B1.item_list?_" spinmodel.pml:80, state 79, "D_STEP80" spinmodel.pml:90, state 85, "D_STEP90" spinmodel.pml:78, state 86, "(((len(T1.item_list)!=0)&&((len(T1.item_list)>p)||(B2.item_list??[eval(x[x_iid].iid)]&&(len(T1.item_list)==p)))))" spinmodel.pml:78, state 86, "else" spinmodel.pml:73, state 88, "D_STEP73" spinmodel.pml:159, state 90, "assert((len(B1.item_list)==0))" spinmodel.pml:160, state 94, "D_STEP160" spinmodel.pml:152, state 95, "((len(T1.item_list)<64))" spinmodel.pml:152, state 95, "else" spinmodel.pml:183, state 100, "B2.item_list?_" spinmodel.pml:198, state 128, "(1)" spinmodel.pml:268, state 155, "-end-" (13 of 155 states) unreached in claim ltl_0 _spin_nvr.tmp:70, state 108, "-end-" (1 of 108 states) pan: elapsed time 0.164 seconds pan: rate 6.0952381 states/second No trail file generated... Bye, Alexander. -- http://www.Leidinger.net Alexander@Leidinger.net: PGP 0x8F31830F9F2772BF http://www.FreeBSD.org netchild@FreeBSD.org : PGP 0x8F31830F9F2772BF --=_485de4d893b5ac7101fde483e9b6fbed Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc; size=833 Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEER9UlYXp1PSd08nWXEg2wmwP42IYFAmT2NF8ACgkQEg2wmwP4 2IYhuQ/+KvWE/uUmjPAsNoDIyaMZTFWq51fxWUZUVERNUIbUtCKLA2u3YqfT/BUM g353QgBLaJ/o9D+b8yufymXa1AQCsUUQLVtxdSAaUdi+mbJg45t/ZLuJftmp8qFu SaktD+UVpPymQO6PRABPAyHL5wYF1+Hhl4qquccLeooyYOC65Bhk6Ei2IM+tNpkM pnzn05CM+Yxy6+syHuwCXv0o/M+M7dF8FziiKaj7YnVvvBK34XcRjnMiLF5k+TxJ MS0fei0jobqD4NIwyUKcx2oaTwoiIrZ8pcU67F+IhErjm7JBNi0/1IL03QeUIEA5 ko+OBFe7IVEG3S3OSDyjFZPs9no2g07oRb3T8ihI1ecOcYIGlTSPoFT1//pkzA1g 4P/dy7Dsz042inhVTJOQSH3YuhszIa/2NcpSsWKv2m1sgSgVMwbMLnNBb6xcoXxY nQ8SOrOielbofZSBsUvXq8am6pIbnKDQR0yoIPXXTIBF/tVZ9+tUXc6DkZXSg3Yh Zd4CDbOA1Xb6jFJwZVLkGrtN+zPM6EALhs+HWgAz7JWNxWHPfb4DImxvkEfeAl+m lXW9ffzyBUrXv2iC5ipUAvWzwmUj+cS02q4uj9uC5Wy+v3XyOoJUCtZPVf7zLZV6 XBmr9ZfexXPtbXhDkt/KoyT4Qdyx5Q9eMgaqejbv6Ov2ux+QYdM= =+w6P -----END PGP SIGNATURE----- --=_485de4d893b5ac7101fde483e9b6fbed-- From nobody Mon Sep 4 23:44:19 2023 X-Original-To: hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rflbl5kHVz4rm80 for ; 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Mon, 04 Sep 2023 16:44:31 -0700 (PDT) Received: from smtpclient.apple ([2600:1700:5430:10b1:bd53:4baa:f6a1:5b2e]) by smtp.gmail.com with ESMTPSA id w10-20020a170902e88a00b001bbd8cf6b57sm8063756plg.230.2023.09.04.16.44.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Sep 2023 16:44:30 -0700 (PDT) From: Christopher Bowman Content-Type: multipart/alternative; boundary="Apple-Mail=_15CB57CB-A5DB-4F0C-B748-B95ABD7615D3" List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3731.500.231\)) Subject: Trouble booting current on ARM Message-Id: Date: Mon, 4 Sep 2023 16:44:19 -0700 To: hackers@freebsd.org X-Mailer: Apple Mail (2.3731.500.231) X-Spamd-Bar: -- X-Spamd-Result: default: False [-2.80 / 15.00]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-1.000]; MV_CASE(0.50)[]; R_DKIM_ALLOW(-0.20)[chrisbowman-com.20230601.gappssmtp.com:s=20230601]; MIME_GOOD(-0.10)[multipart/alternative,text/plain]; RCVD_TLS_LAST(0.00)[]; MLMMJ_DEST(0.00)[hackers@freebsd.org]; RCVD_IN_DNSWL_NONE(0.00)[2607:f8b0:4864:20::634:from]; R_SPF_NA(0.00)[no SPF record]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+,1:+,2:~]; ASN(0.00)[asn:15169, ipnet:2607:f8b0::/32, country:US]; DKIM_TRACE(0.00)[chrisbowman-com.20230601.gappssmtp.com:+]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; DMARC_NA(0.00)[chrisbowman.com]; TO_MATCH_ENVRCPT_ALL(0.00)[]; PREVIOUSLY_DELIVERED(0.00)[hackers@freebsd.org]; TO_DN_NONE(0.00)[]; RCPT_COUNT_ONE(0.00)[1]; MID_RHS_MATCH_FROM(0.00)[] X-Rspamd-Queue-Id: 4Rflbk4pDHz4JXK --Apple-Mail=_15CB57CB-A5DB-4F0C-B748-B95ABD7615D3 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 I=E2=80=99ve been using an Arty-Z7 from Diligent for several years now. = This is a AMD/Xilinx ZYNQ based board. It=E2=80=99s mostly similar to a = ZED board which has an in tree kernel cobfug. It has worked fine with = 13.0. I=E2=80=99m now looking to mow my work forward and keep pace with = the project. I=E2=80=99d like to eventually upgrade to 14.0 when it = comes out. In preparation I built a new release using sources from = after the 14.0 branch. I=E2=80=99m able to cross build fine but when I = boot the kernel I see the crash below, Has anyone seen panic: Storing = an invalid VFP state. Any information or ideas about what might be = happening before I try to debug? Any information at all would be = helpful. Is anyone else running a Zynq based board of any kind with a recent 14.0 = or current kernel? Thanks for any help, Christopher GDB: debug ports: uart GDB: current port: uart KDB: debugger backends: ddb gdb KDB: current backend: ddb Copyright (c) 1992-2023 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights = reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 15.0-CURRENT armv7 1500000 #3 main-n265107-03d104888cae: Fri Sep = 1 20:18:55 PDT 2023 crb@eclipse.ChrisBowman.com:/usr/obj/tmp/src/arm.armv7/sys/ARTYZ7 = arm FreeBSD clang version 16.0.6 (https://github.com/llvm/llvm-project.git = llvmorg-16.0.6-0-g7cbf1a259152) WARNING: WITNESS option enabled, expect reduced performance. WARNING: 32-bit kernels are deprecated and may be removed in FreeBSD = 15.0. CPU: ARM Cortex-A9 r3p0 (ECO: 0x00000000) CPU Features:=20 Multiprocessing, Thumb2, Security, VMSAv7, Coherent Walk Optional instructions:=20 UMULL, SMULL, SIMD(ext) LoUU:2 LoC:2 LoUIS:2=20 Cache level 1: 32KB/32B 4-way data cache WB Read-Alloc Write-Alloc 32KB/32B 4-way instruction cache Read-Alloc real memory =3D 536866816 (511 MB) avail memory =3D 511369216 (487 MB) FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs arc4random: WARNING: initial seeding bypassed the cryptographic random = device because it was not yet seeded and the knob = 'bypass_before_seeding' was enabled. random: entropy device external interface ofwbus0: regfix0: on ofwbus0 simplebus0: on ofwbus0 simple_mfd0: mem = 0xf8000000-0xf8000fff on simplebus0 l2cache0: mem 0xf8f02000-0xf8f02fff irq 8 on = simplebus0 l2cache0: cannot allocate IRQ, not using interrupt l2cache0: Part number: 0x3, release: 0x8 l2cache0: L2 Cache enabled: 512KB/32B 8 ways gic0: mem = 0xf8f01000-0xf8f01fff,0xf8f00100-0xf8f001ff on simplebus0 gic0: pn 0x39, arch 0x1, rev 0x2, implementer 0x43b irqs 96 mp_tmr0: mem 0xf8f00200-0xf8f0021f irq 29 on = simplebus0 Timecounter "MPCore" frequency 50000000 Hz quality 800 mp_tmr1: mem 0xf8f00600-0xf8f0061f irq 36 on = simplebus0 Event timer "MPCore" frequency 50000000 Hz quality 1000 cpulist0: on ofwbus0 cpu0: on cpulist0 uart0: mem 0xe0000000-0xe0000fff irq 9 on simplebus0 uart0: console (-1,n,8,1) zy7_qspi0: mem 0xe000d000-0xe000dfff = irq 13 on simplebus0 zy7_qspi0: must have ref-clock property device_attach: zy7_qspi0 attach returned 6 cgem0: mem = 0xe000b000-0xe000bfff irq 14 on simplebus0 cgem0: could not retrieve reference clock. miibus0: on cgem0 rgephy0: PHY 0 on = miibus0 rgephy0: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, = 1000baseT-FDX, 1000baseT-FDX-master, auto rgephy1: PHY 1 on = miibus0 rgephy1: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, = 1000baseT-FDX, 1000baseT-FDX-master, auto cgem0: Ethernet address: 66:da:ac:ca:9e:86 sdhci_fdt0: mem = 0xe0100000-0xe0100fff irq 17 on simplebus0 sdhci_fdt0: 1 slot(s) allocated mmc0: on sdhci_fdt0 zy7_devcfg0: mem 0xf8007000-0xf80070ff irq 28 on = simplebus0 Timecounters tick every 1.000 msec usb_needs_explore_all: no devclass panic: Storing an invalid VFP state cpuid =3D 0 time =3D 1 KDB: stack backtrace: db_trace_self() at db_trace_self pc =3D 0xc04fcbf8 lr =3D 0xc0071424 = (db_trace_self_wrapper+0x30) sp =3D 0xc0a14930 fp =3D 0xc0a14a48 db_trace_self_wrapper() at db_trace_self_wrapper+0x30 pc =3D 0xc0071424 lr =3D 0xc02039cc (vpanic+0x140) sp =3D 0xc0a14a50 fp =3D 0xc0a14a70 r4 =3D 0x00000100 r5 =3D 0x00000000 r6 =3D 0xc05b70fb r7 =3D 0xc072f7a8 vpanic() at vpanic+0x140 pc =3D 0xc02039cc lr =3D 0xc02037ac (doadump) sp =3D 0xc0a14a78 fp =3D 0xc0a14a7c r4 =3D 0x2009e010 r5 =3D 0xcfc96000 r6 =3D 0xc06f6da9 r7 =3D 0xcf0cce90 r8 =3D 0xc07a2800 r9 =3D 0xc07408c4 r10 =3D 0xc071f1e0 doadump() at doadump pc =3D 0xc02037ac lr =3D 0xc0520eb0 (fpu_kern_enter) sp =3D 0xc0a14a84 fp =3D 0xc0a14a90 r4 =3D 0xc071f1e0 r5 =3D 0xc0a14a7c r6 =3D 0xc02037ac r10 =3D 0xc0a14a84 fpu_kern_enter() at fpu_kern_enter pc =3D 0xc0520eb0 lr =3D 0xc051e0c8 (cpu_switch+0x5c) sp =3D 0xc0a14a98 fp =3D 0xcfc96000 r4 =3D 0xc0520eb0 r5 =3D 0xc0a14e90 r6 =3D 0x00000000 r10 =3D 0xc07a2800 cpu_switch() at cpu_switch+0x5c pc =3D 0xc051e0c8 lr =3D 0xc051e0c8 (cpu_switch+0x5c) sp =3D 0xc0a14a98 fp =3D 0xcfc96000 Unwind failure (no registers changed) KDB: enter: panic [ thread pid 0 tid 100000 ] Stopped at kdb_enter+0x54: ldrb r15, [r15, r15, ror r15]! db>=20= --Apple-Mail=_15CB57CB-A5DB-4F0C-B748-B95ABD7615D3 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8 I=E2=80=99ve = been using an Arty-Z7 from Diligent for several years now.  This is = a AMD/Xilinx ZYNQ based board.  It=E2=80=99s mostly similar to a = ZED board which has an in tree kernel cobfug.  It has worked fine = with 13.0.  I=E2=80=99m now looking to mow my work forward and keep = pace with the project.  I=E2=80=99d like to eventually upgrade to = 14.0 when it comes out.  In preparation I built a new release using = sources from after the 14.0 branch.  I=E2=80=99m able to cross = build fine but when I boot the kernel I see the crash below,  Has = anyone seen panic: Storing an invalid VFP state. =  Any information or ideas about what might be happening before I = try to debug?  Any information at all would be = helpful.

Is anyone else running a Zynq based board of = any kind with a recent 14.0 or current kernel?
Thanks for any = help,
Christopher



GDB: debug ports: uart

GDB: current port: uart

KDB: debugger backends: ddb gdb

KDB: current backend: ddb

Copyright (c) 1992-2023 The FreeBSD Project.

Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, = 1992, 1993, 1994

= The Regents of the University of California. All rights = reserved.

FreeBSD is a registered trademark of The FreeBSD = Foundation.

FreeBSD 15.0-CURRENT armv7 1500000 #3 = main-n265107-03d104888cae: Fri Sep  1 20:18:55 PDT 2023

    = crb@eclipse.ChrisBowman.com:/usr/obj/tmp/src/arm.armv7/sys/ARTYZ7 = arm

FreeBSD clang version 16.0.6 = (https://github.com/llvm/llvm-project.git = llvmorg-16.0.6-0-g7cbf1a259152)

WARNING: WITNESS option enabled, expect reduced = performance.

WARNING: 32-bit kernels are deprecated and may be = removed in FreeBSD 15.0.

CPU: ARM Cortex-A9 r3p0 (ECO: 0x00000000)

CPU Features: 

  Multiprocessing, Thumb2, Security, VMSAv7, = Coherent Walk

Optional instructions: 

  UMULL, SMULL, SIMD(ext)

LoUU:2 LoC:2 LoUIS:2 

Cache level 1:

 32KB/32B 4-way data cache WB Read-Alloc = Write-Alloc

 32KB/32B 4-way instruction cache Read-Alloc

real memory  =3D 536866816 (511 MB)

avail memory =3D 511369216 (487 MB)

FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs

arc4random: WARNING: initial seeding bypassed the = cryptographic random device because it was not yet seeded and the knob = 'bypass_before_seeding' was enabled.

random: entropy device external interface

ofwbus0: <Open Firmware Device Tree>

regfix0: <Fixed Regulator> on ofwbus0

simplebus0: <Flattened device tree simple bus> on = ofwbus0

simple_mfd0: <Simple MFD (Multi-Functions = Device)> mem 0xf8000000-0xf8000fff on simplebus0

l2cache0: <PL310 L2 cache controller> mem = 0xf8f02000-0xf8f02fff irq 8 on simplebus0

l2cache0: cannot allocate IRQ, not using interrupt

l2cache0: Part number: 0x3, release: 0x8

l2cache0: L2 Cache enabled: 512KB/32B 8 ways

gic0: <ARM Generic Interrupt Controller> mem = 0xf8f01000-0xf8f01fff,0xf8f00100-0xf8f001ff on simplebus0

gic0: pn 0x39, arch 0x1, rev 0x2, implementer 0x43b = irqs 96

mp_tmr0: <ARM MPCore Timers> mem = 0xf8f00200-0xf8f0021f irq 29 on simplebus0

Timecounter "MPCore" frequency 50000000 Hz quality = 800

mp_tmr1: <ARM MPCore Timers> mem = 0xf8f00600-0xf8f0061f irq 36 on simplebus0

Event timer "MPCore" frequency 50000000 Hz quality = 1000

cpulist0: <Open Firmware CPU Group> on = ofwbus0

cpu0: <Open Firmware CPU> on cpulist0

uart0: <Cadence UART> mem 0xe0000000-0xe0000fff = irq 9 on simplebus0

uart0: console (-1,n,8,1)

zy7_qspi0: <Zynq Quad-SPI Flash Controller> mem = 0xe000d000-0xe000dfff irq 13 on simplebus0

zy7_qspi0: must have ref-clock property

device_attach: zy7_qspi0 attach returned 6

cgem0: <Cadence CGEM Gigabit Ethernet Interface> = mem 0xe000b000-0xe000bfff irq 14 on simplebus0

cgem0: could not retrieve reference clock.

miibus0: <MII bus> on cgem0

rgephy0: <RTL8169S/8110S/8211 1000BASE-T media = interface> PHY 0 on miibus0

rgephy0:  none, 10baseT, 10baseT-FDX, 100baseTX, = 100baseTX-FDX, 1000baseT-FDX, 1000baseT-FDX-master, auto

rgephy1: <RTL8169S/8110S/8211 1000BASE-T media = interface> PHY 1 on miibus0

rgephy1:  none, 10baseT, 10baseT-FDX, 100baseTX, = 100baseTX-FDX, 1000baseT-FDX, 1000baseT-FDX-master, auto

cgem0: Ethernet address: 66:da:ac:ca:9e:86

sdhci_fdt0: <Zynq-7000 generic fdt SDHCI = controller> mem 0xe0100000-0xe0100fff irq 17 on simplebus0

sdhci_fdt0: 1 slot(s) allocated

mmc0: <MMC/SD bus> on sdhci_fdt0

zy7_devcfg0: <Zynq devcfg block> mem = 0xf8007000-0xf80070ff irq 28 on simplebus0

Timecounters tick every 1.000 msec

usb_needs_explore_all: no devclass

panic: Storing an invalid VFP state

cpuid =3D 0

time =3D 1

KDB: stack backtrace:

db_trace_self() at db_trace_self

= pc =3D 0xc04fcbf8  lr =3D 0xc0071424 = (db_trace_self_wrapper+0x30)

= sp =3D 0xc0a14930  fp =3D 0xc0a14a48

db_trace_self_wrapper() at = db_trace_self_wrapper+0x30

= pc =3D 0xc0071424  lr =3D 0xc02039cc = (vpanic+0x140)

= sp =3D 0xc0a14a50  fp =3D 0xc0a14a70

= r4 =3D 0x00000100  r5 =3D 0x00000000

= r6 =3D 0xc05b70fb  r7 =3D 0xc072f7a8

vpanic() at vpanic+0x140

= pc =3D 0xc02039cc  lr =3D 0xc02037ac (doadump)

= sp =3D 0xc0a14a78  fp =3D 0xc0a14a7c

= r4 =3D 0x2009e010  r5 =3D 0xcfc96000

= r6 =3D 0xc06f6da9  r7 =3D 0xcf0cce90

= r8 =3D 0xc07a2800  r9 =3D 0xc07408c4

= r10 =3D 0xc071f1e0

doadump() at doadump

= pc =3D 0xc02037ac  lr =3D 0xc0520eb0 = (fpu_kern_enter)

= sp =3D 0xc0a14a84  fp =3D 0xc0a14a90

= r4 =3D 0xc071f1e0  r5 =3D 0xc0a14a7c

= r6 =3D 0xc02037ac r10 =3D 0xc0a14a84

fpu_kern_enter() at fpu_kern_enter

= pc =3D 0xc0520eb0  lr =3D 0xc051e0c8 = (cpu_switch+0x5c)

= sp =3D 0xc0a14a98  fp =3D 0xcfc96000

= r4 =3D 0xc0520eb0  r5 =3D 0xc0a14e90

= r6 =3D 0x00000000 r10 =3D 0xc07a2800

cpu_switch() at cpu_switch+0x5c

= pc =3D 0xc051e0c8  lr =3D 0xc051e0c8 = (cpu_switch+0x5c)

= sp =3D 0xc0a14a98  fp =3D 0xcfc96000

Unwind failure (no registers changed)

KDB: enter: panic

[ thread pid 0 tid 100000 ]

Stopped at      kdb_enter+0x54: = ldrb    r15, [r15, r15, ror r15]!

db> 

= --Apple-Mail=_15CB57CB-A5DB-4F0C-B748-B95ABD7615D3-- From nobody Tue Sep 5 19:48:59 2023 X-Original-To: hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RgGKV0pYwz4sGTX for ; Tue, 5 Sep 2023 19:49:02 +0000 (UTC) (envelope-from des@freebsd.org) Received: from smtp.freebsd.org (smtp.freebsd.org [IPv6:2610:1c1:1:606c::24b:4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "smtp.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RgGKV0C3Nz4c61 for ; Tue, 5 Sep 2023 19:49:02 +0000 (UTC) (envelope-from des@freebsd.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1693943342; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=6Mk0KLCSAOqNHnJWOg0+8iefrVQm+N7c/0jZpLK+Cms=; b=KrRH0FR0llZqrk3lBPSYBjVwOxpeMt/q3PnTyQE3zQDbRQ4X7tZwoX3GgjgzxX97TNOSjr MKHmN6hXrGoBPdEyiplx1kEdO99A29S4fdy5MbXqMaE6JIqNpXaqwuuv03Hw00W95ZHq4o EXRlO/XqsU+AROcS9hQNOcDetxBPQAi1PKodRwknbNk5TzZQK6zyoSnknLKePpviYBTHho tYoAcmHY2cPn7wdsF58Vvxl2Xe8To0sRH70EIrodF6jYV0ULvkpn7dRqkFbTFDwakUMMW+ 2jheMllkPRGIy42xoCeAOtqsjzGsywV9Kg2cAQoA9ESGPBCZT0atW1fGBPPmig== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1693943342; a=rsa-sha256; cv=none; b=f5aOM4Y174RGsAZF11CgWDZRjgYXpcPNMydEXBKOBxTugSxN4xDEfF+8tJ4kqsTdEQfAL6 6usPpyd32ZjxwcZT5CnZgDy2yeeBsHTQKdp9e7BCCGleAVvZmaNKoWBz2Of5fZOuJ862nl pet9dSmJeDdBSXFWSEDwRUb+kIf3rsM0uzoM5jSNo3xx4bRewkAMApNtarqAlN1oD4nwIU RGz+D8vcXPGHQgysHLR0czvll5DAT5LR37+lrho5F3+9OEHdBd3OBejbaLuzUVcmvqhT7Q PAAMb7RFAWMz0qtqRBi+unA/9cQlchEvZVJBsowu7H7HUsPhj0cARMLZFVfBEg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1693943342; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=6Mk0KLCSAOqNHnJWOg0+8iefrVQm+N7c/0jZpLK+Cms=; b=edFzbgJqnvBRC43/0aC6TymHVlAxuGOhiGeqyt1fR6Bz45Abuj4FAKO3I9awGloy/ew8Os TEYt1j8a3ea2gfUlgO1EPNkTOJymgK+zbAR4WoBG1BSPFYRwht3zURYJj22aDKnd8VYltj mAwduH8QiV7TCOxmZZvuzQnyR5tKPi/TDs/iUC9FZUUJk4RjDvzg2pp6pVFc50Awx0BL6b hE7pNUcsENuOc65ACJ8OwMD8ZYouvM/Tsuiwk8B88F/38jh8LGb7KrhOijKY8I4nn2NbPI 40WlgkHSmGCscc2ns6exdXpQTi/UiZ+z4jLmuCtyEHQTvjk6nHF2wGlsDXKNUg== Received: from ltc.des.no (unknown [IPv6:2001:4647:d671:0:36e8:94ff:feca:9834]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) (Authenticated sender: des) by smtp.freebsd.org (Postfix) with ESMTPSA id 4RgGKT5XJCz1NRq for ; Tue, 5 Sep 2023 19:49:01 +0000 (UTC) (envelope-from des@freebsd.org) Received: by ltc.des.no (Postfix, from userid 1001) id 41D9A4CEE1; Tue, 5 Sep 2023 21:48:59 +0200 (CEST) From: =?utf-8?Q?Dag-Erling_Sm=C3=B8rgrav?= To: hackers@freebsd.org Subject: Please help review C23 features User-Agent: Gnus/5.13 (Gnus v5.13) Date: Tue, 05 Sep 2023 21:48:59 +0200 Message-ID: <86a5u0s8no.fsf@ltc.des.no> List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable As you may have noticed, I've been working on adding C23 features to libc. I have a few more patches in flight which I'd like to get committed in time for 14.0 but which still await review: - Add a wchar version of the snprintf test for N2630 (formatted binary inte= gers) https://reviews.freebsd.org/D41726 - Implement N2680 (specific-width length modifier) https://reviews.freebsd.org/D41725 - Add test cases for N2680 (and fix some nits in the N2630 tests) https://reviews.freebsd.org/D41743 - Implement N2867 (checked integer arithmetic) https://reviews.freebsd.org/D41734 - Add tests for N2867 https://reviews.freebsd.org/D41735 This is far from everything we need for C23 (clang 16 understands N2630 but not N2680, for instance, and we're still missing ) but it gets us pretty close. DES -- Dag-Erling Sm=C3=B8rgrav - des@FreeBSD.org From nobody Wed Sep 6 05:53:58 2023 X-Original-To: hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RgWlp4qLFz4srR8 for ; Wed, 6 Sep 2023 05:54:14 +0000 (UTC) (envelope-from crb@chrisbowman.com) Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RgWln5vLVz4JFn for ; Wed, 6 Sep 2023 05:54:13 +0000 (UTC) (envelope-from crb@chrisbowman.com) Authentication-Results: mx1.freebsd.org; dkim=pass header.d=chrisbowman-com.20230601.gappssmtp.com header.s=20230601 header.b="wh81q0X/"; spf=none (mx1.freebsd.org: domain of crb@chrisbowman.com has no SPF policy when checking 2607:f8b0:4864:20::430) smtp.mailfrom=crb@chrisbowman.com; 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Tue, 05 Sep 2023 22:54:09 -0700 (PDT) From: Christopher Bowman Content-Type: multipart/alternative; boundary="Apple-Mail=_D4C4534F-2853-448D-8EF1-3DBE7CECBBAF" List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3731.500.231\)) Subject: Trouble booting current on ARM Message-Id: <8653BBBD-9EE5-4B53-ADB7-2BE5577BD819@chrisbowman.com> Date: Tue, 5 Sep 2023 22:53:58 -0700 To: hackers@freebsd.org X-Mailer: Apple Mail (2.3731.500.231) X-Spamd-Bar: -- X-Spamd-Result: default: False [-2.30 / 15.00]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-1.000]; MV_CASE(0.50)[]; SUBJECT_ENDS_SPACES(0.50)[]; R_DKIM_ALLOW(-0.20)[chrisbowman-com.20230601.gappssmtp.com:s=20230601]; MIME_GOOD(-0.10)[multipart/alternative,text/plain]; RCVD_IN_DNSWL_NONE(0.00)[2607:f8b0:4864:20::430:from]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:15169, ipnet:2607:f8b0::/32, country:US]; MIME_TRACE(0.00)[0:+,1:+,2:~]; MLMMJ_DEST(0.00)[hackers@freebsd.org]; FROM_EQ_ENVFROM(0.00)[]; R_SPF_NA(0.00)[no SPF record]; RCVD_VIA_SMTP_AUTH(0.00)[]; DMARC_NA(0.00)[chrisbowman.com]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; DKIM_TRACE(0.00)[chrisbowman-com.20230601.gappssmtp.com:+]; TO_MATCH_ENVRCPT_ALL(0.00)[]; PREVIOUSLY_DELIVERED(0.00)[hackers@freebsd.org]; TO_DN_NONE(0.00)[]; RCPT_COUNT_ONE(0.00)[1]; MID_RHS_MATCH_FROM(0.00)[] X-Rspamd-Queue-Id: 4RgWln5vLVz4JFn --Apple-Mail=_D4C4534F-2853-448D-8EF1-3DBE7CECBBAF Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 Apologies if this is a duplicate but I didn=E2=80=99t see this come out = on the list: I=E2=80=99ve been using an Arty-Z7 from Diligent for several years now. = This is a AMD/Xilinx ZYNQ based board. It=E2=80=99s mostly similar to a = ZED board which has an in tree kernel config. It has worked fine with = 13.0. I=E2=80=99m now looking to mowe my work forward and keep pace = with the project. I=E2=80=99d like to eventually upgrade to 14.0 when = it comes out. In preparation I built a new release using sources from = after the 14.0 branch. I=E2=80=99m able to cross build fine but when I = boot the kernel I see the crash below, Has anyone seen panic: Storing = an invalid VFP state. Any information or ideas about what might be = happening before I try to debug? Any information at all would be = helpful. Is anyone else running a Zynq based board of any kind with a recent 14.0 = or current kernel? Thanks for any help, Christopher GDB: debug ports: uart GDB: current port: uart KDB: debugger backends: ddb gdb KDB: current backend: ddb Copyright (c) 1992-2023 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights = reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 15.0-CURRENT armv7 1500000 #3 main-n265107-03d104888cae: Fri Sep = 1 20:18:55 PDT 2023 crb@eclipse.ChrisBowman.com = :/usr/obj/tmp/src/arm.armv7/sys/ARTYZ7= arm FreeBSD clang version 16.0.6 (https://github.com/llvm/llvm-project.git = llvmorg-16.0.6-0-g7cbf1a259152) WARNING: WITNESS option enabled, expect reduced performance. WARNING: 32-bit kernels are deprecated and may be removed in FreeBSD = 15.0. CPU: ARM Cortex-A9 r3p0 (ECO: 0x00000000) CPU Features:=20 Multiprocessing, Thumb2, Security, VMSAv7, Coherent Walk Optional instructions:=20 UMULL, SMULL, SIMD(ext) LoUU:2 LoC:2 LoUIS:2=20 Cache level 1: 32KB/32B 4-way data cache WB Read-Alloc Write-Alloc 32KB/32B 4-way instruction cache Read-Alloc real memory =3D 536866816 (511 MB) avail memory =3D 511369216 (487 MB) FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs arc4random: WARNING: initial seeding bypassed the cryptographic random = device because it was not yet seeded and the knob = 'bypass_before_seeding' was enabled. random: entropy device external interface ofwbus0: regfix0: on ofwbus0 simplebus0: on ofwbus0 simple_mfd0: mem = 0xf8000000-0xf8000fff on simplebus0 l2cache0: mem 0xf8f02000-0xf8f02fff irq 8 on = simplebus0 l2cache0: cannot allocate IRQ, not using interrupt l2cache0: Part number: 0x3, release: 0x8 l2cache0: L2 Cache enabled: 512KB/32B 8 ways gic0: mem = 0xf8f01000-0xf8f01fff,0xf8f00100-0xf8f001ff on simplebus0 gic0: pn 0x39, arch 0x1, rev 0x2, implementer 0x43b irqs 96 mp_tmr0: mem 0xf8f00200-0xf8f0021f irq 29 on = simplebus0 Timecounter "MPCore" frequency 50000000 Hz quality 800 mp_tmr1: mem 0xf8f00600-0xf8f0061f irq 36 on = simplebus0 Event timer "MPCore" frequency 50000000 Hz quality 1000 cpulist0: on ofwbus0 cpu0: on cpulist0 uart0: mem 0xe0000000-0xe0000fff irq 9 on simplebus0 uart0: console (-1,n,8,1) zy7_qspi0: mem 0xe000d000-0xe000dfff = irq 13 on simplebus0 zy7_qspi0: must have ref-clock property device_attach: zy7_qspi0 attach returned 6 cgem0: mem = 0xe000b000-0xe000bfff irq 14 on simplebus0 cgem0: could not retrieve reference clock. miibus0: on cgem0 rgephy0: PHY 0 on = miibus0 rgephy0: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, = 1000baseT-FDX, 1000baseT-FDX-master, auto rgephy1: PHY 1 on = miibus0 rgephy1: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, = 1000baseT-FDX, 1000baseT-FDX-master, auto cgem0: Ethernet address: 66:da:ac:ca:9e:86 sdhci_fdt0: mem = 0xe0100000-0xe0100fff irq 17 on simplebus0 sdhci_fdt0: 1 slot(s) allocated mmc0: on sdhci_fdt0 zy7_devcfg0: mem 0xf8007000-0xf80070ff irq 28 on = simplebus0 Timecounters tick every 1.000 msec usb_needs_explore_all: no devclass panic: Storing an invalid VFP state cpuid =3D 0 time =3D 1 KDB: stack backtrace: db_trace_self() at db_trace_self pc =3D 0xc04fcbf8 lr =3D 0xc0071424 = (db_trace_self_wrapper+0x30) sp =3D 0xc0a14930 fp =3D 0xc0a14a48 db_trace_self_wrapper() at db_trace_self_wrapper+0x30 pc =3D 0xc0071424 lr =3D 0xc02039cc (vpanic+0x140) sp =3D 0xc0a14a50 fp =3D 0xc0a14a70 r4 =3D 0x00000100 r5 =3D 0x00000000 r6 =3D 0xc05b70fb r7 =3D 0xc072f7a8 vpanic() at vpanic+0x140 pc =3D 0xc02039cc lr =3D 0xc02037ac (doadump) sp =3D 0xc0a14a78 fp =3D 0xc0a14a7c r4 =3D 0x2009e010 r5 =3D 0xcfc96000 r6 =3D 0xc06f6da9 r7 =3D 0xcf0cce90 r8 =3D 0xc07a2800 r9 =3D 0xc07408c4 r10 =3D 0xc071f1e0 doadump() at doadump pc =3D 0xc02037ac lr =3D 0xc0520eb0 (fpu_kern_enter) sp =3D 0xc0a14a84 fp =3D 0xc0a14a90 r4 =3D 0xc071f1e0 r5 =3D 0xc0a14a7c r6 =3D 0xc02037ac r10 =3D 0xc0a14a84 fpu_kern_enter() at fpu_kern_enter pc =3D 0xc0520eb0 lr =3D 0xc051e0c8 (cpu_switch+0x5c) sp =3D 0xc0a14a98 fp =3D 0xcfc96000 r4 =3D 0xc0520eb0 r5 =3D 0xc0a14e90 r6 =3D 0x00000000 r10 =3D 0xc07a2800 cpu_switch() at cpu_switch+0x5c pc =3D 0xc051e0c8 lr =3D 0xc051e0c8 (cpu_switch+0x5c) sp =3D 0xc0a14a98 fp =3D 0xcfc96000 Unwind failure (no registers changed) KDB: enter: panic [ thread pid 0 tid 100000 ] Stopped at kdb_enter+0x54: ldrb r15, [r15, r15, ror r15]! db>=20= --Apple-Mail=_D4C4534F-2853-448D-8EF1-3DBE7CECBBAF Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8 Apologies if = this is a duplicate but I didn=E2=80=99t see this come out on the = list:

I=E2=80=99ve been using an Arty-Z7 from = Diligent for several years now.  This is a AMD/Xilinx ZYNQ based = board.  It=E2=80=99s mostly similar to a ZED board which has an in = tree kernel config.  It has worked fine with 13.0.  I=E2=80=99m = now looking to mowe my work forward and keep pace with the project. =  I=E2=80=99d like to eventually upgrade to 14.0 when it comes out. =  In preparation I built a new release using sources from after the = 14.0 branch.  I=E2=80=99m able to cross build fine but when I boot = the kernel I see the crash below,  Has anyone seen panic: Storing an invalid VFP state. =  Any information or ideas about what might be happening before I = try to debug?  Any information at all would be = helpful.

Is anyone else running a Zynq based board of = any kind with a recent 14.0 or current kernel?
Thanks for any = help,
Christopher



GDB: debug = ports: uart

GDB: current = port: uart

KDB: debugger = backends: ddb gdb

KDB: current = backend: ddb

Copyright (c) = 1992-2023 The FreeBSD Project.

Copyright (c) = 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994

The = Regents of the University of California. All rights reserved.

FreeBSD is a = registered trademark of The FreeBSD Foundation.

FreeBSD 15.0-CURRENT armv7 1500000 #3 = main-n265107-03d104888cae: Fri Sep  1 20:18:55 PDT 2023

  =   crb@eclipse.ChrisBowman.com:/usr/obj/tmp/src/arm.armv7/sys/ARTYZ7 arm

FreeBSD clang version 16.0.6 (https://github.com/llvm/= llvm-project.git llvmorg-16.0.6-0-g7cbf1a259152)

WARNING: = WITNESS option enabled, expect reduced performance.

WARNING: 32-bit kernels are deprecated and may be = removed in FreeBSD 15.0.

CPU: ARM = Cortex-A9 r3p0 (ECO: 0x00000000)

CPU Features: 

  Multiprocessing, Thumb2, Security, VMSAv7, = Coherent Walk

Optional = instructions: 

  UMULL, = SMULL, SIMD(ext)

LoUU:2 LoC:2 = LoUIS:2 

Cache level = 1:

 32KB/32B = 4-way data cache WB Read-Alloc Write-Alloc

 32KB/32B 4-way instruction cache Read-Alloc

real = memory  =3D 536866816 (511 MB)

avail memory =3D 511369216 (487 MB)

FreeBSD/SMP: = Multiprocessor System Detected: 2 CPUs

arc4random: WARNING: initial seeding bypassed the = cryptographic random device because it was not yet seeded and the knob = 'bypass_before_seeding' was enabled.

random: entropy device external interface

ofwbus0: = <Open Firmware Device Tree>

regfix0: <Fixed Regulator> on ofwbus0

simplebus0: = <Flattened device tree simple bus> on ofwbus0

simple_mfd0: <Simple MFD (Multi-Functions = Device)> mem 0xf8000000-0xf8000fff on simplebus0

l2cache0: <PL310 L2 cache controller> mem = 0xf8f02000-0xf8f02fff irq 8 on simplebus0

l2cache0: cannot allocate IRQ, not using = interrupt

l2cache0: Part = number: 0x3, release: 0x8

l2cache0: L2 = Cache enabled: 512KB/32B 8 ways

gic0: <ARM Generic Interrupt Controller> mem = 0xf8f01000-0xf8f01fff,0xf8f00100-0xf8f001ff on simplebus0

gic0: pn 0x39, = arch 0x1, rev 0x2, implementer 0x43b irqs 96

mp_tmr0: <ARM MPCore Timers> mem = 0xf8f00200-0xf8f0021f irq 29 on simplebus0

Timecounter "MPCore" frequency 50000000 Hz quality = 800

mp_tmr1: = <ARM MPCore Timers> mem 0xf8f00600-0xf8f0061f irq 36 on = simplebus0

Event timer = "MPCore" frequency 50000000 Hz quality 1000

cpulist0: <Open Firmware CPU Group> on = ofwbus0

cpu0: <Open = Firmware CPU> on cpulist0

uart0: = <Cadence UART> mem 0xe0000000-0xe0000fff irq 9 on simplebus0

uart0: console = (-1,n,8,1)

zy7_qspi0: = <Zynq Quad-SPI Flash Controller> mem 0xe000d000-0xe000dfff irq 13 = on simplebus0

zy7_qspi0: must = have ref-clock property

device_attach: = zy7_qspi0 attach returned 6

cgem0: = <Cadence CGEM Gigabit Ethernet Interface> mem = 0xe000b000-0xe000bfff irq 14 on simplebus0

cgem0: could not retrieve reference clock.

miibus0: = <MII bus> on cgem0

rgephy0: = <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 0 on = miibus0

rgephy0:  = none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, = 1000baseT-FDX-master, auto

rgephy1: = <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 1 on = miibus0

rgephy1:  = none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, = 1000baseT-FDX-master, auto

cgem0: Ethernet = address: 66:da:ac:ca:9e:86

sdhci_fdt0: = <Zynq-7000 generic fdt SDHCI controller> mem 0xe0100000-0xe0100fff = irq 17 on simplebus0

sdhci_fdt0: 1 = slot(s) allocated

mmc0: = <MMC/SD bus> on sdhci_fdt0

zy7_devcfg0: <Zynq devcfg block> mem = 0xf8007000-0xf80070ff irq 28 on simplebus0

Timecounters tick every 1.000 msec

usb_needs_explore_all: no devclass

panic: Storing an invalid VFP state

cpuid =3D = 0

time =3D = 1

KDB: stack = backtrace:

db_trace_self() = at db_trace_self

 pc = =3D 0xc04fcbf8  lr =3D 0xc0071424 = (db_trace_self_wrapper+0x30)

 sp = =3D 0xc0a14930  fp =3D 0xc0a14a48

db_trace_self_wrapper() at = db_trace_self_wrapper+0x30

 pc = =3D 0xc0071424  lr =3D 0xc02039cc (vpanic+0x140)

 sp = =3D 0xc0a14a50  fp =3D 0xc0a14a70

 r4 =3D 0x00000100  r5 =3D 0x00000000

 r6 = =3D 0xc05b70fb  r7 =3D 0xc072f7a8

vpanic() at vpanic+0x140

 pc =3D 0xc02039cc  lr =3D 0xc02037ac = (doadump)

 sp = =3D 0xc0a14a78  fp =3D 0xc0a14a7c

 r4 =3D 0x2009e010  r5 =3D 0xcfc96000

 r6 = =3D 0xc06f6da9  r7 =3D 0xcf0cce90

 r8 =3D 0xc07a2800  r9 =3D 0xc07408c4

r10 =3D = 0xc071f1e0

doadump() at = doadump

 pc = =3D 0xc02037ac  lr =3D 0xc0520eb0 (fpu_kern_enter)

 sp = =3D 0xc0a14a84  fp =3D 0xc0a14a90

 r4 =3D 0xc071f1e0  r5 =3D 0xc0a14a7c

 r6 = =3D 0xc02037ac r10 =3D 0xc0a14a84

fpu_kern_enter() at fpu_kern_enter

 pc =3D 0xc0520eb0  lr =3D 0xc051e0c8 = (cpu_switch+0x5c)

 sp = =3D 0xc0a14a98  fp =3D 0xcfc96000

 r4 =3D 0xc0520eb0  r5 =3D 0xc0a14e90

 r6 = =3D 0x00000000 r10 =3D 0xc07a2800

cpu_switch() at cpu_switch+0x5c

 pc =3D 0xc051e0c8  lr =3D 0xc051e0c8 = (cpu_switch+0x5c)

 sp = =3D 0xc0a14a98  fp =3D 0xcfc96000

Unwind failure (no registers changed)

KDB: enter: = panic

[ thread pid 0 = tid 100000 ]

Stopped = at      kdb_enter+0x54: ldrb    r15, [r15, r15, = ror r15]!

db> 

= --Apple-Mail=_D4C4534F-2853-448D-8EF1-3DBE7CECBBAF-- From nobody Wed Sep 6 05:55:36 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RgWnf0C38z4ssP7 for ; Wed, 6 Sep 2023 05:55:50 +0000 (UTC) (envelope-from crb@chrisbowman.com) Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RgWnd0q2cz4KVQ for ; Wed, 6 Sep 2023 05:55:49 +0000 (UTC) (envelope-from crb@chrisbowman.com) Authentication-Results: mx1.freebsd.org; dkim=pass header.d=chrisbowman-com.20230601.gappssmtp.com header.s=20230601 header.b=Xs2utrVJ; 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Tue, 05 Sep 2023 22:55:46 -0700 (PDT) From: Christopher Bowman Content-Type: multipart/alternative; boundary="Apple-Mail=_46CCF1F6-FBA3-4145-B153-798AEDE55049" List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3731.500.231\)) Subject: Trouble booting current on AMD/Xilinx Zynq ARM based board Message-Id: <383D43E7-7BCB-452F-B8D6-7A65153FD2AD@chrisbowman.com> Date: Tue, 5 Sep 2023 22:55:36 -0700 To: freebsd-hackers@freebsd.org X-Mailer: Apple Mail (2.3731.500.231) X-Spamd-Bar: -- X-Spamd-Result: default: False [-2.80 / 15.00]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-1.000]; MV_CASE(0.50)[]; R_DKIM_ALLOW(-0.20)[chrisbowman-com.20230601.gappssmtp.com:s=20230601]; MIME_GOOD(-0.10)[multipart/alternative,text/plain]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org]; RCVD_IN_DNSWL_NONE(0.00)[2607:f8b0:4864:20::42b:from]; R_SPF_NA(0.00)[no SPF record]; MIME_TRACE(0.00)[0:+,1:+,2:~]; RCVD_TLS_LAST(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; ASN(0.00)[asn:15169, ipnet:2607:f8b0::/32, country:US]; DKIM_TRACE(0.00)[chrisbowman-com.20230601.gappssmtp.com:+]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; DMARC_NA(0.00)[chrisbowman.com]; TO_MATCH_ENVRCPT_ALL(0.00)[]; TO_DN_NONE(0.00)[]; PREVIOUSLY_DELIVERED(0.00)[freebsd-hackers@freebsd.org]; RCPT_COUNT_ONE(0.00)[1]; MID_RHS_MATCH_FROM(0.00)[] X-Rspamd-Queue-Id: 4RgWnd0q2cz4KVQ --Apple-Mail=_46CCF1F6-FBA3-4145-B153-798AEDE55049 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 I=E2=80=99ve been using an Arty-Z7 from Diligent for several years now. = This is a AMD/Xilinx ZYNQ based board. It=E2=80=99s mostly similar to a = ZED board which has an in tree kernel config. It has worked fine with = 13.0. I=E2=80=99m now looking to mowe my work forward and keep pace = with the project. I=E2=80=99d like to eventually upgrade to 14.0 when = it comes out. In preparation I built a new release using sources from = after the 14.0 branch. I=E2=80=99m able to cross build fine but when I = boot the kernel I see the crash below, Has anyone seen panic: Storing = an invalid VFP state. Any information or ideas about what might be = happening before I try to debug? Any information at all would be = helpful. Is anyone else running a Zynq based board of any kind with a recent 14.0 = or current kernel? Thanks for any help, Christopher GDB: debug ports: uart GDB: current port: uart KDB: debugger backends: ddb gdb KDB: current backend: ddb Copyright (c) 1992-2023 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights = reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 15.0-CURRENT armv7 1500000 #3 main-n265107-03d104888cae: Fri Sep = 1 20:18:55 PDT 2023 crb@eclipse.ChrisBowman.com = :/usr/obj/tmp/src/arm.armv7/sys/ARTYZ7= arm FreeBSD clang version 16.0.6 (https://github.com/llvm/llvm-project.git = llvmorg-16.0.6-0-g7cbf1a259152) WARNING: WITNESS option enabled, expect reduced performance. WARNING: 32-bit kernels are deprecated and may be removed in FreeBSD = 15.0. CPU: ARM Cortex-A9 r3p0 (ECO: 0x00000000) CPU Features:=20 Multiprocessing, Thumb2, Security, VMSAv7, Coherent Walk Optional instructions:=20 UMULL, SMULL, SIMD(ext) LoUU:2 LoC:2 LoUIS:2=20 Cache level 1: 32KB/32B 4-way data cache WB Read-Alloc Write-Alloc 32KB/32B 4-way instruction cache Read-Alloc real memory =3D 536866816 (511 MB) avail memory =3D 511369216 (487 MB) FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs arc4random: WARNING: initial seeding bypassed the cryptographic random = device because it was not yet seeded and the knob = 'bypass_before_seeding' was enabled. random: entropy device external interface ofwbus0: regfix0: on ofwbus0 simplebus0: on ofwbus0 simple_mfd0: mem = 0xf8000000-0xf8000fff on simplebus0 l2cache0: mem 0xf8f02000-0xf8f02fff irq 8 on = simplebus0 l2cache0: cannot allocate IRQ, not using interrupt l2cache0: Part number: 0x3, release: 0x8 l2cache0: L2 Cache enabled: 512KB/32B 8 ways gic0: mem = 0xf8f01000-0xf8f01fff,0xf8f00100-0xf8f001ff on simplebus0 gic0: pn 0x39, arch 0x1, rev 0x2, implementer 0x43b irqs 96 mp_tmr0: mem 0xf8f00200-0xf8f0021f irq 29 on = simplebus0 Timecounter "MPCore" frequency 50000000 Hz quality 800 mp_tmr1: mem 0xf8f00600-0xf8f0061f irq 36 on = simplebus0 Event timer "MPCore" frequency 50000000 Hz quality 1000 cpulist0: on ofwbus0 cpu0: on cpulist0 uart0: mem 0xe0000000-0xe0000fff irq 9 on simplebus0 uart0: console (-1,n,8,1) zy7_qspi0: mem 0xe000d000-0xe000dfff = irq 13 on simplebus0 zy7_qspi0: must have ref-clock property device_attach: zy7_qspi0 attach returned 6 cgem0: mem = 0xe000b000-0xe000bfff irq 14 on simplebus0 cgem0: could not retrieve reference clock. miibus0: on cgem0 rgephy0: PHY 0 on = miibus0 rgephy0: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, = 1000baseT-FDX, 1000baseT-FDX-master, auto rgephy1: PHY 1 on = miibus0 rgephy1: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, = 1000baseT-FDX, 1000baseT-FDX-master, auto cgem0: Ethernet address: 66:da:ac:ca:9e:86 sdhci_fdt0: mem = 0xe0100000-0xe0100fff irq 17 on simplebus0 sdhci_fdt0: 1 slot(s) allocated mmc0: on sdhci_fdt0 zy7_devcfg0: mem 0xf8007000-0xf80070ff irq 28 on = simplebus0 Timecounters tick every 1.000 msec usb_needs_explore_all: no devclass panic: Storing an invalid VFP state cpuid =3D 0 time =3D 1 KDB: stack backtrace: db_trace_self() at db_trace_self pc =3D 0xc04fcbf8 lr =3D 0xc0071424 = (db_trace_self_wrapper+0x30) sp =3D 0xc0a14930 fp =3D 0xc0a14a48 db_trace_self_wrapper() at db_trace_self_wrapper+0x30 pc =3D 0xc0071424 lr =3D 0xc02039cc (vpanic+0x140) sp =3D 0xc0a14a50 fp =3D 0xc0a14a70 r4 =3D 0x00000100 r5 =3D 0x00000000 r6 =3D 0xc05b70fb r7 =3D 0xc072f7a8 vpanic() at vpanic+0x140 pc =3D 0xc02039cc lr =3D 0xc02037ac (doadump) sp =3D 0xc0a14a78 fp =3D 0xc0a14a7c r4 =3D 0x2009e010 r5 =3D 0xcfc96000 r6 =3D 0xc06f6da9 r7 =3D 0xcf0cce90 r8 =3D 0xc07a2800 r9 =3D 0xc07408c4 r10 =3D 0xc071f1e0 doadump() at doadump pc =3D 0xc02037ac lr =3D 0xc0520eb0 (fpu_kern_enter) sp =3D 0xc0a14a84 fp =3D 0xc0a14a90 r4 =3D 0xc071f1e0 r5 =3D 0xc0a14a7c r6 =3D 0xc02037ac r10 =3D 0xc0a14a84 fpu_kern_enter() at fpu_kern_enter pc =3D 0xc0520eb0 lr =3D 0xc051e0c8 (cpu_switch+0x5c) sp =3D 0xc0a14a98 fp =3D 0xcfc96000 r4 =3D 0xc0520eb0 r5 =3D 0xc0a14e90 r6 =3D 0x00000000 r10 =3D 0xc07a2800 cpu_switch() at cpu_switch+0x5c pc =3D 0xc051e0c8 lr =3D 0xc051e0c8 (cpu_switch+0x5c) sp =3D 0xc0a14a98 fp =3D 0xcfc96000 Unwind failure (no registers changed) KDB: enter: panic [ thread pid 0 tid 100000 ] Stopped at kdb_enter+0x54: ldrb r15, [r15, r15, ror r15]! db>=20= --Apple-Mail=_46CCF1F6-FBA3-4145-B153-798AEDE55049 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8 I=E2=80=99ve = been using an Arty-Z7 from Diligent for several years now.  This is = a AMD/Xilinx ZYNQ based board.  It=E2=80=99s mostly similar to a = ZED board which has an in tree kernel config.  It has worked fine = with 13.0.  I=E2=80=99m now looking to mowe my work forward and = keep pace with the project.  I=E2=80=99d like to eventually upgrade = to 14.0 when it comes out.  In preparation I built a new release = using sources from after the 14.0 branch.  I=E2=80=99m able to = cross build fine but when I boot the kernel I see the crash below, =  Has anyone seen panic: Storing an invalid = VFP state.  Any information or ideas about what might be happening = before I try to debug?  Any information at all would be = helpful.

Is anyone else running a Zynq based board of = any kind with a recent 14.0 or current kernel?
Thanks for any = help,
Christopher



GDB: debug = ports: uart

GDB: current = port: uart

KDB: debugger = backends: ddb gdb

KDB: current = backend: ddb

Copyright (c) = 1992-2023 The FreeBSD Project.

Copyright (c) = 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994

The = Regents of the University of California. All rights reserved.

FreeBSD is a = registered trademark of The FreeBSD Foundation.

FreeBSD 15.0-CURRENT armv7 1500000 #3 = main-n265107-03d104888cae: Fri Sep  1 20:18:55 PDT 2023

  =   crb@eclipse.ChrisBowman.com:/usr/obj/tmp/src/arm.armv7/sys/ARTYZ7 arm

FreeBSD clang version 16.0.6 (https://github.com/llvm/= llvm-project.git llvmorg-16.0.6-0-g7cbf1a259152)

WARNING: = WITNESS option enabled, expect reduced performance.

WARNING: 32-bit kernels are deprecated and may be = removed in FreeBSD 15.0.

CPU: ARM = Cortex-A9 r3p0 (ECO: 0x00000000)

CPU Features: 

  Multiprocessing, Thumb2, Security, VMSAv7, = Coherent Walk

Optional = instructions: 

  UMULL, = SMULL, SIMD(ext)

LoUU:2 LoC:2 = LoUIS:2 

Cache level = 1:

 32KB/32B = 4-way data cache WB Read-Alloc Write-Alloc

 32KB/32B 4-way instruction cache Read-Alloc

real = memory  =3D 536866816 (511 MB)

avail memory =3D 511369216 (487 MB)

FreeBSD/SMP: = Multiprocessor System Detected: 2 CPUs

arc4random: WARNING: initial seeding bypassed the = cryptographic random device because it was not yet seeded and the knob = 'bypass_before_seeding' was enabled.

random: entropy device external interface

ofwbus0: = <Open Firmware Device Tree>

regfix0: <Fixed Regulator> on ofwbus0

simplebus0: = <Flattened device tree simple bus> on ofwbus0

simple_mfd0: <Simple MFD (Multi-Functions = Device)> mem 0xf8000000-0xf8000fff on simplebus0

l2cache0: <PL310 L2 cache controller> mem = 0xf8f02000-0xf8f02fff irq 8 on simplebus0

l2cache0: cannot allocate IRQ, not using = interrupt

l2cache0: Part = number: 0x3, release: 0x8

l2cache0: L2 = Cache enabled: 512KB/32B 8 ways

gic0: <ARM Generic Interrupt Controller> mem = 0xf8f01000-0xf8f01fff,0xf8f00100-0xf8f001ff on simplebus0

gic0: pn 0x39, = arch 0x1, rev 0x2, implementer 0x43b irqs 96

mp_tmr0: <ARM MPCore Timers> mem = 0xf8f00200-0xf8f0021f irq 29 on simplebus0

Timecounter "MPCore" frequency 50000000 Hz quality = 800

mp_tmr1: = <ARM MPCore Timers> mem 0xf8f00600-0xf8f0061f irq 36 on = simplebus0

Event timer = "MPCore" frequency 50000000 Hz quality 1000

cpulist0: <Open Firmware CPU Group> on = ofwbus0

cpu0: <Open = Firmware CPU> on cpulist0

uart0: = <Cadence UART> mem 0xe0000000-0xe0000fff irq 9 on simplebus0

uart0: console = (-1,n,8,1)

zy7_qspi0: = <Zynq Quad-SPI Flash Controller> mem 0xe000d000-0xe000dfff irq 13 = on simplebus0

zy7_qspi0: must = have ref-clock property

device_attach: = zy7_qspi0 attach returned 6

cgem0: = <Cadence CGEM Gigabit Ethernet Interface> mem = 0xe000b000-0xe000bfff irq 14 on simplebus0

cgem0: could not retrieve reference clock.

miibus0: = <MII bus> on cgem0

rgephy0: = <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 0 on = miibus0

rgephy0:  = none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, = 1000baseT-FDX-master, auto

rgephy1: = <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 1 on = miibus0

rgephy1:  = none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, = 1000baseT-FDX-master, auto

cgem0: Ethernet = address: 66:da:ac:ca:9e:86

sdhci_fdt0: = <Zynq-7000 generic fdt SDHCI controller> mem 0xe0100000-0xe0100fff = irq 17 on simplebus0

sdhci_fdt0: 1 = slot(s) allocated

mmc0: = <MMC/SD bus> on sdhci_fdt0

zy7_devcfg0: <Zynq devcfg block> mem = 0xf8007000-0xf80070ff irq 28 on simplebus0

Timecounters tick every 1.000 msec

usb_needs_explore_all: no devclass

panic: Storing an invalid VFP state

cpuid =3D = 0

time =3D = 1

KDB: stack = backtrace:

db_trace_self() = at db_trace_self

 pc = =3D 0xc04fcbf8  lr =3D 0xc0071424 = (db_trace_self_wrapper+0x30)

 sp = =3D 0xc0a14930  fp =3D 0xc0a14a48

db_trace_self_wrapper() at = db_trace_self_wrapper+0x30

 pc = =3D 0xc0071424  lr =3D 0xc02039cc (vpanic+0x140)

 sp = =3D 0xc0a14a50  fp =3D 0xc0a14a70

 r4 =3D 0x00000100  r5 =3D 0x00000000

 r6 = =3D 0xc05b70fb  r7 =3D 0xc072f7a8

vpanic() at vpanic+0x140

 pc =3D 0xc02039cc  lr =3D 0xc02037ac = (doadump)

 sp = =3D 0xc0a14a78  fp =3D 0xc0a14a7c

 r4 =3D 0x2009e010  r5 =3D 0xcfc96000

 r6 = =3D 0xc06f6da9  r7 =3D 0xcf0cce90

 r8 =3D 0xc07a2800  r9 =3D 0xc07408c4

r10 =3D = 0xc071f1e0

doadump() at = doadump

 pc = =3D 0xc02037ac  lr =3D 0xc0520eb0 (fpu_kern_enter)

 sp = =3D 0xc0a14a84  fp =3D 0xc0a14a90

 r4 =3D 0xc071f1e0  r5 =3D 0xc0a14a7c

 r6 = =3D 0xc02037ac r10 =3D 0xc0a14a84

fpu_kern_enter() at fpu_kern_enter

 pc =3D 0xc0520eb0  lr =3D 0xc051e0c8 = (cpu_switch+0x5c)

 sp = =3D 0xc0a14a98  fp =3D 0xcfc96000

 r4 =3D 0xc0520eb0  r5 =3D 0xc0a14e90

 r6 = =3D 0x00000000 r10 =3D 0xc07a2800

cpu_switch() at cpu_switch+0x5c

 pc =3D 0xc051e0c8  lr =3D 0xc051e0c8 = (cpu_switch+0x5c)

 sp = =3D 0xc0a14a98  fp =3D 0xcfc96000

Unwind failure (no registers changed)

KDB: enter: = panic

[ thread pid 0 = tid 100000 ]

Stopped = at      kdb_enter+0x54: ldrb    r15, [r15, r15, = ror r15]!

db> 

= --Apple-Mail=_46CCF1F6-FBA3-4145-B153-798AEDE55049-- From nobody Wed Sep 6 10:48:04 2023 X-Original-To: hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RgfHR1Jp5z4s0WW for ; Wed, 6 Sep 2023 10:48:35 +0000 (UTC) (envelope-from darius@dons.net.au) Received: from midget.dons.net.au (midget.dons.net.au [IPv6:2403:580d:bc41:0:225:90ff:fe47:39b4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature ECDSA (P-384) client-digest SHA384) (Client CN "dons.net.au", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RgfHP6ctsz4KBT for ; Wed, 6 Sep 2023 10:48:33 +0000 (UTC) (envelope-from darius@dons.net.au) Authentication-Results: mx1.freebsd.org; none Received: from smtpclient.apple ([IPv6:2403:580d:bc41:0:4dc5:1570:2f8a:930a]) (authenticated bits=0) by midget.dons.net.au (8.17.2/8.17.1) with ESMTPSA id 386AmERd018963 (version=TLSv1.2 cipher=ECDHE-ECDSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 6 Sep 2023 20:18:14 +0930 (ACST) (envelope-from darius@dons.net.au) X-Authentication-Warning: midget.dons.net.au: Host [IPv6:2403:580d:bc41:0:4dc5:1570:2f8a:930a] claimed to be smtpclient.apple Content-Type: text/plain; charset=utf-8 List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3731.700.6\)) Subject: Re: Trouble booting current on ARM From: "Daniel O'Connor" In-Reply-To: <8653BBBD-9EE5-4B53-ADB7-2BE5577BD819@chrisbowman.com> Date: Wed, 6 Sep 2023 20:18:04 +0930 Cc: hackers@freebsd.org Content-Transfer-Encoding: quoted-printable Message-Id: References: <8653BBBD-9EE5-4B53-ADB7-2BE5577BD819@chrisbowman.com> To: Christopher Bowman X-Mailer: Apple Mail (2.3731.700.6) X-Spam-Status: No, score=0.40 X-Rspamd-Server: midget.dons.net.au X-Spamd-Bar: ---- X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:4764, ipnet:2403:5800::/27, country:AU] X-Rspamd-Queue-Id: 4RgfHP6ctsz4KBT Hi Christopherm,, > On 6 Sep 2023, at 15:23, Christopher Bowman = wrote: >=20 > Apologies if this is a duplicate but I didn=E2=80=99t see this come = out on the list: >=20 > I=E2=80=99ve been using an Arty-Z7 from Diligent for several years = now. This is a AMD/Xilinx ZYNQ based board. It=E2=80=99s mostly = similar to a ZED board which has an in tree kernel config. It has = worked fine with 13.0. I=E2=80=99m now looking to mowe my work forward = and keep pace with the project. I=E2=80=99d like to eventually upgrade = to 14.0 when it comes out. In preparation I built a new release using = sources from after the 14.0 branch. I=E2=80=99m able to cross build = fine but when I boot the kernel I see the crash below, Has anyone seen = panic: Storing an invalid VFP state. Any information or ideas about = what might be happening before I try to debug? Any information at all = would be helpful. >=20 > Is anyone else running a Zynq based board of any kind with a recent = 14.0 or current kernel? I don't have any experience as yet but I do have a Zynq board I am = playing around with so your experience is interesting :) > panic: Storing an invalid VFP state Regarding the panic - it is only checked when INVARIANTS is on, so if = you previously had been using stable it would not be on by default. ie the problem may have always been present but masked. I would try #if'ing out the KASSERT in sys/arm64/arm64/vfp.c around line = 190 and see what else breaks. -- Daniel O'Connor "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum From nobody Wed Sep 6 11:36:18 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RggMX0Qd3z4sRqM for ; Wed, 6 Sep 2023 11:37:12 +0000 (UTC) (envelope-from c@bow.st) Received: from comms.drone (in.bow.st [71.19.146.166]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4RggMV3BQjz4XYW; Wed, 6 Sep 2023 11:37:10 +0000 (UTC) (envelope-from c@bow.st) Authentication-Results: mx1.freebsd.org; dkim=none; spf=pass (mx1.freebsd.org: domain of c@bow.st designates 71.19.146.166 as permitted sender) smtp.mailfrom=c@bow.st; dmarc=none Received: from homebase (unknown [IPv6:fe80::ff1d:976a:a7e4:ee6a]) by comms.drone (Postfix) with ESMTPSA id B1735FCDC; Wed, 6 Sep 2023 11:36:53 +0000 (UTC) From: "Mathew\, Cherry G.*" To: Alexander Leidinger Cc: adridg@freebsd.org, freebsd-hackers@freebsd.org Subject: Re: ARC model specified in spinroot/promela References: <85jzt96qjz.fsf@bow.st> <9c424a574cdd39fc879c9ed9192556c0@Leidinger.net> <858r9o6ee0.fsf@bow.st> <85pm304dzi.fsf@bow.st> <85a5u22oxx.fsf@bow.st> <1e3a17e39094a9630eebce9f91f00e30@Leidinger.net> Date: Wed, 06 Sep 2023 11:36:18 +0000 In-Reply-To: <1e3a17e39094a9630eebce9f91f00e30@Leidinger.net> (Alexander Leidinger's message of "Mon, 04 Sep 2023 21:47:27 +0200") Message-ID: <85bkefh6tp.fsf@bow.st> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (berkeley-unix) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain X-Spamd-Bar: / X-Spamd-Result: default: False [-0.19 / 15.00]; HFILTER_HELO_IP_A(1.00)[comms.drone]; NEURAL_HAM_LONG(-0.99)[-0.993]; NEURAL_HAM_SHORT(-0.97)[-0.974]; NEURAL_SPAM_MEDIUM(0.68)[0.681]; HFILTER_HELO_NORES_A_OR_MX(0.30)[comms.drone]; R_SPF_ALLOW(-0.20)[+mx]; MIME_GOOD(-0.10)[text/plain]; ONCE_RECEIVED(0.10)[]; TO_DN_SOME(0.00)[]; R_DKIM_NA(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; RCVD_TLS_ALL(0.00)[]; ASN(0.00)[asn:47066, ipnet:71.19.146.0/24, country:US]; FROM_HAS_DN(0.00)[]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org]; ARC_NA(0.00)[]; RCPT_COUNT_THREE(0.00)[3]; RCVD_COUNT_ONE(0.00)[1]; DMARC_NA(0.00)[bow.st]; TO_MATCH_ENVRCPT_SOME(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 4RggMV3BQjz4XYW [...] > spinmodel.pml:80, state 28, "D_STEP80" > spinmodel.pml:80, state 53, "D_STEP80" > spinmodel.pml:154, state 70, "B1.item_list?_" > spinmodel.pml:80, state 79, "D_STEP80" > spinmodel.pml:90, state 85, "D_STEP90" > spinmodel.pml:78, state 86, >(((len(T1.item_list)!=0)&&((len(T1.item_list)>p)||(B2.item_list??[eval(x[x_iid].iid)]&&(len(T1.item_list)==p)))))" > spinmodel.pml:78, state 86, "else" > spinmodel.pml:73, state 88, "D_STEP73" > spinmodel.pml:159, state 90, "assert((len(B1.item_list)==0))" > spinmodel.pml:160, state 94, "D_STEP160" > spinmodel.pml:152, state 95, "((len(T1.item_list)<64))" > spinmodel.pml:152, state 95, "else" > spinmodel.pml:183, state 100, "B2.item_list?_" > spinmodel.pml:198, state 128, "(1)" > spinmodel.pml:268, state 155, "-end-" > (13 of 155 states) [...] These correspond to "Case A" in arc.pml, which were never entered because the driver file wasn't able to create the right sequence to exercise those code paths. I'll look at this later - as this is an illustrative project, it may even make sense to just find an input "trace" as an input array that is guaranteed to make the state machine enter all paths. Thanks for the confirmation trace! -- ~cherry From nobody Wed Sep 6 11:58:49 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RggsH3wxjz4sd5b for ; Wed, 6 Sep 2023 11:59:31 +0000 (UTC) (envelope-from c@bow.st) Received: from comms.drone (in.bow.st [71.19.146.166]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4RggsF1DfCz4dh5; Wed, 6 Sep 2023 11:59:29 +0000 (UTC) (envelope-from c@bow.st) Authentication-Results: mx1.freebsd.org; dkim=none; spf=pass (mx1.freebsd.org: domain of c@bow.st designates 71.19.146.166 as permitted sender) smtp.mailfrom=c@bow.st; dmarc=none Received: from homebase (unknown [IPv6:fe80::ff1d:976a:a7e4:ee6a]) by comms.drone (Postfix) with ESMTPSA id 99F75FCDC; Wed, 6 Sep 2023 11:59:24 +0000 (UTC) From: "Mathew\, Cherry G.*" To: "Mathew\, Cherry G.*" Cc: Alexander Leidinger , adridg@freebsd.org, freebsd-hackers@freebsd.org Subject: Re: ARC model specified in spinroot/promela References: <85jzt96qjz.fsf@bow.st> <9c424a574cdd39fc879c9ed9192556c0@Leidinger.net> <858r9o6ee0.fsf@bow.st> <85pm304dzi.fsf@bow.st> <85a5u22oxx.fsf@bow.st> Date: Wed, 06 Sep 2023 11:58:49 +0000 In-Reply-To: <85a5u22oxx.fsf@bow.st> (Cherry G. Mathew's message of "Mon, 04 Sep 2023 10:49:30 +0000") Message-ID: <85y1hjecna.fsf@bow.st> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (berkeley-unix) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain X-Spamd-Bar: - X-Spamd-Result: default: False [-1.49 / 15.00]; HFILTER_HELO_IP_A(1.00)[comms.drone]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.99)[-0.989]; NEURAL_HAM_MEDIUM(-0.60)[-0.601]; HFILTER_HELO_NORES_A_OR_MX(0.30)[comms.drone]; R_SPF_ALLOW(-0.20)[+mx]; MIME_GOOD(-0.10)[text/plain]; ONCE_RECEIVED(0.10)[]; TO_DN_SOME(0.00)[]; R_DKIM_NA(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; RCVD_TLS_ALL(0.00)[]; ASN(0.00)[asn:47066, ipnet:71.19.146.0/24, country:US]; FROM_HAS_DN(0.00)[]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org]; ARC_NA(0.00)[]; RCPT_COUNT_THREE(0.00)[4]; RCVD_COUNT_ONE(0.00)[1]; DMARC_NA(0.00)[bow.st]; TO_MATCH_ENVRCPT_SOME(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 4RggsF1DfCz4dh5 >>>>> Mathew, Cherry G * writes: [...] > The next step is to write the equivalent C code, compile it with a > simple test "driver" (ideally ATF, but since this is standalone > for the moment, I'll use something simpler, just to illustrate the > concept), and then hook it into spin's "modex" tool, to extract > the implicit model. Once this is done, we'll have a full cycle of design-> implement->verify and this will demonstrate the DDD (Design > Driven Development) methodology I'd love to hear your thoughts > about. I'm attaching below patch (with the usual instructions) to give a sense of direction. At this point, the C code is purely manually crafted. The next step (modex extraction) ties the original model (arc.pml and friends) to the extracted code (arc.c and friends). I am working on that next, and will post later in the week when that's done. Meanwhile, please feel free to comment on this approach at Design Driven Development (D3) if you have any. -- ~cherry diff -urN arc.null/arc.c arc/arc.c --- arc.null/arc.c 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.c 2023-09-06 11:18:57.502125698 +0000 @@ -0,0 +1,173 @@ +/* C Implementation of the Adaptive Replacement Cache algorithm. Written by cherry */ + +/* + * We implement the following algorithm from page 10, Figure 4. + * https://www.usenix.org/legacy/events/fast03/tech/full_papers/megiddo/megiddo.pdf + * + * + * ARC(c) + * + * INPUT: The request stream x1,x2,....,xt,.... + * INITIALIZATION: Set p = 0 and set the LRU lists T1, B1, T2, and B2 to empty. + * + * For every t>=1 and any xt, one and only one of the following four cases must occur. + * Case I: xt is in T1 or T2. A cache hit has occurred in ARC(c) and DBL(2c). + * Move xt to MRU position in T2. + * + * Case II: xt is in B1. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = min { p + d1,c } + * where d1 = { 1 if |B1| >= |B2|, |B2|/|B1| otherwise + * + * REPLACE(xt, p). Move xt from B1 to the MRU position in T2 (also fetch xt to the cache). + * + * Case III: xt is in B2. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = max { p - d2,0 } + * where d2 = { 1 if |B2| >= |B1|, |B1|/|B2| otherwise + * + * REPLACE(xt, p). Move xt from B2 to the MRU position in T2 (also fetch xt to the cache). + * + * Case IV: xt is not in T1 U B1 U T2 U B2. A cache miss has occurred in ARC(c) and DBL(2c). + * Case A: L1 = T1 U B1 has exactly c pages. + * If (|T1| < c) + * Delete LRU page in B1. REPLACE(xt,p). + * else + * Here B1 is empty. Delete LRU page in T1 (also remove it from the cache). + * endif + * Case B: L1 = T1 U B1 has less than c pages. + * If (|T1| + |T2| + |B1| + |B2| >= c) + * Delete LRU page in B2, if (|T1| + |T2| + |B1| + |B2| = 2c). + * REPLACE(xt, p). + * endif + * + * Finally, fetch xt to the cache and move it to MRU position in T1. + * + * Subroutine REPLACE(xt,p) + * If ( (|T1| is not empty) and ((|T1| exceeds the target p) or (xt is in B2 and |T1| = p)) ) + * Delete the LRU page in T1 (also remove it from the cache), and move it to MRU position in B1. + * else + * Delete the LRU page in T2 (also remove it from the cache), and move it to MRU position in B2. + * endif + */ + +#include "arc.h" + +void arc_list_init(struct arc_list *_arc_list) +{ + TAILQ_INIT(&_arc_list->qhead); + _arc_list->qcount = 0; + + for(int i = 0; i < ARCLEN; i++) { + init_arc_item(&_arc_list->item_list[i], IID_INVAL, false); + }; +} + +int p, d1, d2; +struct arc_list _B1, *B1 = &_B1, _B2, *B2 = &_B2, _T1, *T1 = &_T1, _T2, *T2 = &_T2; + +void arc_init(void) +{ + p = d1 = d2 = 0; + + arc_list_init(B1); + arc_list_init(B2); + arc_list_init(T1); + arc_list_init(T2); +} + +struct arc_item _LRUitem, *LRUitem = &_LRUitem; + +static void +REPLACE(struct arc_item *x_t, int p) +{ + + + init_arc_item(LRUitem, IID_INVAL, false); + + if ((lengthof(T1) != 0) && + ((lengthof(T1) > p) || + (memberof(B2, x_t) && (lengthof(T1) == p)))) { + /* XXX: d_step { ? */ + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + addMRU(B1, LRUitem); + } else { + readLRU(T2, LRUitem); + delLRU(T2); + cacheremove(LRUitem); + addMRU(B2, LRUitem); + } +} + +void +ARC(struct arc_item *x_t) +{ + if (memberof(T1, x_t)) { /* Case I */ + delitem(T1, x_t); + addMRU(T2, x_t); + } + + if (memberof(T2, x_t)) { /* Case I */ + delitem(T2, x_t); + addMRU(T2, x_t); + } + + if (memberof(B1, x_t)) { /* Case II */ + d1 = ((lengthof(B1) >= lengthof(B2)) ? 1 : (lengthof(B2)/lengthof(B1))); + p = min((p + d1), C); + + REPLACE(x_t, p); + + delitem(B1, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + + if (memberof(B2, x_t)) { /* Case III */ + d2 = ((lengthof(B2) >= lengthof(B1)) ? 1 : (lengthof(B1)/lengthof(B2))); + p = max((p - d2), 0); + + REPLACE(x_t, p); + + delitem(B2, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + + if (!(memberof(T1, x_t) || + memberof(B1, x_t) || + memberof(T2, x_t) || + memberof(B2, x_t))) { /* Case IV */ + + if ((lengthof(T1) + lengthof(B1)) == C) { /* Case A */ + if (lengthof(T1) < C) { + delLRU(B1); + REPLACE(x_t, p); + } else { + assert(lengthof(B1) == 0); + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + } + } + + if ((lengthof(T1) + lengthof(B1)) < C) { + if ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) >= C) { + if ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) == (2 * C)) { + + delLRU(B2); + } + + REPLACE(x_t, p); + } + } + cachefetch(x_t); + addMRU(T1, x_t); + } +} diff -urN arc.null/arc.drv arc/arc.drv --- arc.null/arc.drv 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.drv 2023-09-04 10:32:34.042373574 +0000 @@ -0,0 +1,52 @@ +/* Spin process model for Adaptive Replacement Cache algorithm. Written by cherry */ + +/* Note: What we're attempting in this driver file, is to generate an + * input trace that would exercise all code-paths of the model specified + * in arc.pml + * + * Feeding a static trace to the algorithm in array _x[N_ITEMS] is a + * acceptable alternative. + */ +#include "arc.pmh" + +#define N_ITEMS (2 * C) /* Number of distinct cache items to test with */ +#define ITEM_REPS (C / 4) /* Max repeat item requests */ +#define N_ITERATIONS 3 + +hidden arc_item _x[N_ITEMS]; /* Input state is irrelevant from a verification PoV */ +hidden int _x_iid = 0; +hidden int _item_rep = 0; +hidden byte _iterations = 0; + +/* Drive the procs */ +init { + + atomic { + do + :: + _iterations < N_ITERATIONS -> + + _x_iid = 0; + do + :: _x_iid < N_ITEMS -> + init_arc_item(_x[_x_iid], _x_iid, false); + _item_rep = 0; + do + :: _item_rep < (_x_iid % ITEM_REPS) -> + ARC(_x[_x_iid]); + _item_rep++; + :: _item_rep >= (_x_iid % ITEM_REPS) -> + break; + od + _x_iid++; + :: _x_iid >= N_ITEMS -> + break; + od + _iterations++; + :: + _iterations >= N_ITERATIONS -> + break; + od + } + +} diff -urN arc.null/arc.h arc/arc.h --- arc.null/arc.h 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.h 2023-09-06 11:27:01.777533992 +0000 @@ -0,0 +1,166 @@ +/* + * The objective of the header here is to provide a set of macros that + * reflect the interfaces designed in arc.pmh + */ + +#ifndef _ARC_H +#define _ARC_H + +#ifdef __NetBSD__ +/* TODO: */ +#else +/* Defaults to POSIX */ +#include +#include +#include +#endif + +#include "queue.h" /* We use the NetBSD version as it has no + * dependencies (except for -DNULL) . */ + +#define C 64 + +#define ARCLEN (2 * C) /* c.f ghost cache directory length constraints in arc.inv */ + +#define IID_INVAL -1 + +struct arc_item { + TAILQ_ENTRY(arc_item) qlink; + int iid; /* Unique identifier for item */ + bool cached; +}; + +struct arc_list { + TAILQ_HEAD(arc_qhead, arc_item) qhead; + int qcount; + struct arc_item item_list[ARCLEN]; /* We use static memory for demo purposes */ +}; + +inline static struct arc_item * allocmember(struct arc_list *); +inline static void freemember(struct arc_item *); +inline static struct arc_item * findmember(struct arc_list *, struct arc_item *); + +#define init_arc_item(/* &struct arc_item [] */ _arc_item_addr, \ + /* int */_iid, /*bool*/_cached) do { \ + struct arc_item *_arc_item = _arc_item_addr; \ + assert(_arc_item != NULL); \ + _arc_item->iid = _iid; \ + _arc_item->cached = _cached; \ + } while (/*CONSTCOND*/0) + +#define lengthof(/* struct arc_list* */_arc_list) (_arc_list->qcount) +#define memberof(/* struct arc_list* */_arc_list, \ + /* struct arc_item* */_arc_item) \ + ((findmember(_arc_list, \ + _arc_item) != TAILQ_END(&_arc_list->qhead)) ? \ + true : false) + +/* + * We follow spin's channel rx/tx semantics here: "send" means + * duplicate onto queue ("_arc_list.item_list!_arc_item.iid"), and + * recieve means "duplicate" from queue but leave the data source on + * queue ("_arc_list.item_list?<_arc_item.iid>"). + * + * It is an error to addMRU() on a full queue. Likewise, it is an + * error to readLRU() on an empty queue. The verifier is expected to + * have covered any case where these happen. We use assert()s to + * indicate the error. + * + * Note: We use spin's channel mechanism in our design, only because + * it's the easiest. We could have chosen another + * mechanism/implementation, if the semantics were specified + * differently due to, for eg: convention, architectural or efficiency + * reasons. + */ +#define addMRU(/* struct arc_list* */_arc_list, \ + /* struct arc_item* */_arc_item) do { \ + _arc_list->qcount++; assert(_arc_list->qcount < ARCLEN); \ + struct arc_item *aitmp = allocmember(_arc_list); \ + assert(aitmp != NULL); \ + *aitmp = *_arc_item; \ + TAILQ_INSERT_TAIL(&_arc_list->qhead, aitmp, qlink); \ + } while (/*CONSTCOND*/0) + +#define readLRU(/* struct arc_list* */_arc_list, \ + /* struct arc_item* */_arc_item) do { \ + assert(!TAILQ_EMPTY(&_arc_list->qhead)); \ + assert(_arc_item != NULL); \ + *_arc_item = *(struct arc_item *)TAILQ_FIRST(&_arc_list->qhead);\ + } while (/*CONSTCOND*/0) + +#define delLRU(/* struct arc_list* */_arc_list) \ + if (!TAILQ_EMPTY(&_arc_list->qhead)) { \ + struct arc_item *aitmp = TAILQ_FIRST(&_arc_list->qhead); \ + TAILQ_REMOVE(&_arc_list->qhead, aitmp, qlink); \ + freemember(aitmp); \ + _arc_list->qcount--; assert(_arc_list->qcount >= 0); \ + } else assert(false) + +#define delitem(/* struct arc_list* */_arc_list, \ + /* struct arc_item* */_arc_item) do { \ + struct arc_item *aitmp; \ + aitmp = findmember(_arc_list, _arc_item); \ + if (aitmp != TAILQ_END(&_arc_list->qhead)) { \ + TAILQ_REMOVE(&_arc_list->qhead, aitmp, qlink); \ + freemember(aitmp); \ + _arc_list->qcount--; assert(_arc_list->qcount >= 0); \ + } \ + } while (/*CONSTCOND*/0) + +#define cachefetch(/* struct arc_item* */_arc_item) do { \ + _arc_item->cached = true; /* XXX:TODO */ \ + } while (/*CONSTCOND*/0) + +#define cacheremove(/* struct arc_item* */_arc_item) do { \ + _arc_item->cached = false; /* XXX:TODO */ \ + } while (/*CONSTCOND*/0) + +#define min(a, b) ((a < b) ? a : b) +#define max(a, b) ((a > b) ? a : b) + +/* These routines deal with our home-rolled mem management for the + * ghost cache directory memory embedded within statically defined + * struct arc_list buffers. + * Note that any pointers emerging from these should be treated as + * "opaque"/cookies - ie; they should not be assumed by other routines + * to have any specific properties (such as being part of any specific + * array etc.) They are solely for the consumption of these + * routines. Their contents however may be freely copied/written to. + */ +inline static struct arc_item * +allocmember(struct arc_list *_arc_list) +{ + /* Search for the first unallocated item in given list */ + struct arc_item *aitmp = NULL; + for (int i = 0; i < ARCLEN; i++) { + if (_arc_list->item_list[i].iid == IID_INVAL) { + assert(_arc_list->item_list[i].cached == false); + aitmp = &_arc_list->item_list[i]; + } + } + return aitmp; + +} + +inline static void +freemember(struct arc_item *_arc_item) +{ + init_arc_item(_arc_item, IID_INVAL, false); +} + +inline static struct arc_item * +findmember(struct arc_list *_arc_list, struct arc_item *aikey) +{ + assert(_arc_list != NULL && aikey != NULL); + struct arc_item *aitmp; + TAILQ_FOREACH(aitmp, &_arc_list->qhead, qlink) { + if (aitmp->iid == aikey->iid) { + return aitmp; + } + } + return aitmp; /* returns TAILQ_END() on non-membership */ +} + +void ARC(struct arc_item * /* x_t */); + +#endif /* _ARC_H_ */ diff -urN arc.null/arc.inv arc/arc.inv --- arc.null/arc.inv 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.inv 2023-09-04 09:20:20.224107390 +0000 @@ -0,0 +1,59 @@ +/* $NetBSD$ */ + +/* These are Linear Temporal Logic invariants (and constraints) + * applied over the statespace created by the promela + * specification. Correctness is implied by Logical consistency. + */ +ltl +{ + /* Liveness - all threads, except control must finally exit */ + eventually always (_nr_pr == 1) && + /* c.f Section I. B, on page 3 of paper */ + always ((lengthof(T1) + + lengthof(B1) + + lengthof(T2) + + lengthof(B2)) <= (2 * C)) && + + /* Reading together Section III. A., on page 7, and + * Section III. B., on pages 7,8 + */ + always ((lengthof(T1) + lengthof(B1)) <= C) && + always ((lengthof(T2) + lengthof(B2)) < (2 * C)) && + + /* Section III. B, Remark III.1 */ + always ((lengthof(T1) + lengthof(T2)) <= C) && + + /* TODO: III B, A.1 */ + + /* III B, A.2 */ + always (((lengthof(T1) + + lengthof(B1) + + lengthof(T2) + + lengthof(B2)) < C) + implies ((lengthof(B1) == 0) && + lengthof(B2) == 0)) && + + /* III B, A.3 */ + always (((lengthof(T1) + + lengthof(B1) + + lengthof(T2) + + lengthof(B2)) >= C) + implies ((lengthof(T1) + + lengthof(T2) == C))) && + + /* TODO: III B, A.4 */ + + /* TODO: III B, A.5 */ + + /* IV A. */ + always (p <= C) && + + /* Not strictly true, but these force us to generate a "good" + * input trace via arc.drv + */ + + eventually /* always ? */ ((lengthof(T1) == p) && lengthof(T2) == (C - p)) && + + eventually (p > 0) + +} diff -urN arc.null/arc.pmh arc/arc.pmh --- arc.null/arc.pmh 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.pmh 2023-09-05 19:11:38.075381290 +0000 @@ -0,0 +1,54 @@ +/* Spin process model for Adaptive Replacement Cache algorithm. Written by cherry */ + +#ifndef _ARC_INC +#define _ARC_INC + +/* XXX: Move these into a set of library includes ? */ +/* XXX: Equivalence verification */ +/* Note: CAS implemented in an atomic {} block */ +#define mutex_enter(_mutex) \ + atomic { \ + (_mutex == 0) -> _mutex = 1; \ + } + +#define mutex_exit(_mutex) \ + atomic { \ + assert(_mutex == 1); \ + (_mutex == 1) -> _mutex = 0; \ + } + +bit sc_lock; + +#define C 64 /* Cache size - use judiciously - adds to statespace */ + +typedef arc_item { + int iid; /* Unique identifier for item */ + bool cached; +}; + +/* Note that we use the arc_item.iid as the member lookup handle to reduce state space */ +typedef arc_list { + chan item_list = [ 2 * C ] of { int }; /* A list of page items */ +}; + + +#define init_arc_item(_arc_item, _iid, _cached) \ + d_step { \ + _arc_item.iid = _iid; \ + _arc_item.cached = _cached; \ + } + +#define lengthof(_arc_list) len(_arc_list.item_list) +#define memberof(_arc_list, _arc_item) _arc_list.item_list??[eval(_arc_item.iid)] +#define addMRU(_arc_list, _arc_item) _arc_list.item_list!_arc_item.iid +#define readLRU(_arc_list, _arc_item) _arc_list.item_list?<_arc_item.iid> +#define delLRU(_arc_list) _arc_list.item_list?_ +#define delitem(_arc_list, _arc_item) _arc_list.item_list??eval(_arc_item.iid) + +#define cachefetch(_arc_item) _arc_item.cached = true +#define cacheremove(_arc_item) _arc_item.cached = false + +#define min(a, b) ((a < b) -> a : b) +#define max(a, b) ((a > b) -> a : b) + +#endif /* _ARC_INC_ */ \ No newline at end of file diff -urN arc.null/arc.pml arc/arc.pml --- arc.null/arc.pml 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.pml 2023-09-04 10:15:53.767411900 +0000 @@ -0,0 +1,216 @@ +/* Spin process model for Adaptive Replacement Cache algorithm. Written by cherry */ + +/* + * We implement the following algorithm from page 10, Figure 4. + * https://www.usenix.org/legacy/events/fast03/tech/full_papers/megiddo/megiddo.pdf + * + * + * ARC(c) + * + * INPUT: The request stream x1,x2,....,xt,.... + * INITIALIZATION: Set p = 0 and set the LRU lists T1, B1, T2, and B2 to empty. + * + * For every t>=1 and any xt, one and only one of the following four cases must occur. + * Case I: xt is in T1 or T2. A cache hit has occurred in ARC(c) and DBL(2c). + * Move xt to MRU position in T2. + * + * Case II: xt is in B1. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = min { p + d1,c } + * where d1 = { 1 if |B1| >= |B2|, |B2|/|B1| otherwise + * + * REPLACE(xt, p). Move xt from B1 to the MRU position in T2 (also fetch xt to the cache). + * + * Case III: xt is in B2. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = max { p - d2,0 } + * where d2 = { 1 if |B2| >= |B1|, |B1|/|B2| otherwise + * + * REPLACE(xt, p). Move xt from B2 to the MRU position in T2 (also fetch xt to the cache). + * + * Case IV: xt is not in T1 U B1 U T2 U B2. A cache miss has occurred in ARC(c) and DBL(2c). + * Case A: L1 = T1 U B1 has exactly c pages. + * If (|T1| < c) + * Delete LRU page in B1. REPLACE(xt,p). + * else + * Here B1 is empty. Delete LRU page in T1 (also remove it from the cache). + * endif + * Case B: L1 = T1 U B1 has less than c pages. + * If (|T1| + |T2| + |B1| + |B2| >= c) + * Delete LRU page in B2, if (|T1| + |T2| + |B1| + |B2| = 2c). + * REPLACE(xt, p). + * endif + * + * Finally, fetch xt to the cache and move it to MRU position in T1. + * + * Subroutine REPLACE(xt,p) + * If ( (|T1| is not empty) and ((|T1| exceeds the target p) or (xt is in B2 and |T1| = p)) ) + * Delete the LRU page in T1 (also remove it from the cache), and move it to MRU position in B1. + * else + * Delete the LRU page in T2 (also remove it from the cache), and move it to MRU position in B2. + * endif + */ + +#include "arc.pmh" + +#define IID_INVAL -1 /* XXX: move to header ? */ + +/* Temp variable to hold LRU item */ +hidden arc_item LRUitem; + +/* Adaptation "delta" variables */ +int d1, d2; +int p = 0; + +/* Declare arc lists - "shadow/ghost cache directories" */ +arc_list B1, B2, T1, T2; + +inline REPLACE(/* arc_item */ x_t, /* int */ p) +{ + /* + * Since LRUitem is declared in scope p_ARC, we expect it to be only accessible from there and REPLACE() + * as REPLACE() is only expected to be called from p_ARC. + * XXX: May need to revisit due to Modex related limitations. + */ + init_arc_item(LRUitem, IID_INVAL, false); + + if + :: + (lengthof(T1) != 0) && + ((lengthof(T1) > p) || (memberof(B2, x_t) && (lengthof(T1) == p))) + -> + d_step { + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + addMRU(B1, LRUitem); + } + + :: + else + -> + d_step { + readLRU(T2, LRUitem); + delLRU(T2); + cacheremove(LRUitem); + addMRU(B2, LRUitem); + } + fi +} + +inline ARC(/* arc_item */ x_t) +{ + if + :: /* Case I */ + memberof(T1, x_t) + -> + d_step { + delitem(T1, x_t); + addMRU(T2, x_t); + } + :: /* Case I */ + memberof(T2, x_t) + -> + d_step { + delitem(T2, x_t); + addMRU(T2, x_t); + } + :: /* Case II */ + memberof(B1, x_t) + -> + d1 = ((lengthof(B1) >= lengthof(B2)) -> 1 : (lengthof(B2)/lengthof(B1))); + p = min((p + d1), C); + + REPLACE(x_t, p); + d_step { + delitem(B1, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + :: /* Case III */ + memberof(B2, x_t) + -> + d2 = ((lengthof(B2) >= lengthof(B1)) -> 1 : (lengthof(B1)/lengthof(B2))); + p = max(p - d2, 0); + + REPLACE(x_t, p); + d_step { + delitem(B2, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + :: /* Case IV */ + !(memberof(T1, x_t) || + memberof(B1, x_t) || + memberof(T2, x_t) || + memberof(B2, x_t)) + -> + if + :: /* Case A */ + ((lengthof(T1) + lengthof(B1)) == C) + -> + if + :: + (lengthof(T1) < C) + -> + delLRU(B1); + REPLACE(x_t, p); + :: + else + -> + assert(lengthof(B1) == 0); + d_step { + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + } + fi + :: /* Case B */ + ((lengthof(T1) + lengthof(B1)) < C) + -> + if + :: + ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) >= C) + -> + if + :: + ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) == (2 * C)) + -> + delLRU(B2); + :: + else + -> + skip; + fi + REPLACE(x_t, p); + :: + else + -> + skip; + fi + :: + else + -> + skip; + fi + cachefetch(x_t); + addMRU(T1, x_t); + fi + +} + +#if 0 /* Resolve this after modex extract foo */ +proctype p_arc(arc_item x_t) +{ + /* Serialise entry */ + mutex_enter(sc_lock); + + ARC(x_t); + + mutex_exit(sc_lock); +} +#endif diff -urN arc.null/Makefile arc/Makefile --- arc.null/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ arc/Makefile 2023-09-06 11:37:35.438225102 +0000 @@ -0,0 +1,78 @@ +# This set of spinroot related files were written by cherry +# in the Gregorian Calendar year AD.2023, in the month +# of February that year. +# +# We have two specification files and a properties file +# +# The properties file contains "constraint" sections +# such as ltl or never claims (either or, not both). +# The specification is divided into two files: +# the file with suffix '.drv' is a "driver" which +# instantiates processes that will ultimately "drive" the +# models under test. +# The file with the suffix '.pml' contains the process +# model code, which, is intended to be the formal specification +# for the code we are interested in writing in C. +# +# We process these files in slightly different ways during +# the dev cycle, but broadly speaking, the idea is to create +# a file called 'spinmodel.pml' which contains the final +# model file that is fed to spin. +# +# Note that when we use the model extractor tool "modex" to +# extract the 'specification' from C code written to implement +# the model defined above. We use a 'harness' file (see file with +# suffix '.prx' below. +# +# Once the harness has been run, spinmodel.pml should be +# synthesised and processed as usual. +# +# The broad idea is that software dev starts by writing the spec +# first, validating the model, and then implementing the model in +# C, after which we come back to extract the model from the C file +# and cross check our implementation using spin. +# +# If things go well, the constraints specified in the '.ltl' file +# should hold exactly for both the handwritten model, and the +# extracted one. + +spin-gen: arc.pml arc.drv arc.inv + cp arc.pml model #mimic modex + cat model > spinmodel.pml;cat arc.drv >> spinmodel.pml;cat arc.inv >> spinmodel.pml; + spin -am spinmodel.pml + +spin-build: spin-gen + cc -DVECTORSZ=65536 -o pan pan.c + +all: spin-gen spin-build prog + +# Verification related targets. +spin-run: spin-build + ./pan -a #Generate arc.pml.trail on error + +# You run the trace only if the spin run above failed and created a trail +spin-trace: spinmodel.pml.trail + spin -t spinmodel.pml -p -g # -p (statements) -g (globals) -l (locals) -s (send) -r (recv) + ./pan -r spinmodel.pml.trail -g + +# Build the implementation +prog: arc.c arc.h + cc -o arc.o -c arc.c + +# Housekeeping +prog-clean: + rm -f arc.o +spin-run-clean: + rm -f spinmodel.pml.trail + +spin-build-clean: + rm -f pan + +spin-gen-clean: + rm -f spinmodel.pml # Our consolidated model file + rm -f _spin_nvr.tmp # Never claim file + rm -f model # Intermediate "model" file + rm -f pan.* # Spin generated source files + +clean: spin-gen-clean spin-build-clean spin-run-clean prog-clean + rm -f *~ diff -urN arc.null/queue.h arc/queue.h --- arc.null/queue.h 1970-01-01 00:00:00.000000000 +0000 +++ arc/queue.h 2021-01-16 23:51:51.000000000 +0000 @@ -0,0 +1,655 @@ +/* $NetBSD: queue.h,v 1.76 2021/01/16 23:51:51 chs Exp $ */ + +/* + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + */ + +#ifndef _SYS_QUEUE_H_ +#define _SYS_QUEUE_H_ + +/* + * This file defines five types of data structures: singly-linked lists, + * lists, simple queues, tail queues, and circular queues. + * + * A singly-linked list is headed by a single forward pointer. The + * elements are singly linked for minimum space and pointer manipulation + * overhead at the expense of O(n) removal for arbitrary elements. New + * elements can be added to the list after an existing element or at the + * head of the list. Elements being removed from the head of the list + * should use the explicit macro for this purpose for optimum + * efficiency. A singly-linked list may only be traversed in the forward + * direction. Singly-linked lists are ideal for applications with large + * datasets and few or no removals or for implementing a LIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A simple queue is headed by a pair of pointers, one the head of the + * list and the other to the tail of the list. The elements are singly + * linked to save space, so elements can only be removed from the + * head of the list. New elements can be added to the list after + * an existing element, at the head of the list, or at the end of the + * list. A simple queue may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * For details on the use of these macros, see the queue(3) manual page. + */ + +/* + * Include the definition of NULL only on NetBSD because sys/null.h + * is not available elsewhere. This conditional makes the header + * portable and it can simply be dropped verbatim into any system. + * The caveat is that on other systems some other header + * must provide NULL before the macros can be used. + */ +#ifdef __NetBSD__ +#include +#endif + +#if defined(_KERNEL) && defined(DIAGNOSTIC) +#define QUEUEDEBUG 1 +#endif + +#if defined(QUEUEDEBUG) +# if defined(_KERNEL) +# define QUEUEDEBUG_ABORT(...) panic(__VA_ARGS__) +# else +# include +# define QUEUEDEBUG_ABORT(...) err(1, __VA_ARGS__) +# endif +#endif + +/* + * Singly-linked List definitions. + */ +#define SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List access methods. + */ +#define SLIST_FIRST(head) ((head)->slh_first) +#define SLIST_END(head) NULL +#define SLIST_EMPTY(head) ((head)->slh_first == NULL) +#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define SLIST_FOREACH(var, head, field) \ + for((var) = (head)->slh_first; \ + (var) != SLIST_END(head); \ + (var) = (var)->field.sle_next) + +#define SLIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = SLIST_FIRST((head)); \ + (var) != SLIST_END(head) && \ + ((tvar) = SLIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +/* + * Singly-linked List functions. + */ +#define SLIST_INIT(head) do { \ + (head)->slh_first = SLIST_END(head); \ +} while (/*CONSTCOND*/0) + +#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + (elm)->field.sle_next = (slistelm)->field.sle_next; \ + (slistelm)->field.sle_next = (elm); \ +} while (/*CONSTCOND*/0) + +#define SLIST_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.sle_next = (head)->slh_first; \ + (head)->slh_first = (elm); \ +} while (/*CONSTCOND*/0) + +#define SLIST_REMOVE_AFTER(slistelm, field) do { \ + (slistelm)->field.sle_next = \ + SLIST_NEXT(SLIST_NEXT((slistelm), field), field); \ +} while (/*CONSTCOND*/0) + +#define SLIST_REMOVE_HEAD(head, field) do { \ + (head)->slh_first = (head)->slh_first->field.sle_next; \ +} while (/*CONSTCOND*/0) + +#define SLIST_REMOVE(head, elm, type, field) do { \ + if ((head)->slh_first == (elm)) { \ + SLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = (head)->slh_first; \ + while(curelm->field.sle_next != (elm)) \ + curelm = curelm->field.sle_next; \ + curelm->field.sle_next = \ + curelm->field.sle_next->field.sle_next; \ + } \ +} while (/*CONSTCOND*/0) + + +/* + * List definitions. + */ +#define LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List access methods. + */ +#define LIST_FIRST(head) ((head)->lh_first) +#define LIST_END(head) NULL +#define LIST_EMPTY(head) ((head)->lh_first == LIST_END(head)) +#define LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define LIST_FOREACH(var, head, field) \ + for ((var) = ((head)->lh_first); \ + (var) != LIST_END(head); \ + (var) = ((var)->field.le_next)) + +#define LIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = LIST_FIRST((head)); \ + (var) != LIST_END(head) && \ + ((tvar) = LIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define LIST_MOVE(head1, head2, field) do { \ + LIST_INIT((head2)); \ + if (!LIST_EMPTY((head1))) { \ + (head2)->lh_first = (head1)->lh_first; \ + (head2)->lh_first->field.le_prev = &(head2)->lh_first; \ + LIST_INIT((head1)); \ + } \ +} while (/*CONSTCOND*/0) + +/* + * List functions. + */ +#if defined(QUEUEDEBUG) +#define QUEUEDEBUG_LIST_INSERT_HEAD(head, elm, field) \ + if ((head)->lh_first && \ + (head)->lh_first->field.le_prev != &(head)->lh_first) \ + QUEUEDEBUG_ABORT("LIST_INSERT_HEAD %p %s:%d", (head), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_LIST_OP(elm, field) \ + if ((elm)->field.le_next && \ + (elm)->field.le_next->field.le_prev != \ + &(elm)->field.le_next) \ + QUEUEDEBUG_ABORT("LIST_* forw %p %s:%d", (elm), \ + __FILE__, __LINE__); \ + if (*(elm)->field.le_prev != (elm)) \ + QUEUEDEBUG_ABORT("LIST_* back %p %s:%d", (elm), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_LIST_POSTREMOVE(elm, field) \ + (elm)->field.le_next = (void *)1L; \ + (elm)->field.le_prev = (void *)1L; +#else +#define QUEUEDEBUG_LIST_INSERT_HEAD(head, elm, field) +#define QUEUEDEBUG_LIST_OP(elm, field) +#define QUEUEDEBUG_LIST_POSTREMOVE(elm, field) +#endif + +#define LIST_INIT(head) do { \ + (head)->lh_first = LIST_END(head); \ +} while (/*CONSTCOND*/0) + +#define LIST_INSERT_AFTER(listelm, elm, field) do { \ + QUEUEDEBUG_LIST_OP((listelm), field) \ + if (((elm)->field.le_next = (listelm)->field.le_next) != \ + LIST_END(head)) \ + (listelm)->field.le_next->field.le_prev = \ + &(elm)->field.le_next; \ + (listelm)->field.le_next = (elm); \ + (elm)->field.le_prev = &(listelm)->field.le_next; \ +} while (/*CONSTCOND*/0) + +#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ + QUEUEDEBUG_LIST_OP((listelm), field) \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + (elm)->field.le_next = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &(elm)->field.le_next; \ +} while (/*CONSTCOND*/0) + +#define LIST_INSERT_HEAD(head, elm, field) do { \ + QUEUEDEBUG_LIST_INSERT_HEAD((head), (elm), field) \ + if (((elm)->field.le_next = (head)->lh_first) != LIST_END(head))\ + (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ + (head)->lh_first = (elm); \ + (elm)->field.le_prev = &(head)->lh_first; \ +} while (/*CONSTCOND*/0) + +#define LIST_REMOVE(elm, field) do { \ + QUEUEDEBUG_LIST_OP((elm), field) \ + if ((elm)->field.le_next != NULL) \ + (elm)->field.le_next->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = (elm)->field.le_next; \ + QUEUEDEBUG_LIST_POSTREMOVE((elm), field) \ +} while (/*CONSTCOND*/0) + +#define LIST_REPLACE(elm, elm2, field) do { \ + if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ + (elm2)->field.le_next->field.le_prev = \ + &(elm2)->field.le_next; \ + (elm2)->field.le_prev = (elm)->field.le_prev; \ + *(elm2)->field.le_prev = (elm2); \ + QUEUEDEBUG_LIST_POSTREMOVE((elm), field) \ +} while (/*CONSTCOND*/0) + +/* + * Simple queue definitions. + */ +#define SIMPLEQ_HEAD(name, type) \ +struct name { \ + struct type *sqh_first; /* first element */ \ + struct type **sqh_last; /* addr of last next element */ \ +} + +#define SIMPLEQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).sqh_first } + +#define SIMPLEQ_ENTRY(type) \ +struct { \ + struct type *sqe_next; /* next element */ \ +} + +/* + * Simple queue access methods. + */ +#define SIMPLEQ_FIRST(head) ((head)->sqh_first) +#define SIMPLEQ_END(head) NULL +#define SIMPLEQ_EMPTY(head) ((head)->sqh_first == SIMPLEQ_END(head)) +#define SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) + +#define SIMPLEQ_FOREACH(var, head, field) \ + for ((var) = ((head)->sqh_first); \ + (var) != SIMPLEQ_END(head); \ + (var) = ((var)->field.sqe_next)) + +#define SIMPLEQ_FOREACH_SAFE(var, head, field, next) \ + for ((var) = ((head)->sqh_first); \ + (var) != SIMPLEQ_END(head) && \ + ((next = ((var)->field.sqe_next)), 1); \ + (var) = (next)) + +/* + * Simple queue functions. + */ +#define SIMPLEQ_INIT(head) do { \ + (head)->sqh_first = NULL; \ + (head)->sqh_last = &(head)->sqh_first; \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ + (head)->sqh_last = &(elm)->field.sqe_next; \ + (head)->sqh_first = (elm); \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.sqe_next = NULL; \ + *(head)->sqh_last = (elm); \ + (head)->sqh_last = &(elm)->field.sqe_next; \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ + (head)->sqh_last = &(elm)->field.sqe_next; \ + (listelm)->field.sqe_next = (elm); \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_REMOVE_HEAD(head, field) do { \ + if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ + (head)->sqh_last = &(head)->sqh_first; \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_REMOVE_AFTER(head, elm, field) do { \ + if (((elm)->field.sqe_next = (elm)->field.sqe_next->field.sqe_next) \ + == NULL) \ + (head)->sqh_last = &(elm)->field.sqe_next; \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_REMOVE(head, elm, type, field) do { \ + if ((head)->sqh_first == (elm)) { \ + SIMPLEQ_REMOVE_HEAD((head), field); \ + } else { \ + struct type *curelm = (head)->sqh_first; \ + while (curelm->field.sqe_next != (elm)) \ + curelm = curelm->field.sqe_next; \ + if ((curelm->field.sqe_next = \ + curelm->field.sqe_next->field.sqe_next) == NULL) \ + (head)->sqh_last = &(curelm)->field.sqe_next; \ + } \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_CONCAT(head1, head2) do { \ + if (!SIMPLEQ_EMPTY((head2))) { \ + *(head1)->sqh_last = (head2)->sqh_first; \ + (head1)->sqh_last = (head2)->sqh_last; \ + SIMPLEQ_INIT((head2)); \ + } \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_LAST(head, type, field) \ + (SIMPLEQ_EMPTY((head)) ? \ + NULL : \ + ((struct type *)(void *) \ + ((char *)((head)->sqh_last) - offsetof(struct type, field)))) + +/* + * Tail queue definitions. + */ +#define _TAILQ_HEAD(name, type, qual) \ +struct name { \ + qual type *tqh_first; /* first element */ \ + qual type *qual *tqh_last; /* addr of last next element */ \ +} +#define TAILQ_HEAD(name, type) _TAILQ_HEAD(name, struct type,) + +#define TAILQ_HEAD_INITIALIZER(head) \ + { TAILQ_END(head), &(head).tqh_first } + +#define _TAILQ_ENTRY(type, qual) \ +struct { \ + qual type *tqe_next; /* next element */ \ + qual type *qual *tqe_prev; /* address of previous next element */\ +} +#define TAILQ_ENTRY(type) _TAILQ_ENTRY(struct type,) + +/* + * Tail queue access methods. + */ +#define TAILQ_FIRST(head) ((head)->tqh_first) +#define TAILQ_END(head) (NULL) +#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) +#define TAILQ_LAST(head, headname) \ + (*(((struct headname *)(void *)((head)->tqh_last))->tqh_last)) +#define TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)(void *)((elm)->field.tqe_prev))->tqh_last)) +#define TAILQ_EMPTY(head) (TAILQ_FIRST(head) == TAILQ_END(head)) + + +#define TAILQ_FOREACH(var, head, field) \ + for ((var) = ((head)->tqh_first); \ + (var) != TAILQ_END(head); \ + (var) = ((var)->field.tqe_next)) + +#define TAILQ_FOREACH_SAFE(var, head, field, next) \ + for ((var) = ((head)->tqh_first); \ + (var) != TAILQ_END(head) && \ + ((next) = TAILQ_NEXT(var, field), 1); (var) = (next)) + +#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var) != TAILQ_END(head); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, prev) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var) != TAILQ_END(head) && \ + ((prev) = TAILQ_PREV((var), headname, field), 1); (var) = (prev)) + +/* + * Tail queue functions. + */ +#if defined(QUEUEDEBUG) +#define QUEUEDEBUG_TAILQ_INSERT_HEAD(head, elm, field) \ + if ((head)->tqh_first && \ + (head)->tqh_first->field.tqe_prev != &(head)->tqh_first) \ + QUEUEDEBUG_ABORT("TAILQ_INSERT_HEAD %p %s:%d", (head), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_TAILQ_INSERT_TAIL(head, elm, field) \ + if (*(head)->tqh_last != NULL) \ + QUEUEDEBUG_ABORT("TAILQ_INSERT_TAIL %p %s:%d", (head), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_TAILQ_OP(elm, field) \ + if ((elm)->field.tqe_next && \ + (elm)->field.tqe_next->field.tqe_prev != \ + &(elm)->field.tqe_next) \ + QUEUEDEBUG_ABORT("TAILQ_* forw %p %s:%d", (elm), \ + __FILE__, __LINE__); \ + if (*(elm)->field.tqe_prev != (elm)) \ + QUEUEDEBUG_ABORT("TAILQ_* back %p %s:%d", (elm), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_TAILQ_PREREMOVE(head, elm, field) \ + if ((elm)->field.tqe_next == NULL && \ + (head)->tqh_last != &(elm)->field.tqe_next) \ + QUEUEDEBUG_ABORT("TAILQ_PREREMOVE head %p elm %p %s:%d",\ + (head), (elm), __FILE__, __LINE__); +#define QUEUEDEBUG_TAILQ_POSTREMOVE(elm, field) \ + (elm)->field.tqe_next = (void *)1L; \ + (elm)->field.tqe_prev = (void *)1L; +#else +#define QUEUEDEBUG_TAILQ_INSERT_HEAD(head, elm, field) +#define QUEUEDEBUG_TAILQ_INSERT_TAIL(head, elm, field) +#define QUEUEDEBUG_TAILQ_OP(elm, field) +#define QUEUEDEBUG_TAILQ_PREREMOVE(head, elm, field) +#define QUEUEDEBUG_TAILQ_POSTREMOVE(elm, field) +#endif + +#define TAILQ_INIT(head) do { \ + (head)->tqh_first = TAILQ_END(head); \ + (head)->tqh_last = &(head)->tqh_first; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_INSERT_HEAD(head, elm, field) do { \ + QUEUEDEBUG_TAILQ_INSERT_HEAD((head), (elm), field) \ + if (((elm)->field.tqe_next = (head)->tqh_first) != TAILQ_END(head))\ + (head)->tqh_first->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (head)->tqh_first = (elm); \ + (elm)->field.tqe_prev = &(head)->tqh_first; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_INSERT_TAIL(head, elm, field) do { \ + QUEUEDEBUG_TAILQ_INSERT_TAIL((head), (elm), field) \ + (elm)->field.tqe_next = TAILQ_END(head); \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &(elm)->field.tqe_next; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + QUEUEDEBUG_TAILQ_OP((listelm), field) \ + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != \ + TAILQ_END(head)) \ + (elm)->field.tqe_next->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (listelm)->field.tqe_next = (elm); \ + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + QUEUEDEBUG_TAILQ_OP((listelm), field) \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + (elm)->field.tqe_next = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_REMOVE(head, elm, field) do { \ + QUEUEDEBUG_TAILQ_PREREMOVE((head), (elm), field) \ + QUEUEDEBUG_TAILQ_OP((elm), field) \ + if (((elm)->field.tqe_next) != TAILQ_END(head)) \ + (elm)->field.tqe_next->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ + QUEUEDEBUG_TAILQ_POSTREMOVE((elm), field); \ +} while (/*CONSTCOND*/0) + +#define TAILQ_REPLACE(head, elm, elm2, field) do { \ + if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != \ + TAILQ_END(head)) \ + (elm2)->field.tqe_next->field.tqe_prev = \ + &(elm2)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm2)->field.tqe_next; \ + (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ + *(elm2)->field.tqe_prev = (elm2); \ + QUEUEDEBUG_TAILQ_POSTREMOVE((elm), field); \ +} while (/*CONSTCOND*/0) + +#define TAILQ_CONCAT(head1, head2, field) do { \ + if (!TAILQ_EMPTY(head2)) { \ + *(head1)->tqh_last = (head2)->tqh_first; \ + (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ + (head1)->tqh_last = (head2)->tqh_last; \ + TAILQ_INIT((head2)); \ + } \ +} while (/*CONSTCOND*/0) + +/* + * Singly-linked Tail queue declarations. + */ +#define STAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first; /* first element */ \ + struct type **stqh_last; /* addr of last next element */ \ +} + +#define STAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first } + +#define STAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue access methods. + */ +#define STAILQ_FIRST(head) ((head)->stqh_first) +#define STAILQ_END(head) NULL +#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) +#define STAILQ_EMPTY(head) (STAILQ_FIRST(head) == STAILQ_END(head)) + +/* + * Singly-linked Tail queue functions. + */ +#define STAILQ_INIT(head) do { \ + (head)->stqh_first = NULL; \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (/*CONSTCOND*/0) + +#define STAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (head)->stqh_first = (elm); \ +} while (/*CONSTCOND*/0) + +#define STAILQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.stqe_next = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &(elm)->field.stqe_next; \ +} while (/*CONSTCOND*/0) + +#define STAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.stqe_next = (listelm)->field.stqe_next) == NULL)\ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (listelm)->field.stqe_next = (elm); \ +} while (/*CONSTCOND*/0) + +#define STAILQ_REMOVE_HEAD(head, field) do { \ + if (((head)->stqh_first = (head)->stqh_first->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (/*CONSTCOND*/0) + +#define STAILQ_REMOVE(head, elm, type, field) do { \ + if ((head)->stqh_first == (elm)) { \ + STAILQ_REMOVE_HEAD((head), field); \ + } else { \ + struct type *curelm = (head)->stqh_first; \ + while (curelm->field.stqe_next != (elm)) \ + curelm = curelm->field.stqe_next; \ + if ((curelm->field.stqe_next = \ + curelm->field.stqe_next->field.stqe_next) == NULL) \ + (head)->stqh_last = &(curelm)->field.stqe_next; \ + } \ +} while (/*CONSTCOND*/0) + +#define STAILQ_FOREACH(var, head, field) \ + for ((var) = ((head)->stqh_first); \ + (var); \ + (var) = ((var)->field.stqe_next)) + +#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = STAILQ_FIRST((head)); \ + (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define STAILQ_CONCAT(head1, head2) do { \ + if (!STAILQ_EMPTY((head2))) { \ + *(head1)->stqh_last = (head2)->stqh_first; \ + (head1)->stqh_last = (head2)->stqh_last; \ + STAILQ_INIT((head2)); \ + } \ +} while (/*CONSTCOND*/0) + +#define STAILQ_LAST(head, type, field) \ + (STAILQ_EMPTY((head)) ? \ + NULL : \ + ((struct type *)(void *) \ + ((char *)((head)->stqh_last) - offsetof(struct type, field)))) + +#endif /* !_SYS_QUEUE_H_ */ From nobody Wed Sep 6 19:24:32 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rgskr70rVz4s6QR; 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[89.164.226.31]) by smtp.gmail.com with ESMTPSA id r14-20020a056402034e00b00523d2a1626esm8844254edw.6.2023.09.06.12.24.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Sep 2023 12:24:33 -0700 (PDT) Message-ID: <8670bde3-58bf-66db-b228-a7d7bc94a48b@gmail.com> Date: Wed, 6 Sep 2023 21:24:32 +0200 List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Content-Language: en-US To: freebsd-hackers@freebsd.org, freebsd-dtrace@freebsd.org From: Domagoj Stolfa Subject: Structured/machine-readable output for DTrace Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spamd-Bar: --- X-Spamd-Result: default: False [-3.85 / 15.00]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.85)[-0.848]; DMARC_POLICY_ALLOW(-0.50)[gmail.com,none]; R_SPF_ALLOW(-0.20)[+ip6:2a00:1450:4000::/36]; R_DKIM_ALLOW(-0.20)[gmail.com:s=20221208]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; FROM_HAS_DN(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[2a00:1450:4864:20::52d:from]; DWL_DNSWL_NONE(0.00)[gmail.com:dkim]; ASN(0.00)[asn:15169, ipnet:2a00:1450::/32, country:US]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org,freebsd-dtrace@freebsd.org]; DKIM_TRACE(0.00)[gmail.com:+]; TO_DN_NONE(0.00)[]; FREEMAIL_FROM(0.00)[gmail.com]; TAGGED_FROM(0.00)[]; RCPT_COUNT_TWO(0.00)[2]; RCVD_TLS_LAST(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FREEMAIL_ENVFROM(0.00)[gmail.com]; MIME_TRACE(0.00)[0:+]; RCVD_COUNT_TWO(0.00)[2] X-Rspamd-Queue-Id: 4Rgskq3jNtz4HHT Hi: I've implemented machine-readable output in the form of JSON, XML and HTML into libdtrace, and by extension dtrace(1) using libxo. The goal is not to replace linking to libdtrace in any way when one wishes to build a custom application around it, but rather to supplement it (as it would now also support this form of output by default) and act as a middle-ground between linking directly to libdtrace and parsing the pretty-printed dtrace(1) output that is available today (but not replace it). In order to get it to work, you can simply run dtrace(1) as normal, but add -x oformat=json|xml|html|plain. I've posted the patch up for review if anyone wants to take a look or try it out [1] and posted a hacked up Python program (by no means good Python code) as an example of how this might be used [2]. I would appreciate any feedback you might have. As this patch is still in its early stages however, there isn't much documentation available for it. I aim to address this soon. [1]: https://reviews.freebsd.org/D41745 [2]: https://reviews.freebsd.org/D41745 -- Domagoj From nobody Thu Sep 7 02:28:06 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rh37n6jfgz4sfJS for ; Thu, 7 Sep 2023 02:28:21 +0000 (UTC) (envelope-from asomers@gmail.com) Received: from mail-ua1-f45.google.com (mail-ua1-f45.google.com [209.85.222.45]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Rh37m26MSz3bVp for ; Thu, 7 Sep 2023 02:28:20 +0000 (UTC) (envelope-from asomers@gmail.com) Authentication-Results: mx1.freebsd.org; dkim=none; spf=pass (mx1.freebsd.org: domain of asomers@gmail.com designates 209.85.222.45 as permitted sender) smtp.mailfrom=asomers@gmail.com; dmarc=none Received: by mail-ua1-f45.google.com with SMTP id a1e0cc1a2514c-79a2216a2d1so163018241.2 for ; Wed, 06 Sep 2023 19:28:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694053698; x=1694658498; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=xRKKjxx4CbBi5E1zlpKL13gmAF2Ls5SkRPHWwbFlugI=; b=IVDE0Po38fd0H1NsCyQB/cJo3yNDkum8GuGdCLpDrVWmhl2z/bLpUab9VZ/S95wPIK T0JkArp7c7VgIBn0PWzgeSxtlGUwBwuRpDgn8YuUR5kIg3aTlyyIoJn9yur23iayy9Xw Y5oy1cXpJzvHu2ihC99Ng1bXnGu7IAJnPCcKcZ+pnrt5geFSMdXuYvMlvzllfd5ZQVlt de2kcPdAQtLAcoZnk+g8oVxFLBWpQnYM+jIucfYPIe3xUGi+AjK/ge9q5c7s1rdwigie vDNZ0SHvmYLvRXKe4Nw66CF0GUL3O6Yg70Ibp+znb3Sygbmp1K6B6WOa8C+dXKNySdlS Nsjg== X-Gm-Message-State: AOJu0YykpcwusgGMtxUoIGMiIv+/oSsoyEVB3xzkRkPeRdcV5de7A0IA 9+oOcwnJdSWWbUTbj6RdEoQMGmyMEm+gaK47AKXb1k4ID/M= X-Google-Smtp-Source: AGHT+IGI8qc1yxaT0Y8xPyklrBnY2OzFMLtAdq3f9W5htmFSJsCW5oqhmk3CLHYADTUyx1TboBQPPVk4AqnjjjwjrSw= X-Received: by 2002:a67:fc15:0:b0:44e:c2d6:cbcd with SMTP id o21-20020a67fc15000000b0044ec2d6cbcdmr4540211vsq.6.1694053698347; Wed, 06 Sep 2023 19:28:18 -0700 (PDT) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 From: Alan Somers Date: Wed, 6 Sep 2023 19:28:06 -0700 Message-ID: Subject: Will we ever raise _POSIX_VERSION ? To: FreeBSD Hackers Content-Type: text/plain; charset="UTF-8" X-Spamd-Bar: - X-Spamd-Result: default: False [-1.96 / 15.00]; SUBJECT_ENDS_QUESTION(1.00)[]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-0.998]; NEURAL_HAM_LONG(-0.96)[-0.962]; FORGED_SENDER(0.30)[asomers@freebsd.org,asomers@gmail.com]; R_SPF_ALLOW(-0.20)[+ip4:209.85.128.0/17]; MIME_GOOD(-0.10)[text/plain]; PREVIOUSLY_DELIVERED(0.00)[freebsd-hackers@freebsd.org]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DMARC_NA(0.00)[freebsd.org]; RCPT_COUNT_ONE(0.00)[1]; FROM_HAS_DN(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[209.85.222.45:from]; BLOCKLISTDE_FAIL(0.00)[209.85.222.45:server fail]; FREEFALL_USER(0.00)[asomers]; TO_DOM_EQ_FROM_DOM(0.00)[]; ARC_NA(0.00)[]; RCVD_TLS_LAST(0.00)[]; RCVD_COUNT_ONE(0.00)[1]; TO_DN_ALL(0.00)[]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org]; MIME_TRACE(0.00)[0:+]; FROM_NEQ_ENVFROM(0.00)[asomers@freebsd.org,asomers@gmail.com]; FREEMAIL_ENVFROM(0.00)[gmail.com]; R_DKIM_NA(0.00)[]; ASN(0.00)[asn:15169, ipnet:209.85.128.0/17, country:US]; RWL_MAILSPIKE_POSSIBLE(0.00)[209.85.222.45:from] X-Rspamd-Queue-Id: 4Rh37m26MSz3bVp I notice that _POSIX_VERSION is still set to 200112L. That's a shame, because it prevents zstd from using utimensat and tzdata from using strftime_l, even though we implement both of those functions. And who knows what programs in ports are keying off of it. What would be required for us to confidently raise it to 200809L or later? -Alan From nobody Thu Sep 7 03:40:32 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rh4lP66Pnz4s1hM for ; Thu, 7 Sep 2023 03:40:49 +0000 (UTC) (envelope-from wlosh@bsdimp.com) Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Rh4lP1SHZz4R7B for ; Thu, 7 Sep 2023 03:40:49 +0000 (UTC) (envelope-from wlosh@bsdimp.com) Authentication-Results: mx1.freebsd.org; none Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-5298e43bb67so919164a12.1 for ; Wed, 06 Sep 2023 20:40:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20230601.gappssmtp.com; s=20230601; t=1694058045; x=1694662845; darn=freebsd.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=iHdQJegRnyAvL79nIPBLW078/2Rrsqd4IJjldykjMtk=; b=L3r+281BiOapDw/zb8uv2HFMg24gxJ+y8hHO8pFvq76vs0JS6Pzgqox26nLZWEYdD7 AGuir2ytQjNWEXg3Z1tvTAzjW0VxLecbbnoSouT13dP4wnut+AZPrFsz1LuME0NT/1QF 1OqQKfTN2u5XVpzYnM9dEhDWwnsi6QIsJbD0LGXAnDOJ+KiUSIJbmB/fXBf1YjORlgB9 Z6ESxaHtL4OE08b2o+WaFXAKZ5uAPXD0hsZ1f7y9GsNRHo/jf6mYQK/xpf/WjwDD1ULv uq1qEDyZseSu1/DuDa0/9HQGRHtEtDdUCNQD3N2yudTlplpD+muvUMtdNduh/UaSBD6w lhCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694058045; x=1694662845; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=iHdQJegRnyAvL79nIPBLW078/2Rrsqd4IJjldykjMtk=; b=fHU1W9Su2BiIbbrVb2/YIuakGRHFtPOVHge/fmUoTixidrYa1SsgVWfRNRv4N5ePM9 vDoSgxOL9c/UK5TmRK6aJJHBH62olv6pL8PhuG5jCYdjMOG1pamPxj3NGvi49SRxnYxM Doj75vOm7ULEw24qcpI/8chpIzYbcWOC+S0h1Rhvuk/cBpBFfTSvh6jJDct0nlAjZWbS 4QmgpkSqUpfTtsUW/whgxFtyzR7Tg1x2KfLNGoYGgAX1RQgRE3gNcuubz1IdPz8pLp/G Zd6rIY9J/Y9P/jW8AM+flcFYOZVOuNMwiEZuW5FvndwgbDbfkruZo7xoh7e2TIPXkppj MKGw== X-Gm-Message-State: AOJu0YzL8bpk09/H9Z1orNUR/QWA2lrPCdau4x5oc0Ch9FI+KU2jJumU CwvY9jcWaB5FAdsoelpcW3c45++NW/Nq4qkfmaMwckQUaistF/3Y X-Google-Smtp-Source: AGHT+IFbNuLB7oVS9UtuEB0XVDaRiwh4dZogh4V/Pvwi+vbuezz+cNCU4XppIlzIOPk3A2QWxgeYxnBMmfBG4xz44Xk= X-Received: by 2002:a05:6402:2883:b0:522:2add:5841 with SMTP id eg3-20020a056402288300b005222add5841mr1772954edb.7.1694058044291; Wed, 06 Sep 2023 20:40:44 -0700 (PDT) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 References: In-Reply-To: From: Warner Losh Date: Wed, 6 Sep 2023 21:40:32 -0600 Message-ID: Subject: Re: Will we ever raise _POSIX_VERSION ? To: Alan Somers Cc: FreeBSD Hackers Content-Type: multipart/alternative; boundary="000000000000f58fc80604bc9f30" X-Spamd-Bar: ---- X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:15169, ipnet:2a00:1450::/32, country:US] X-Rspamd-Queue-Id: 4Rh4lP1SHZz4R7B --000000000000f58fc80604bc9f30 Content-Type: text/plain; charset="UTF-8" On Wed, Sep 6, 2023, 8:28 PM Alan Somers wrote: > I notice that _POSIX_VERSION is still set to 200112L. That's a shame, > because it prevents zstd from using utimensat and tzdata from using > strftime_l, even though we implement both of those functions. And who > knows what programs in ports are keying off of it. What would be > required for us to confidently raise it to 200809L or later? > The delta between the two is small... It would take an exp run to find out... it would also tell you 90% of what's needed as well as trigger a few false positives where ports are naughty... Also, we should have a new standard that's the first major revision since 2001... Warner > --000000000000f58fc80604bc9f30 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Wed, Sep 6, 2023, 8:28 PM Alan Somers <asomers@freebsd.org> wrote:
I notice that _POSIX_VERSION is still set t= o 200112L.=C2=A0 That's a shame,
because it prevents zstd from using utimensat and tzdata from using
strftime_l, even though we implement both of those functions.=C2=A0 And who=
knows what programs in ports are keying off of it.=C2=A0 What would be
required for us to confidently raise it to 200809L or later?

The delta betwe= en the two is small...

I= t would take an exp run to find out... it would also tell you 90% of what&#= 39;s needed as well as trigger a few false positives where ports are naught= y...

Also, we should hav= e a new standard that's the first major revision since 2001...

Warner
--000000000000f58fc80604bc9f30-- From nobody Thu Sep 7 03:43:54 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rh4qC20dNz4s3Nt for ; Thu, 7 Sep 2023 03:44:07 +0000 (UTC) (envelope-from wlosh@bsdimp.com) Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Rh4qB5pYJz4Snd for ; Thu, 7 Sep 2023 03:44:06 +0000 (UTC) (envelope-from wlosh@bsdimp.com) Authentication-Results: mx1.freebsd.org; dkim=pass header.d=bsdimp-com.20230601.gappssmtp.com header.s=20230601 header.b="WFaf/W34"; spf=none (mx1.freebsd.org: domain of wlosh@bsdimp.com has no SPF policy when checking 2a00:1450:4864:20::534) smtp.mailfrom=wlosh@bsdimp.com; dmarc=none Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-52a4737a08fso516276a12.3 for ; Wed, 06 Sep 2023 20:44:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20230601.gappssmtp.com; s=20230601; t=1694058245; x=1694663045; darn=freebsd.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=0RL5a5G2Xg3egO+c1/jhlb5qlc+1FxLC69K2HxTQM4A=; b=WFaf/W34HBhuGudci68v+qAbS04xuT8LllLKLHWGxzWAIaXz+2/n8hKiTrJLbw7Hvu dNkpiVe0W73Yt80Gbp1lRd/NkT128Wt+UaolJSat7Og+pgqN5wvhjaOGAdxQ8C5IrWGY G78/ircgUVkMyr8dUp3GPjFII5AU4msO/pJAKvfOmRyIiBzWzqqkJYoVPBQg2Et8jll2 S5Fh4CwnRLYVgB/xaJ8p9yL9yEo/Gfp+DyP8XSg33gFV+pTXoVce1J7sNWqZH1BQQYu1 fgCIxlZ+74F7P+IZgkCVUaM1u78merdyUs3VEx1Lf+gz1PLgBCX6IDASS4OvCNxTXStH 4GCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694058245; x=1694663045; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=0RL5a5G2Xg3egO+c1/jhlb5qlc+1FxLC69K2HxTQM4A=; b=XMTKPcncygECxnTrfgBCD6tYcM+u3Hk+4DwUKvrUbt+4vQc++dDNvXubvsO3tVKcPy PCwJhWhXYGBpUcgka4fnB3zHyt6B3hbZIkZ9pP8+CVY/iRkQwfedhRaIbxTI6z5EfRTS wRcElg8i0bKziJhO+RawUrHTrDssgOopDgglNKgKTF++FSD28YjjfKP10UkcseRosJnV xly47xSvHsebKR53usPe/OcnkwJ7oKq/sTS8JaCd41hZGzv32mbDHpm43JmoygCcT5ti V42qTCl3Eas0Y1UTPwiUbor6EtnoT3w7oK6Ya5+wpEePCFkZax2sTLkOeVIBAQtOaN3R 67hQ== X-Gm-Message-State: AOJu0YxeSjqyOhruX2wkHQ9afDikaQtznHd5/LS8OaMY2kM2ilo8bbfy i+pKhUOG+jkcJ2/IX9BGoiM70sqQuXlhKKvT65jXpBRfx5s+AqYi X-Google-Smtp-Source: AGHT+IERK0Yl+/yC5w8fsN6ukynaua5k2FXfi70p7PRFTo0XtW3hNsBcH+lq4ZKpGtk2vPn29g0IBQGT7CETGLYhbW8= X-Received: by 2002:a05:6402:11ce:b0:52c:84c4:a0bf with SMTP id j14-20020a05640211ce00b0052c84c4a0bfmr5024865edw.30.1694058244930; Wed, 06 Sep 2023 20:44:04 -0700 (PDT) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 References: In-Reply-To: From: Warner Losh Date: Wed, 6 Sep 2023 21:43:54 -0600 Message-ID: Subject: Re: Will we ever raise _POSIX_VERSION ? To: Alan Somers Cc: FreeBSD Hackers Content-Type: multipart/alternative; boundary="000000000000eb1df70604bcab73" X-Spamd-Bar: - X-Spamd-Result: default: False [-2.00 / 15.00]; SUBJECT_ENDS_QUESTION(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-0.998]; FORGED_SENDER(0.30)[imp@bsdimp.com,wlosh@bsdimp.com]; R_DKIM_ALLOW(-0.20)[bsdimp-com.20230601.gappssmtp.com:s=20230601]; MIME_GOOD(-0.10)[multipart/alternative,text/plain]; RCVD_COUNT_ONE(0.00)[1]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org]; RCVD_TLS_LAST(0.00)[]; BLOCKLISTDE_FAIL(0.00)[2a00:1450:4864:20::534:server fail]; R_SPF_NA(0.00)[no SPF record]; MIME_TRACE(0.00)[0:+,1:+,2:~]; RCVD_IN_DNSWL_NONE(0.00)[2a00:1450:4864:20::534:from]; TO_DN_ALL(0.00)[]; DKIM_TRACE(0.00)[bsdimp-com.20230601.gappssmtp.com:+]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; RCPT_COUNT_TWO(0.00)[2]; PREVIOUSLY_DELIVERED(0.00)[freebsd-hackers@freebsd.org]; TO_MATCH_ENVRCPT_SOME(0.00)[]; DMARC_NA(0.00)[bsdimp.com]; ASN(0.00)[asn:15169, ipnet:2a00:1450::/32, country:US]; FROM_NEQ_ENVFROM(0.00)[imp@bsdimp.com,wlosh@bsdimp.com] X-Rspamd-Queue-Id: 4Rh4qB5pYJz4Snd --000000000000eb1df70604bcab73 Content-Type: text/plain; charset="UTF-8" On Wed, Sep 6, 2023, 9:40 PM Warner Losh wrote: > > > On Wed, Sep 6, 2023, 8:28 PM Alan Somers wrote: > >> I notice that _POSIX_VERSION is still set to 200112L. That's a shame, >> because it prevents zstd from using utimensat and tzdata from using >> strftime_l, even though we implement both of those functions. And who >> knows what programs in ports are keying off of it. What would be >> required for us to confidently raise it to 200809L or later? >> > > The delta between the two is small... > > It would take an exp run to find out... it would also tell you 90% of > what's needed as well as trigger a few false positives where ports are > naughty... > > Also, we should have a new standard that's the first major revision since > 2001... > Nobody has paid someone to do the drudge work of ticking off all the boxes... it's not terribly hard work, just tedious. Especially since there will likely be a few variations in glibc that programs expect too... Warner Warner > >> --000000000000eb1df70604bcab73 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Wed, Sep 6, 2023, 9:40 PM Warner Losh <imp@bsdimp.com> wrote:


On Wed, Sep 6, 2023, 8:28 PM Ala= n Somers <asomers@freebsd.org> wrote:
I notice that _POSIX_VERSION is still set to 200112L.=C2=A0= That's a shame,
because it prevents zstd from using utimensat and tzdata from using
strftime_l, even though we implement both of those functions.=C2=A0 And who=
knows what programs in ports are keying off of it.=C2=A0 What would be
required for us to confidently raise it to 200809L or later?

The delta betwe= en the two is small...

I= t would take an exp run to find out... it would also tell you 90% of what&#= 39;s needed as well as trigger a few false positives where ports are naught= y...

Also, we should hav= e a new standard that's the first major revision since 2001...

N= obody has paid someone to do the drudge work of ticking off all the boxes..= . it's not terribly hard work, just tedious.=C2=A0 Especially since the= re will likely be a few variations in glibc that programs expect too...

Warner

Warner
--000000000000eb1df70604bcab73-- From nobody Thu Sep 7 06:45:19 2023 X-Original-To: hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rh8rK5vh2z4smjM for ; Thu, 7 Sep 2023 06:45:21 +0000 (UTC) (envelope-from bapt@freebsd.org) Received: from smtp.freebsd.org (smtp.freebsd.org [96.47.72.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "smtp.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Rh8rK391Zz4Pr5; Thu, 7 Sep 2023 06:45:21 +0000 (UTC) (envelope-from bapt@freebsd.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1694069121; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=C1IIzK8MS2xqG2h1uheHNTdU4S7pSSrqIlQ1SHIpSTs=; b=I+2CK0NPSH3QMae9wbTevIVkhOBOwuXFbyuJjEQQ2UbqwWrizrj4t3g70/vuunNdtHJSNY r5fLbGTbl0d+iPlDygaXDc9jfAnkgSItJ2e0ibTYZJRkL+5gfzlVEQp81t5dUTRXRTutrH hFA3r63tAiI0JJkUcvJyza1+kmtWiay1tVsuE3ctxMGo13zgnaXmamEHyn/+I2Mh1IJpGz Hb9ea3YjjZGBY1DYUchUTd6xPMo3jtIWHzmgAY21KMCzFrPMegbY1JAIVahRwSxM5XAeGP SvZNCa2h0NuB4tCgeBaFDwR2eLaot6rrqv8RsMHQx4bHwN029BiOOe+7bKOR9w== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1694069121; a=rsa-sha256; cv=none; b=OOpl2HC/Ndue+xDrTpQgQDIEZrLyyWG7kEhwlPdGwB8sN/mttES+5RvDduVjDCFJrVHe5D 5Za3QN4gJO/A0wsz2wo2nnLNY8yzVYEMpgMdTkbWFToSiM5f3wMGnWhEJsPH1IDHj7qZhp 9rQYkJMfpGnk6oBedtfdMN6fm9qJCd06nYHxwt+lMaXCMgv5ITs39TtYPQEJXfZ/7a0MEp g1W7v11P3Y6LQmL2wmb4Z0Fw8gLxGv0Axf3s+5M59d2hd7qaJ8o+ujrAyQzEiNh5Fth4Ro yoLRbGla1yT5WprOerr7Hpz3mVhUXa0efQsl6aIrzY6WyZdNuSH89Ga5026H9w== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1694069121; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=C1IIzK8MS2xqG2h1uheHNTdU4S7pSSrqIlQ1SHIpSTs=; b=UnVGzCKhpsgcVYifS8ONNWlrzgtakoJTfPj2T4kARTNs0tLg6ZxhuTBY2Xahxyyeg4q4VE bE857Xv8kAZomKPZVmRnrfNsRyD0otdbUCHkdQvAY+2Edq5PW3Eho9JIqOgEQg3+GzkiJL zCkl4zxHuO4g6BURgAlNzrCxlm8+rCdk4rtvBygNWzgPWnSkO6J6m3Q/BVX7dWPVLbzWJx Zzy7Rie6qKEA2kITyArQRKOqiJDWnFBRbYcqZMGKOGxheIoQOsUSx2eQaHiPF+Z1/3Ry4c qLA/PNj7ceeFDOtug9Tn8Hn3T3qPB7u4xLPWjFKh23lB8n8aAJyoQa1MGt7zIA== Received: from aniel.nours.eu (nours.eu [176.31.115.77]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) (Authenticated sender: bapt) by smtp.freebsd.org (Postfix) with ESMTPSA id 4Rh8rK1ZXYz14Tr; Thu, 7 Sep 2023 06:45:21 +0000 (UTC) (envelope-from bapt@freebsd.org) Received: by aniel.nours.eu (Postfix, from userid 1001) id 3C0F9155641; Thu, 7 Sep 2023 08:45:19 +0200 (CEST) Date: Thu, 7 Sep 2023 08:45:19 +0200 From: Baptiste Daroussin To: Adriaan de Groot Cc: hackers@freebsd.org, Alexander Leidinger , c@bow.st Subject: Re: ARC model specified in spinroot/promela Message-ID: References: <5846941.Zv9zXsTiuT@beastie.bionicmutton.org> List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5846941.Zv9zXsTiuT@beastie.bionicmutton.org> On Sat, Sep 02, 2023 at 12:33:18PM +0200, Adriaan de Groot wrote: > For what it's worth, spin is available from ports (devel/spin), which I've > just adopted and updated to 6.5.2, so it is quite straightforward to get this > running on any recent FreeBSD system. > > I tested only with the ancient Peterson's mutual exclusion, which resolves > instantly. Mailing-list archives don't preserve attachments, so, Cherry, if > you could send it me directly that would be lovely. I spotted A. Mader's PLC > Controller in the SPIN documents, that is one I am familiar with, and then > realised that academic papers from the 2000s don't come with source code :( > Wrong mailing list do preserve attachemnts, since we migrated out of mailman, we stopped alterring emails if a mail is distributed via the mailing list then its integrity is preserved, if you want to get the full email later on, then you can always fallback on the .txt archive which is actually the mail in a mbox format meaning readable by any sane Mail User Agent. For example for this email: https://lists.freebsd.org/archives/freebsd-hackers/2023-September/002488.txt Bapt From nobody Fri Sep 8 11:15:39 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rhtpl571zz4sLl9 for ; Fri, 8 Sep 2023 11:16:31 +0000 (UTC) (envelope-from c@bow.st) Received: from comms.drone (in.bow.st [71.19.146.166]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4Rhtph2Z6qz3H7X; Fri, 8 Sep 2023 11:16:28 +0000 (UTC) (envelope-from c@bow.st) Authentication-Results: mx1.freebsd.org; dkim=none; spf=pass (mx1.freebsd.org: domain of c@bow.st designates 71.19.146.166 as permitted sender) smtp.mailfrom=c@bow.st; dmarc=none Received: from homebase (unknown [IPv6:fe80::ff1d:976a:a7e4:ee6a]) by comms.drone (Postfix) with ESMTPSA id 5A092FCDC; Fri, 8 Sep 2023 11:16:17 +0000 (UTC) From: "Mathew\, Cherry G.*" To: "Mathew\, Cherry G.*" Cc: Alexander Leidinger , adridg@freebsd.org, freebsd-hackers@freebsd.org Subject: Re: ARC model specified in spinroot/promela References: <85jzt96qjz.fsf@bow.st> <9c424a574cdd39fc879c9ed9192556c0@Leidinger.net> <858r9o6ee0.fsf@bow.st> <85pm304dzi.fsf@bow.st> <85a5u22oxx.fsf@bow.st> <85y1hjecna.fsf@bow.st> Date: Fri, 08 Sep 2023 11:15:39 +0000 In-Reply-To: <85y1hjecna.fsf@bow.st> (Cherry G. Mathew's message of "Wed, 06 Sep 2023 11:58:49 +0000") Message-ID: <85o7icapb8.fsf@bow.st> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (berkeley-unix) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain X-Spamd-Bar: - X-Spamd-Result: default: False [-1.90 / 15.00]; HFILTER_HELO_IP_A(1.00)[comms.drone]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-1.000]; HFILTER_HELO_NORES_A_OR_MX(0.30)[comms.drone]; R_SPF_ALLOW(-0.20)[+mx]; MIME_GOOD(-0.10)[text/plain]; ONCE_RECEIVED(0.10)[]; RCPT_COUNT_THREE(0.00)[4]; R_DKIM_NA(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_ONE(0.00)[1]; MIME_TRACE(0.00)[0:+]; RCVD_TLS_ALL(0.00)[]; ASN(0.00)[asn:47066, ipnet:71.19.146.0/24, country:US]; TO_DN_SOME(0.00)[]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org]; BLOCKLISTDE_FAIL(0.00)[71.19.146.166:server fail]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; DMARC_NA(0.00)[bow.st]; TO_MATCH_ENVRCPT_SOME(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 4Rhtph2Z6qz3H7X >>>>> Mathew, Cherry G * writes: >>>>> Mathew, Cherry G * writes: > [...] >> The next step is to write the equivalent C code, compile it with >> a simple test "driver" (ideally ATF, but since this is standalone >> for the moment, I'll use something simpler, just to illustrate >> the concept), and then hook it into spin's "modex" tool, to >> extract the implicit model. Once this is done, we'll have a full >> cycle of design-> implement->verify and this will demonstrate the DDD (Design >> Driven Development) methodology I'd love to hear your thoughts >> about. > I'm attaching below patch (with the usual instructions) to give a > sense of direction. At this point, the C code is purely manually > crafted. The next step (modex extraction) ties the original model > (arc.pml and friends) to the extracted code (arc.c and friends). I > am working on that next, and will post later in the week when > that's done. Follow up as promised. Please see below patch with the usual instructions. There's a slight complication though, in that the modex tool isn't packaged for most OSs. It's fairly straightforward to compile it on a posix-y build environment though. You can grab the sources here: https://github.com/nimble-code/Modex I think at this stage a few comments on the model extraction are important: 1) The usual pattern for spin modex is to convert the source code into C code "snippets" that sit within the extracted promela source. What then happens is that, subsets of the code's data state space are exported to the model, which can then be subject to the usual LTL invariance checks. I've taken a different approach here - slightly abusing the extractor framework, I have basically "converted" the C source code back as close to the original model as possible. In order to see this in action, do the following: $ make clean modex-gen $ cp spinmodel.pml /tmp/spinmodel-modex.pml $ make clean spin-gen $ diff -u spinmodel /tmp/spinmodel-modex.pml When you make the comparison, you will see that the extraction attempts a source model level retrieval. I ran this by the author of spin (Dr. Gerard Holzmann) and he said the approach looked interesting. The problem is that the "harness language" used to drive the extraction is very brittle and has terrible syntax IMHO (whoever thought up as token separator ?!!!). See arc.prx for this in action. The advantage of this approach is that you can virtually assume that if the model passes verification, then any logical bugs lie elsewhere. Interestingly, I now have a good challenge, as the queue.h manipulation I have done via arc.h does crash (at delLRU() ). So this will be a good test of my theory. At the very least, the model extraction process is a far more rigourous process of code review - where questions about logic can be asked formally via the LTL constraints. 2) The modex data object export support is terrible - it only supports basic data types, and the source parser is unable to automatically export expressions. As you probably noticed in the arc.prx file, I've kludged around this by doing effectively a sed s// over all expressions in the source code. This shortcoming can be addressed by improving the modex parser code. I have applied for a research grant in this regard, and if it comes through, then I am committed to fixing it (in consultation with the primary author, of course). 3) The gap between extracted code, and the "glue" that allows it to be driven both as a final compiled program, and as a module under test can be addressed by setting up infrastructure that I'm calling "Equivalence Verification/Testing". For eg: the semantics of readLRU()/delLRU() are implemented using spin "channel"s in the model, and a simple queue(3) mechanism in the C implementation. Equivalence will guarantee that they implement the intended semantics accurately. I believe that the *BSD OSs have a firm USP, if we can implement modular verification as part of the CI infrastructure - having a mirror "Equivalence" infrastructure will make this process much easier for new modules, as well as ingesting existing ones. With that thought, I take leave for the weekend, and hope to put my money where my mouth is, by debugging the current C implementation using ideas described above. $ make prog $ ./arc should give you a crash dump for gdb, which, I'm getting a SEG fault at delLRU() well into the caching input trace (T1 has 59 out of 64 entries filled!) Finally, if you know anyone contracting or hiring software Engineers or Leads, where an intersect between concurret programming and modelling is interesting, please signpost me (offlist of course). Have a great weekend! -- ~cherry diff -urN arc.null/arc.c arc/arc.c --- arc.null/arc.c 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.c 2023-09-07 07:56:40.245824950 +0000 @@ -0,0 +1,174 @@ +/* C Implementation of the Adaptive Replacement Cache algorithm. Written by cherry */ + +/* + * We implement the following algorithm from page 10, Figure 4. + * https://www.usenix.org/legacy/events/fast03/tech/full_papers/megiddo/megiddo.pdf + * + * + * ARC(c) + * + * INPUT: The request stream x1,x2,....,xt,.... + * INITIALIZATION: Set p = 0 and set the LRU lists T1, B1, T2, and B2 to empty. + * + * For every t>=1 and any xt, one and only one of the following four cases must occur. + * Case I: xt is in T1 or T2. A cache hit has occurred in ARC(c) and DBL(2c). + * Move xt to MRU position in T2. + * + * Case II: xt is in B1. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = min { p + d1,c } + * where d1 = { 1 if |B1| >= |B2|, |B2|/|B1| otherwise + * + * REPLACE(xt, p). Move xt from B1 to the MRU position in T2 (also fetch xt to the cache). + * + * Case III: xt is in B2. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = max { p - d2,0 } + * where d2 = { 1 if |B2| >= |B1|, |B1|/|B2| otherwise + * + * REPLACE(xt, p). Move xt from B2 to the MRU position in T2 (also fetch xt to the cache). + * + * Case IV: xt is not in T1 U B1 U T2 U B2. A cache miss has occurred in ARC(c) and DBL(2c). + * Case A: L1 = T1 U B1 has exactly c pages. + * If (|T1| < c) + * Delete LRU page in B1. REPLACE(xt,p). + * else + * Here B1 is empty. Delete LRU page in T1 (also remove it from the cache). + * endif + * Case B: L1 = T1 U B1 has less than c pages. + * If (|T1| + |T2| + |B1| + |B2| >= c) + * Delete LRU page in B2, if (|T1| + |T2| + |B1| + |B2| = 2c). + * REPLACE(xt, p). + * endif + * + * Finally, fetch xt to the cache and move it to MRU position in T1. + * + * Subroutine REPLACE(xt,p) + * If ( (|T1| is not empty) and ((|T1| exceeds the target p) or (xt is in B2 and |T1| = p)) ) + * Delete the LRU page in T1 (also remove it from the cache), and move it to MRU position in B1. + * else + * Delete the LRU page in T2 (also remove it from the cache), and move it to MRU position in B2. + * endif + */ + +#include "arc.h" + +static void arc_list_init(struct arc_list *_arc_list) +{ + TAILQ_INIT(&_arc_list->qhead); + _arc_list->qcount = 0; + + int i; + for(i = 0; i < ARCLEN; i++) { + init_arc_item(&_arc_list->item_list[i], IID_INVAL, false); + }; +} + +int p, d1, d2; +struct arc_list _B1, *B1 = &_B1, _B2, *B2 = &_B2, _T1, *T1 = &_T1, _T2, *T2 = &_T2; + +void arc_init(void) +{ + p = d1 = d2 = 0; + + arc_list_init(B1); + arc_list_init(B2); + arc_list_init(T1); + arc_list_init(T2); +} + +struct arc_item _LRUitem, *LRUitem = &_LRUitem; + +static void +REPLACE(struct arc_item *x_t, int p) +{ + + + init_arc_item(LRUitem, IID_INVAL, false); + + if ((lengthof(T1) != 0) && + ((lengthof(T1) > p) || + (memberof(B2, x_t) && (lengthof(T1) == p)))) { + /* XXX: d_step { ? */ + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + addMRU(B1, LRUitem); + } else { + readLRU(T2, LRUitem); + delLRU(T2); + cacheremove(LRUitem); + addMRU(B2, LRUitem); + } +} + +void +ARC(struct arc_item *x_t) +{ + if (memberof(T1, x_t)) { /* Case I */ + delitem(T1, x_t); + addMRU(T2, x_t); + } + + if (memberof(T2, x_t)) { /* Case I */ + delitem(T2, x_t); + addMRU(T2, x_t); + } + + if (memberof(B1, x_t)) { /* Case II */ + d1 = ((lengthof(B1) >= lengthof(B2)) ? 1 : (lengthof(B2)/lengthof(B1))); + p = min((p + d1), C); + + REPLACE(x_t, p); + + delitem(B1, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + + if (memberof(B2, x_t)) { /* Case III */ + d2 = ((lengthof(B2) >= lengthof(B1)) ? 1 : (lengthof(B1)/lengthof(B2))); + p = max((p - d2), 0); + + REPLACE(x_t, p); + + delitem(B2, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + + if (!(memberof(T1, x_t) || + memberof(B1, x_t) || + memberof(T2, x_t) || + memberof(B2, x_t))) { /* Case IV */ + + if ((lengthof(T1) + lengthof(B1)) == C) { /* Case A */ + if (lengthof(T1) < C) { + delLRU(B1); + REPLACE(x_t, p); + } else { + assert(lengthof(B1) == 0); + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + } + } + + if ((lengthof(T1) + lengthof(B1)) < C) { + if ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) >= C) { + if ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) == (2 * C)) { + + delLRU(B2); + } + + REPLACE(x_t, p); + } + } + cachefetch(x_t); + addMRU(T1, x_t); + } +} diff -urN arc.null/arc.drv arc/arc.drv --- arc.null/arc.drv 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.drv 2023-09-07 16:43:18.906339006 +0000 @@ -0,0 +1,52 @@ +/* Spin process model for Adaptive Replacement Cache algorithm. Written by cherry */ + +/* Note: What we're attempting in this driver file, is to generate an + * input trace that would exercise all code-paths of the model specified + * in arc.pml + * + * Feeding a static trace to the algorithm in array _x[N_ITEMS] is a + * acceptable alternative. + */ +/* #include "arc.pmh" See Makefile , spinmodel.pml */ + +#define N_ITEMS (2 * C) /* Number of distinct cache items to test with */ +#define ITEM_REPS (C / 4) /* Max repeat item requests */ +#define N_ITERATIONS 3 + +hidden arc_item _x[N_ITEMS]; /* Input state is irrelevant from a verification PoV */ +hidden int _x_iid = 0; +hidden int _item_rep = 0; +hidden int _iterations = 0; + +/* Drive the procs */ +init { + + atomic { + do + :: + _iterations < N_ITERATIONS -> + + _x_iid = 0; + do + :: _x_iid < N_ITEMS -> + init_arc_item(_x[_x_iid], _x_iid, false); + _item_rep = 0; + do + :: _item_rep < (_x_iid % ITEM_REPS) -> + ARC(_x[_x_iid]); + _item_rep++; + :: _item_rep >= (_x_iid % ITEM_REPS) -> + break; + od + _x_iid++; + :: _x_iid >= N_ITEMS -> + break; + od + _iterations++; + :: + _iterations >= N_ITERATIONS -> + break; + od + } + +} diff -urN arc.null/arc_drv.c arc/arc_drv.c --- arc.null/arc_drv.c 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc_drv.c 2023-09-06 14:25:07.045001611 +0000 @@ -0,0 +1,33 @@ +#include "arc.h" + +#define N_ITEMS (2 * C) /* Number of distinct cache items to test with */ +#define ITEM_REPS (C / 4) /* Max repeat item requests */ +#define N_ITERATIONS 3 + +static struct arc_item _x[N_ITEMS]; /* Input state is irrelevant from a verification PoV */ +static int _x_iid = 0; +static int _item_rep = 0; +static int _iterations = 0; + +/* Drive ARC() with a preset input trace */ + +void +main(void) +{ + arc_init(); /* Init module state */ + + while (_iterations < N_ITERATIONS) { + _x_iid = 0; + while (_x_iid < N_ITEMS) { + init_arc_item(&_x[_x_iid], _x_iid, false); + _item_rep = 0; + while(_item_rep < (_x_iid % ITEM_REPS) ) { + ARC(&_x[_x_iid]); + _item_rep++; + } + _x_iid++; + } + _iterations++; + } +} + diff -urN arc.null/arc.h arc/arc.h --- arc.null/arc.h 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.h 2023-09-08 10:09:17.217694851 +0000 @@ -0,0 +1,169 @@ +/* + * The objective of the header here is to provide a set of macros that + * reflect the interfaces designed in arc.pmh + */ + +#ifndef _ARC_H_ +#define _ARC_H_ + +#ifdef __NetBSD__ +/* TODO: */ +#else +/* Defaults to POSIX */ +#include +#include +#include +#endif + +#include "queue.h" /* We use the NetBSD version as it has no + * dependencies (except for -DNULL) . */ + +#define C 64 + +#define ARCLEN (2 * C) /* c.f ghost cache directory length constraints in arc.inv */ + +#define IID_INVAL -1 + +struct arc_item { + TAILQ_ENTRY(arc_item) qlink; + int iid; /* Unique identifier for item */ + bool cached; +}; + +struct arc_list { + TAILQ_HEAD(arc_qhead, arc_item) qhead; + int qcount; + struct arc_item item_list[ARCLEN]; /* We use static memory for demo purposes */ +}; + +inline static struct arc_item * allocmember(struct arc_list *); +inline static void freemember(struct arc_item *); +inline static struct arc_item * findmember(struct arc_list *, struct arc_item *); + +#define init_arc_item(/* &struct arc_item [] */ _arc_item_addr, \ + /* int */_iid, /*bool*/_cached) do { \ + struct arc_item *_arc_item = _arc_item_addr; \ + assert(_arc_item != NULL); \ + _arc_item->iid = _iid; \ + _arc_item->cached = _cached; \ + } while (/*CONSTCOND*/0) + +#define lengthof(/* struct arc_list* */_arc_list) (_arc_list->qcount) +#define memberof(/* struct arc_list* */_arc_list, \ + /* struct arc_item* */_arc_item) \ + ((findmember(_arc_list, \ + _arc_item) != TAILQ_END(&_arc_list->qhead)) ? \ + true : false) + +/* + * We follow spin's channel rx/tx semantics here: "send" means + * duplicate onto queue ("_arc_list.item_list!_arc_item.iid"), and + * recieve means "duplicate" from queue but leave the data source on + * queue ("_arc_list.item_list?<_arc_item.iid>"). + * + * It is an error to addMRU() on a full queue. Likewise, it is an + * error to readLRU() on an empty queue. The verifier is expected to + * have covered any case where these happen. We use assert()s to + * indicate the error. + * + * Note: We use spin's channel mechanism in our design, only because + * it's the easiest. We could have chosen another + * mechanism/implementation, if the semantics were specified + * differently due to, for eg: convention, architectural or efficiency + * reasons. + */ +#define addMRU(/* struct arc_list* */_arc_list, \ + /* struct arc_item* */_arc_item) do { \ + _arc_list->qcount++; assert(_arc_list->qcount < ARCLEN); \ + struct arc_item *aitmp = allocmember(_arc_list); \ + assert(aitmp != NULL); \ + *aitmp = *_arc_item; \ + TAILQ_INSERT_TAIL(&_arc_list->qhead, aitmp, qlink); \ + } while (/*CONSTCOND*/0) + +#define readLRU(/* struct arc_list* */_arc_list, \ + /* struct arc_item* */_arc_item) do { \ + assert(!TAILQ_EMPTY(&_arc_list->qhead)); \ + assert(_arc_item != NULL); \ + *_arc_item = *(struct arc_item *)TAILQ_FIRST(&_arc_list->qhead);\ + } while (/*CONSTCOND*/0) + +#define delLRU(/* struct arc_list* */_arc_list) \ + if (!TAILQ_EMPTY(&_arc_list->qhead)) { \ + struct arc_item *aitmp = TAILQ_FIRST(&_arc_list->qhead); \ + TAILQ_REMOVE(&_arc_list->qhead, aitmp, qlink); \ + freemember(aitmp); \ + _arc_list->qcount--; assert(_arc_list->qcount >= 0); \ + } else assert(false) + +#define delitem(/* struct arc_list* */_arc_list, \ + /* struct arc_item* */_arc_item) do { \ + struct arc_item *aitmp; \ + aitmp = findmember(_arc_list, _arc_item); \ + if (aitmp != TAILQ_END(&_arc_list->qhead)) { \ + TAILQ_REMOVE(&_arc_list->qhead, aitmp, qlink); \ + freemember(aitmp); \ + _arc_list->qcount--; assert(_arc_list->qcount >= 0); \ + } \ + } while (/*CONSTCOND*/0) + +#define cachefetch(/* struct arc_item* */_arc_item) do { \ + _arc_item->cached = true; /* XXX:TODO */ \ + } while (/*CONSTCOND*/0) + +#define cacheremove(/* struct arc_item* */_arc_item) do { \ + _arc_item->cached = false; /* XXX:TODO */ \ + } while (/*CONSTCOND*/0) + +#define min(a, b) ((a < b) ? a : b) +#define max(a, b) ((a > b) ? a : b) + +/* These routines deal with our home-rolled mem management for the + * ghost cache directory memory embedded within statically defined + * struct arc_list buffers. + * Note that any pointers emerging from these should be treated as + * "opaque"/cookies - ie; they should not be assumed by other routines + * to have any specific properties (such as being part of any specific + * array etc.) They are solely for the consumption of these + * routines. Their contents however may be freely copied/written to. + */ +inline static struct arc_item * +allocmember(struct arc_list *_arc_list) +{ + /* Search for the first unallocated item in given list */ + struct arc_item *aitmp = NULL; + int i; + for (i = 0; i < ARCLEN; i++) { + if (_arc_list->item_list[i].iid == IID_INVAL) { + assert(_arc_list->item_list[i].cached == false); + aitmp = &_arc_list->item_list[i]; + } + } + return aitmp; + +} + +inline static void +freemember(struct arc_item *_arc_item) +{ + init_arc_item(_arc_item, IID_INVAL, false); +} + +static inline struct arc_item * +findmember(struct arc_list *_arc_list, struct arc_item *aikey) +{ + assert(_arc_list != NULL && aikey != NULL); + assert(aikey->iid != IID_INVAL); + struct arc_item *aitmp; + TAILQ_FOREACH(aitmp, &_arc_list->qhead, qlink) { + if (aitmp->iid == aikey->iid) { + return aitmp; + } + } + return aitmp; /* returns TAILQ_END() on non-membership */ +} + +void ARC(struct arc_item * /* x_t */); +void arc_init(void); + +#endif /* _ARC_H_ */ diff -urN arc.null/arc.inv arc/arc.inv --- arc.null/arc.inv 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.inv 2023-09-04 09:20:20.224107390 +0000 @@ -0,0 +1,59 @@ +/* $NetBSD$ */ + +/* These are Linear Temporal Logic invariants (and constraints) + * applied over the statespace created by the promela + * specification. Correctness is implied by Logical consistency. + */ +ltl +{ + /* Liveness - all threads, except control must finally exit */ + eventually always (_nr_pr == 1) && + /* c.f Section I. B, on page 3 of paper */ + always ((lengthof(T1) + + lengthof(B1) + + lengthof(T2) + + lengthof(B2)) <= (2 * C)) && + + /* Reading together Section III. A., on page 7, and + * Section III. B., on pages 7,8 + */ + always ((lengthof(T1) + lengthof(B1)) <= C) && + always ((lengthof(T2) + lengthof(B2)) < (2 * C)) && + + /* Section III. B, Remark III.1 */ + always ((lengthof(T1) + lengthof(T2)) <= C) && + + /* TODO: III B, A.1 */ + + /* III B, A.2 */ + always (((lengthof(T1) + + lengthof(B1) + + lengthof(T2) + + lengthof(B2)) < C) + implies ((lengthof(B1) == 0) && + lengthof(B2) == 0)) && + + /* III B, A.3 */ + always (((lengthof(T1) + + lengthof(B1) + + lengthof(T2) + + lengthof(B2)) >= C) + implies ((lengthof(T1) + + lengthof(T2) == C))) && + + /* TODO: III B, A.4 */ + + /* TODO: III B, A.5 */ + + /* IV A. */ + always (p <= C) && + + /* Not strictly true, but these force us to generate a "good" + * input trace via arc.drv + */ + + eventually /* always ? */ ((lengthof(T1) == p) && lengthof(T2) == (C - p)) && + + eventually (p > 0) + +} diff -urN arc.null/arc.pmh arc/arc.pmh --- arc.null/arc.pmh 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.pmh 2023-09-08 10:36:52.827695101 +0000 @@ -0,0 +1,38 @@ +/* Spin process model for Adaptive Replacement Cache algorithm. Written by cherry */ + +#ifndef _ARC_INC +#define _ARC_INC + +#define C 64 /* Cache size - use judiciously - adds to statespace */ + +typedef arc_item { + int iid; /* Unique identifier for item */ + bool cached; +}; + +/* Note that we use the arc_item.iid as the member lookup handle to reduce state space */ +typedef arc_list { + chan item_list = [ 2 * C ] of { int }; /* A list of page items */ +}; + + +#define init_arc_item(_arc_item, _iid, _cached) \ + { \ + _arc_item.iid = _iid; \ + _arc_item.cached = _cached; \ + } + +#define lengthof(_arc_list) len(_arc_list.item_list) +#define memberof(_arc_list, _arc_item) _arc_list.item_list??[eval(_arc_item.iid)] +#define addMRU(_arc_list, _arc_item) _arc_list.item_list!_arc_item.iid +#define readLRU(_arc_list, _arc_item) _arc_list.item_list?<_arc_item.iid> +#define delLRU(_arc_list) _arc_list.item_list?_ +#define delitem(_arc_list, _arc_item) _arc_list.item_list??eval(_arc_item.iid) + +#define cachefetch(_arc_item) _arc_item.cached = true +#define cacheremove(_arc_item) _arc_item.cached = false + +#define min(a, b) ((a < b) -> a : b) +#define max(a, b) ((a > b) -> a : b) + +#endif /* _ARC_INC_ */ \ No newline at end of file diff -urN arc.null/arc.pml arc/arc.pml --- arc.null/arc.pml 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.pml 2023-09-08 10:34:47.759024169 +0000 @@ -0,0 +1,216 @@ +/* Spin process model for Adaptive Replacement Cache algorithm. Written by cherry */ + +/* + * We implement the following algorithm from page 10, Figure 4. + * https://www.usenix.org/legacy/events/fast03/tech/full_papers/megiddo/megiddo.pdf + * + * + * ARC(c) + * + * INPUT: The request stream x1,x2,....,xt,.... + * INITIALIZATION: Set p = 0 and set the LRU lists T1, B1, T2, and B2 to empty. + * + * For every t>=1 and any xt, one and only one of the following four cases must occur. + * Case I: xt is in T1 or T2. A cache hit has occurred in ARC(c) and DBL(2c). + * Move xt to MRU position in T2. + * + * Case II: xt is in B1. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = min { p + d1,c } + * where d1 = { 1 if |B1| >= |B2|, |B2|/|B1| otherwise + * + * REPLACE(xt, p). Move xt from B1 to the MRU position in T2 (also fetch xt to the cache). + * + * Case III: xt is in B2. A cache miss (resp. hit) has occurred in ARC(c) (resp. DBL(2c)). + * ADAPTATION: Update p = max { p - d2,0 } + * where d2 = { 1 if |B2| >= |B1|, |B1|/|B2| otherwise + * + * REPLACE(xt, p). Move xt from B2 to the MRU position in T2 (also fetch xt to the cache). + * + * Case IV: xt is not in T1 U B1 U T2 U B2. A cache miss has occurred in ARC(c) and DBL(2c). + * Case A: L1 = T1 U B1 has exactly c pages. + * If (|T1| < c) + * Delete LRU page in B1. REPLACE(xt,p). + * else + * Here B1 is empty. Delete LRU page in T1 (also remove it from the cache). + * endif + * Case B: L1 = T1 U B1 has less than c pages. + * If (|T1| + |T2| + |B1| + |B2| >= c) + * Delete LRU page in B2, if (|T1| + |T2| + |B1| + |B2| = 2c). + * REPLACE(xt, p). + * endif + * + * Finally, fetch xt to the cache and move it to MRU position in T1. + * + * Subroutine REPLACE(xt,p) + * If ( (|T1| is not empty) and ((|T1| exceeds the target p) or (xt is in B2 and |T1| = p)) ) + * Delete the LRU page in T1 (also remove it from the cache), and move it to MRU position in B1. + * else + * Delete the LRU page in T2 (also remove it from the cache), and move it to MRU position in B2. + * endif + */ + +/* #include "arc.pmh" See Makefile */ + +#define IID_INVAL -1 /* XXX: move to header ? */ + +/* Temp variable to hold LRU item */ +hidden arc_item LRUitem; + +/* Adaptation "delta" variables */ +int d1, d2; +int p = 0; + +/* Declare arc lists - "shadow/ghost cache directories" */ +arc_list B1, B2, T1, T2; + +inline REPLACE(/* arc_item */ x_t, /* int */ p) +{ + /* + * Since LRUitem is declared in scope p_ARC, we expect it to be only accessible from there and REPLACE() + * as REPLACE() is only expected to be called from p_ARC. + * XXX: May need to revisit due to Modex related limitations. + */ + init_arc_item(LRUitem, IID_INVAL, false); + + if + :: + (lengthof(T1) != 0) && + ((lengthof(T1) > p) || (memberof(B2, x_t) && (lengthof(T1) == p))) + -> + { + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + addMRU(B1, LRUitem); + } + + :: + else + -> + { + readLRU(T2, LRUitem); + delLRU(T2); + cacheremove(LRUitem); + addMRU(B2, LRUitem); + } + fi +} + +inline ARC(/* arc_item */ x_t) +{ + if + :: /* Case I */ + memberof(T1, x_t) + -> + { + delitem(T1, x_t); + addMRU(T2, x_t); + } + :: /* Case I */ + memberof(T2, x_t) + -> + { + delitem(T2, x_t); + addMRU(T2, x_t); + } + :: /* Case II */ + memberof(B1, x_t) + -> + d1 = ((lengthof(B1) >= lengthof(B2)) -> 1 : (lengthof(B2)/lengthof(B1))); + p = min((p + d1), C); + + REPLACE(x_t, p); + { + delitem(B1, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + :: /* Case III */ + memberof(B2, x_t) + -> + d2 = ((lengthof(B2) >= lengthof(B1)) -> 1 : (lengthof(B1)/lengthof(B2))); + p = max(p - d2, 0); + + REPLACE(x_t, p); + { + delitem(B2, x_t); + addMRU(T2, x_t); + cachefetch(x_t); + } + :: /* Case IV */ + !(memberof(T1, x_t) || + memberof(B1, x_t) || + memberof(T2, x_t) || + memberof(B2, x_t)) + -> + if + :: /* Case A */ + ((lengthof(T1) + lengthof(B1)) == C) + -> + if + :: + (lengthof(T1) < C) + -> + delLRU(B1); + REPLACE(x_t, p); + :: + else + -> + assert(lengthof(B1) == 0); + { + readLRU(T1, LRUitem); + delLRU(T1); + cacheremove(LRUitem); + } + fi + :: /* Case B */ + ((lengthof(T1) + lengthof(B1)) < C) + -> + if + :: + ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) >= C) + -> + if + :: + ((lengthof(T1) + + lengthof(T2) + + lengthof(B1) + + lengthof(B2)) == (2 * C)) + -> + delLRU(B2); + :: + else + -> + skip; + fi + REPLACE(x_t, p); + :: + else + -> + skip; + fi + :: + else + -> + skip; + fi + cachefetch(x_t); + addMRU(T1, x_t); + fi + +} + +#if 0 /* Resolve this after modex extract foo */ +proctype p_arc(arc_item x_t) +{ + /* Serialise entry */ + mutex_enter(sc_lock); + + ARC(x_t); + + mutex_exit(sc_lock); +} +#endif diff -urN arc.null/arc.prx arc/arc.prx --- arc.null/arc.prx 1970-01-01 00:00:00.000000000 +0000 +++ arc/arc.prx 2023-09-07 17:35:35.607923403 +0000 @@ -0,0 +1,81 @@ +// Spin model extractor harness written by cherry +// +%F arc.c +%X -n REPLACE +%X -n ARC +%H +// Disable effects of all included files and try to implement a subset of the APIs they provide. +#define _ARC_H_ +%% +//%C // c_code {} +//%% +//%D // c_cdecl {} +//%% +%L +// We use spin primitives and data objects. +// See %P Below +NonState hidden _LRUitem +NonState hidden LRUitem +NonState hidden _B2 +NonState hidden B2 +NonState hidden _B1 +NonState hidden B1 +NonState hidden _T2 +NonState hidden T2 +NonState hidden _T1 +NonState hidden T1 +NonState hidden x_t + + + +assert(... keep +REPLACE(... keep +init_arc_item(... keep +lengthof(... keep +memberof(... keep +addMRU(... keep +readLRU(... keep +delLRU(... keep +delitem(... keep +cacheremove(... keep +cachefetch(... keep + + +Substitute c_expr { ((lengthof(T1)!=0)&&((lengthof(T1)>now.p)||(memberof(B2,x_t)&&(lengthof(T1)==now.p)))) } (lengthof(T1) != 0) && ((lengthof(T1) > p) || (memberof(B2, x_t) && (lengthof(T1) == p))) +Substitute c_code { now.d1=((lengthof(B1)>=lengthof(B2)) ? Int 1\n : (lengthof(B2)/lengthof(B1))); } d1 = ((lengthof(B1) >= lengthof(B2)) -> 1 : (lengthof(B2)/lengthof(B1))) +Substitute c_code { now.p=min((now.p+now.d1),C); } p = min((p + d1), C) + +Substitute c_code { now.d2=((lengthof(B2)>=lengthof(B1)) ? Int 1\n : (lengthof(B1)/lengthof(B2))); } d2 = ((lengthof(B2) >= lengthof(B1)) -> 1 : (lengthof(B1)/lengthof(B2))); +Substitute c_code { now.p=max((now.p-now.d2),0); } p = max(p - d2, 0); +Substitute c_expr { (!(((memberof(T1,x_t)||memberof(B1,x_t))||memberof(T2,x_t))||memberof(B2,x_t))) } !(memberof(T1, x_t) || memberof(B1, x_t) || memberof(T2, x_t) || memberof(B2, x_t)) +Substitute c_expr { ((lengthof(T1)+lengthof(B1))==C) } ((lengthof(T1) + lengthof(B1)) == C) +Substitute c_expr { (lengthof(T1)=C) } ((lengthof(T1) + lengthof(T2) + lengthof(B1) + lengthof(B2)) >= C) +Substitute c_expr { ((((lengthof(T1)+lengthof(T2))+lengthof(B1))+lengthof(B2))==(2*C)) } ((lengthof(T1) + lengthof(T2) + lengthof(B1) + lengthof(B2)) == (2 * C)) +%% + +%P +#define IID_INVAL -1 /* XXX: move to header ? */ + +/* Temp variable to hold LRU item */ +hidden arc_item LRUitem; + +arc_list B1, B2, T1, T2; + +#define p_REPLACE(_arg1, _arg2) REPLACE(_arg1, _arg2) /* Demo arbitrary Cfunc->PMLproc transformation */ +inline p_REPLACE(/* arc_item */ x_t, /* int */ p) +{ + +#include "_modex_REPLACE.pml" + +} + +#define p_ARC(_arg1) ARC(_arg1) +inline p_ARC(/* arc_item */ x_t) +{ + +#include "_modex_ARC.pml" + +} +%% \ No newline at end of file diff -urN arc.null/Makefile arc/Makefile --- arc.null/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ arc/Makefile 2023-09-08 10:32:11.650504807 +0000 @@ -0,0 +1,93 @@ +# This set of spinroot related files were written by cherry +# in the Gregorian Calendar year AD.2023, in the month +# of February that year. +# +# We have two specification files and a properties file +# +# The properties file contains "constraint" sections +# such as ltl or never claims (either or, not both). +# The specification is divided into two files: +# the file with suffix '.drv' is a "driver" which +# instantiates processes that will ultimately "drive" the +# models under test. +# The file with the suffix '.pml' contains the process +# model code, which, is intended to be the formal specification +# for the code we are interested in writing in C. +# +# We process these files in slightly different ways during +# the dev cycle, but broadly speaking, the idea is to create +# a file called 'spinmodel.pml' which contains the final +# model file that is fed to spin. +# +# Note that when we use the model extractor tool "modex" to +# extract the 'specification' from C code written to implement +# the model defined above. We use a 'harness' file (see file with +# suffix '.prx' below. +# +# Once the harness has been run, spinmodel.pml should be +# synthesised and processed as usual. +# +# The broad idea is that software dev starts by writing the spec +# first, validating the model, and then implementing the model in +# C, after which we come back to extract the model from the C file +# and cross check our implementation using spin. +# +# If things go well, the constraints specified in the '.ltl' file +# should hold exactly for both the handwritten model, and the +# extracted one. + +spin-gen: arc.pml arc.drv arc.inv + cp arc.pml model #mimic modex + cat arc.pmh model > spinmodel.pml;cat arc.drv >> spinmodel.pml;cat arc.inv >> spinmodel.pml; + spin -am spinmodel.pml + +spin-build: #Could be spin-gen or modex-gen + cc -DVECTORSZ=65536 -o pan pan.c + +all: spin-gen spin-build prog + +# Verification related targets. +spin-run: spin-build + ./pan -a #Generate arc.pml.trail on error + +# You run the trace only if the spin run above failed and created a trail +spin-trace: spinmodel.pml.trail + spin -t spinmodel.pml -p -g # -p (statements) -g (globals) -l (locals) -s (send) -r (recv) + ./pan -r spinmodel.pml.trail -g + +# Build the implementation +prog: arc.c arc.h + cc -g -o arc arc_drv.c arc.c + +# Modex Extracts from C code to 'model' - see arc.prx +# Unfortunately there doesn't seem to be a way to specify a filename to generate +modex-gen: arc.prx arc.c + modex -v -w arc.prx + cat arc.pmh model > spinmodel.pml;cat arc.drv >> spinmodel.pml;cat arc.inv >> spinmodel.pml; + spin -a spinmodel.pml #Sanity check + +# Housekeeping +modex-gen-clean: + rm -f spinmodel.pml # Our consolidated model file + rm -f _spin_nvr.tmp # Never claim file + rm -f model # modex generated intermediate "model" file + rm -f pan.* # Spin generated source files + rm -f _modex* # modex generated script files + rm -f *.I *.M + +prog-clean: + rm -f arc +spin-run-clean: + rm -f spinmodel.pml.trail + +spin-build-clean: + rm -f pan + +spin-gen-clean: + rm -f spinmodel.pml # Our consolidated model file + rm -f _spin_nvr.tmp # Never claim file + rm -f model # Intermediate "model" file + rm -f pan.* # Spin generated source files + +clean: modex-gen-clean spin-gen-clean spin-build-clean spin-run-clean prog-clean + rm -f *~ diff -urN arc.null/queue.h arc/queue.h --- arc.null/queue.h 1970-01-01 00:00:00.000000000 +0000 +++ arc/queue.h 2021-01-16 23:51:51.000000000 +0000 @@ -0,0 +1,655 @@ +/* $NetBSD: queue.h,v 1.76 2021/01/16 23:51:51 chs Exp $ */ + +/* + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + */ + +#ifndef _SYS_QUEUE_H_ +#define _SYS_QUEUE_H_ + +/* + * This file defines five types of data structures: singly-linked lists, + * lists, simple queues, tail queues, and circular queues. + * + * A singly-linked list is headed by a single forward pointer. The + * elements are singly linked for minimum space and pointer manipulation + * overhead at the expense of O(n) removal for arbitrary elements. New + * elements can be added to the list after an existing element or at the + * head of the list. Elements being removed from the head of the list + * should use the explicit macro for this purpose for optimum + * efficiency. A singly-linked list may only be traversed in the forward + * direction. Singly-linked lists are ideal for applications with large + * datasets and few or no removals or for implementing a LIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A simple queue is headed by a pair of pointers, one the head of the + * list and the other to the tail of the list. The elements are singly + * linked to save space, so elements can only be removed from the + * head of the list. New elements can be added to the list after + * an existing element, at the head of the list, or at the end of the + * list. A simple queue may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * For details on the use of these macros, see the queue(3) manual page. + */ + +/* + * Include the definition of NULL only on NetBSD because sys/null.h + * is not available elsewhere. This conditional makes the header + * portable and it can simply be dropped verbatim into any system. + * The caveat is that on other systems some other header + * must provide NULL before the macros can be used. + */ +#ifdef __NetBSD__ +#include +#endif + +#if defined(_KERNEL) && defined(DIAGNOSTIC) +#define QUEUEDEBUG 1 +#endif + +#if defined(QUEUEDEBUG) +# if defined(_KERNEL) +# define QUEUEDEBUG_ABORT(...) panic(__VA_ARGS__) +# else +# include +# define QUEUEDEBUG_ABORT(...) err(1, __VA_ARGS__) +# endif +#endif + +/* + * Singly-linked List definitions. + */ +#define SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List access methods. + */ +#define SLIST_FIRST(head) ((head)->slh_first) +#define SLIST_END(head) NULL +#define SLIST_EMPTY(head) ((head)->slh_first == NULL) +#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define SLIST_FOREACH(var, head, field) \ + for((var) = (head)->slh_first; \ + (var) != SLIST_END(head); \ + (var) = (var)->field.sle_next) + +#define SLIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = SLIST_FIRST((head)); \ + (var) != SLIST_END(head) && \ + ((tvar) = SLIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +/* + * Singly-linked List functions. + */ +#define SLIST_INIT(head) do { \ + (head)->slh_first = SLIST_END(head); \ +} while (/*CONSTCOND*/0) + +#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + (elm)->field.sle_next = (slistelm)->field.sle_next; \ + (slistelm)->field.sle_next = (elm); \ +} while (/*CONSTCOND*/0) + +#define SLIST_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.sle_next = (head)->slh_first; \ + (head)->slh_first = (elm); \ +} while (/*CONSTCOND*/0) + +#define SLIST_REMOVE_AFTER(slistelm, field) do { \ + (slistelm)->field.sle_next = \ + SLIST_NEXT(SLIST_NEXT((slistelm), field), field); \ +} while (/*CONSTCOND*/0) + +#define SLIST_REMOVE_HEAD(head, field) do { \ + (head)->slh_first = (head)->slh_first->field.sle_next; \ +} while (/*CONSTCOND*/0) + +#define SLIST_REMOVE(head, elm, type, field) do { \ + if ((head)->slh_first == (elm)) { \ + SLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = (head)->slh_first; \ + while(curelm->field.sle_next != (elm)) \ + curelm = curelm->field.sle_next; \ + curelm->field.sle_next = \ + curelm->field.sle_next->field.sle_next; \ + } \ +} while (/*CONSTCOND*/0) + + +/* + * List definitions. + */ +#define LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List access methods. + */ +#define LIST_FIRST(head) ((head)->lh_first) +#define LIST_END(head) NULL +#define LIST_EMPTY(head) ((head)->lh_first == LIST_END(head)) +#define LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define LIST_FOREACH(var, head, field) \ + for ((var) = ((head)->lh_first); \ + (var) != LIST_END(head); \ + (var) = ((var)->field.le_next)) + +#define LIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = LIST_FIRST((head)); \ + (var) != LIST_END(head) && \ + ((tvar) = LIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define LIST_MOVE(head1, head2, field) do { \ + LIST_INIT((head2)); \ + if (!LIST_EMPTY((head1))) { \ + (head2)->lh_first = (head1)->lh_first; \ + (head2)->lh_first->field.le_prev = &(head2)->lh_first; \ + LIST_INIT((head1)); \ + } \ +} while (/*CONSTCOND*/0) + +/* + * List functions. + */ +#if defined(QUEUEDEBUG) +#define QUEUEDEBUG_LIST_INSERT_HEAD(head, elm, field) \ + if ((head)->lh_first && \ + (head)->lh_first->field.le_prev != &(head)->lh_first) \ + QUEUEDEBUG_ABORT("LIST_INSERT_HEAD %p %s:%d", (head), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_LIST_OP(elm, field) \ + if ((elm)->field.le_next && \ + (elm)->field.le_next->field.le_prev != \ + &(elm)->field.le_next) \ + QUEUEDEBUG_ABORT("LIST_* forw %p %s:%d", (elm), \ + __FILE__, __LINE__); \ + if (*(elm)->field.le_prev != (elm)) \ + QUEUEDEBUG_ABORT("LIST_* back %p %s:%d", (elm), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_LIST_POSTREMOVE(elm, field) \ + (elm)->field.le_next = (void *)1L; \ + (elm)->field.le_prev = (void *)1L; +#else +#define QUEUEDEBUG_LIST_INSERT_HEAD(head, elm, field) +#define QUEUEDEBUG_LIST_OP(elm, field) +#define QUEUEDEBUG_LIST_POSTREMOVE(elm, field) +#endif + +#define LIST_INIT(head) do { \ + (head)->lh_first = LIST_END(head); \ +} while (/*CONSTCOND*/0) + +#define LIST_INSERT_AFTER(listelm, elm, field) do { \ + QUEUEDEBUG_LIST_OP((listelm), field) \ + if (((elm)->field.le_next = (listelm)->field.le_next) != \ + LIST_END(head)) \ + (listelm)->field.le_next->field.le_prev = \ + &(elm)->field.le_next; \ + (listelm)->field.le_next = (elm); \ + (elm)->field.le_prev = &(listelm)->field.le_next; \ +} while (/*CONSTCOND*/0) + +#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ + QUEUEDEBUG_LIST_OP((listelm), field) \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + (elm)->field.le_next = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &(elm)->field.le_next; \ +} while (/*CONSTCOND*/0) + +#define LIST_INSERT_HEAD(head, elm, field) do { \ + QUEUEDEBUG_LIST_INSERT_HEAD((head), (elm), field) \ + if (((elm)->field.le_next = (head)->lh_first) != LIST_END(head))\ + (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ + (head)->lh_first = (elm); \ + (elm)->field.le_prev = &(head)->lh_first; \ +} while (/*CONSTCOND*/0) + +#define LIST_REMOVE(elm, field) do { \ + QUEUEDEBUG_LIST_OP((elm), field) \ + if ((elm)->field.le_next != NULL) \ + (elm)->field.le_next->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = (elm)->field.le_next; \ + QUEUEDEBUG_LIST_POSTREMOVE((elm), field) \ +} while (/*CONSTCOND*/0) + +#define LIST_REPLACE(elm, elm2, field) do { \ + if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ + (elm2)->field.le_next->field.le_prev = \ + &(elm2)->field.le_next; \ + (elm2)->field.le_prev = (elm)->field.le_prev; \ + *(elm2)->field.le_prev = (elm2); \ + QUEUEDEBUG_LIST_POSTREMOVE((elm), field) \ +} while (/*CONSTCOND*/0) + +/* + * Simple queue definitions. + */ +#define SIMPLEQ_HEAD(name, type) \ +struct name { \ + struct type *sqh_first; /* first element */ \ + struct type **sqh_last; /* addr of last next element */ \ +} + +#define SIMPLEQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).sqh_first } + +#define SIMPLEQ_ENTRY(type) \ +struct { \ + struct type *sqe_next; /* next element */ \ +} + +/* + * Simple queue access methods. + */ +#define SIMPLEQ_FIRST(head) ((head)->sqh_first) +#define SIMPLEQ_END(head) NULL +#define SIMPLEQ_EMPTY(head) ((head)->sqh_first == SIMPLEQ_END(head)) +#define SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) + +#define SIMPLEQ_FOREACH(var, head, field) \ + for ((var) = ((head)->sqh_first); \ + (var) != SIMPLEQ_END(head); \ + (var) = ((var)->field.sqe_next)) + +#define SIMPLEQ_FOREACH_SAFE(var, head, field, next) \ + for ((var) = ((head)->sqh_first); \ + (var) != SIMPLEQ_END(head) && \ + ((next = ((var)->field.sqe_next)), 1); \ + (var) = (next)) + +/* + * Simple queue functions. + */ +#define SIMPLEQ_INIT(head) do { \ + (head)->sqh_first = NULL; \ + (head)->sqh_last = &(head)->sqh_first; \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ + (head)->sqh_last = &(elm)->field.sqe_next; \ + (head)->sqh_first = (elm); \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.sqe_next = NULL; \ + *(head)->sqh_last = (elm); \ + (head)->sqh_last = &(elm)->field.sqe_next; \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ + (head)->sqh_last = &(elm)->field.sqe_next; \ + (listelm)->field.sqe_next = (elm); \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_REMOVE_HEAD(head, field) do { \ + if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ + (head)->sqh_last = &(head)->sqh_first; \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_REMOVE_AFTER(head, elm, field) do { \ + if (((elm)->field.sqe_next = (elm)->field.sqe_next->field.sqe_next) \ + == NULL) \ + (head)->sqh_last = &(elm)->field.sqe_next; \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_REMOVE(head, elm, type, field) do { \ + if ((head)->sqh_first == (elm)) { \ + SIMPLEQ_REMOVE_HEAD((head), field); \ + } else { \ + struct type *curelm = (head)->sqh_first; \ + while (curelm->field.sqe_next != (elm)) \ + curelm = curelm->field.sqe_next; \ + if ((curelm->field.sqe_next = \ + curelm->field.sqe_next->field.sqe_next) == NULL) \ + (head)->sqh_last = &(curelm)->field.sqe_next; \ + } \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_CONCAT(head1, head2) do { \ + if (!SIMPLEQ_EMPTY((head2))) { \ + *(head1)->sqh_last = (head2)->sqh_first; \ + (head1)->sqh_last = (head2)->sqh_last; \ + SIMPLEQ_INIT((head2)); \ + } \ +} while (/*CONSTCOND*/0) + +#define SIMPLEQ_LAST(head, type, field) \ + (SIMPLEQ_EMPTY((head)) ? \ + NULL : \ + ((struct type *)(void *) \ + ((char *)((head)->sqh_last) - offsetof(struct type, field)))) + +/* + * Tail queue definitions. + */ +#define _TAILQ_HEAD(name, type, qual) \ +struct name { \ + qual type *tqh_first; /* first element */ \ + qual type *qual *tqh_last; /* addr of last next element */ \ +} +#define TAILQ_HEAD(name, type) _TAILQ_HEAD(name, struct type,) + +#define TAILQ_HEAD_INITIALIZER(head) \ + { TAILQ_END(head), &(head).tqh_first } + +#define _TAILQ_ENTRY(type, qual) \ +struct { \ + qual type *tqe_next; /* next element */ \ + qual type *qual *tqe_prev; /* address of previous next element */\ +} +#define TAILQ_ENTRY(type) _TAILQ_ENTRY(struct type,) + +/* + * Tail queue access methods. + */ +#define TAILQ_FIRST(head) ((head)->tqh_first) +#define TAILQ_END(head) (NULL) +#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) +#define TAILQ_LAST(head, headname) \ + (*(((struct headname *)(void *)((head)->tqh_last))->tqh_last)) +#define TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)(void *)((elm)->field.tqe_prev))->tqh_last)) +#define TAILQ_EMPTY(head) (TAILQ_FIRST(head) == TAILQ_END(head)) + + +#define TAILQ_FOREACH(var, head, field) \ + for ((var) = ((head)->tqh_first); \ + (var) != TAILQ_END(head); \ + (var) = ((var)->field.tqe_next)) + +#define TAILQ_FOREACH_SAFE(var, head, field, next) \ + for ((var) = ((head)->tqh_first); \ + (var) != TAILQ_END(head) && \ + ((next) = TAILQ_NEXT(var, field), 1); (var) = (next)) + +#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var) != TAILQ_END(head); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, prev) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var) != TAILQ_END(head) && \ + ((prev) = TAILQ_PREV((var), headname, field), 1); (var) = (prev)) + +/* + * Tail queue functions. + */ +#if defined(QUEUEDEBUG) +#define QUEUEDEBUG_TAILQ_INSERT_HEAD(head, elm, field) \ + if ((head)->tqh_first && \ + (head)->tqh_first->field.tqe_prev != &(head)->tqh_first) \ + QUEUEDEBUG_ABORT("TAILQ_INSERT_HEAD %p %s:%d", (head), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_TAILQ_INSERT_TAIL(head, elm, field) \ + if (*(head)->tqh_last != NULL) \ + QUEUEDEBUG_ABORT("TAILQ_INSERT_TAIL %p %s:%d", (head), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_TAILQ_OP(elm, field) \ + if ((elm)->field.tqe_next && \ + (elm)->field.tqe_next->field.tqe_prev != \ + &(elm)->field.tqe_next) \ + QUEUEDEBUG_ABORT("TAILQ_* forw %p %s:%d", (elm), \ + __FILE__, __LINE__); \ + if (*(elm)->field.tqe_prev != (elm)) \ + QUEUEDEBUG_ABORT("TAILQ_* back %p %s:%d", (elm), \ + __FILE__, __LINE__); +#define QUEUEDEBUG_TAILQ_PREREMOVE(head, elm, field) \ + if ((elm)->field.tqe_next == NULL && \ + (head)->tqh_last != &(elm)->field.tqe_next) \ + QUEUEDEBUG_ABORT("TAILQ_PREREMOVE head %p elm %p %s:%d",\ + (head), (elm), __FILE__, __LINE__); +#define QUEUEDEBUG_TAILQ_POSTREMOVE(elm, field) \ + (elm)->field.tqe_next = (void *)1L; \ + (elm)->field.tqe_prev = (void *)1L; +#else +#define QUEUEDEBUG_TAILQ_INSERT_HEAD(head, elm, field) +#define QUEUEDEBUG_TAILQ_INSERT_TAIL(head, elm, field) +#define QUEUEDEBUG_TAILQ_OP(elm, field) +#define QUEUEDEBUG_TAILQ_PREREMOVE(head, elm, field) +#define QUEUEDEBUG_TAILQ_POSTREMOVE(elm, field) +#endif + +#define TAILQ_INIT(head) do { \ + (head)->tqh_first = TAILQ_END(head); \ + (head)->tqh_last = &(head)->tqh_first; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_INSERT_HEAD(head, elm, field) do { \ + QUEUEDEBUG_TAILQ_INSERT_HEAD((head), (elm), field) \ + if (((elm)->field.tqe_next = (head)->tqh_first) != TAILQ_END(head))\ + (head)->tqh_first->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (head)->tqh_first = (elm); \ + (elm)->field.tqe_prev = &(head)->tqh_first; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_INSERT_TAIL(head, elm, field) do { \ + QUEUEDEBUG_TAILQ_INSERT_TAIL((head), (elm), field) \ + (elm)->field.tqe_next = TAILQ_END(head); \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &(elm)->field.tqe_next; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + QUEUEDEBUG_TAILQ_OP((listelm), field) \ + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != \ + TAILQ_END(head)) \ + (elm)->field.tqe_next->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (listelm)->field.tqe_next = (elm); \ + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + QUEUEDEBUG_TAILQ_OP((listelm), field) \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + (elm)->field.tqe_next = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ +} while (/*CONSTCOND*/0) + +#define TAILQ_REMOVE(head, elm, field) do { \ + QUEUEDEBUG_TAILQ_PREREMOVE((head), (elm), field) \ + QUEUEDEBUG_TAILQ_OP((elm), field) \ + if (((elm)->field.tqe_next) != TAILQ_END(head)) \ + (elm)->field.tqe_next->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ + QUEUEDEBUG_TAILQ_POSTREMOVE((elm), field); \ +} while (/*CONSTCOND*/0) + +#define TAILQ_REPLACE(head, elm, elm2, field) do { \ + if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != \ + TAILQ_END(head)) \ + (elm2)->field.tqe_next->field.tqe_prev = \ + &(elm2)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm2)->field.tqe_next; \ + (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ + *(elm2)->field.tqe_prev = (elm2); \ + QUEUEDEBUG_TAILQ_POSTREMOVE((elm), field); \ +} while (/*CONSTCOND*/0) + +#define TAILQ_CONCAT(head1, head2, field) do { \ + if (!TAILQ_EMPTY(head2)) { \ + *(head1)->tqh_last = (head2)->tqh_first; \ + (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ + (head1)->tqh_last = (head2)->tqh_last; \ + TAILQ_INIT((head2)); \ + } \ +} while (/*CONSTCOND*/0) + +/* + * Singly-linked Tail queue declarations. + */ +#define STAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first; /* first element */ \ + struct type **stqh_last; /* addr of last next element */ \ +} + +#define STAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first } + +#define STAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue access methods. + */ +#define STAILQ_FIRST(head) ((head)->stqh_first) +#define STAILQ_END(head) NULL +#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) +#define STAILQ_EMPTY(head) (STAILQ_FIRST(head) == STAILQ_END(head)) + +/* + * Singly-linked Tail queue functions. + */ +#define STAILQ_INIT(head) do { \ + (head)->stqh_first = NULL; \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (/*CONSTCOND*/0) + +#define STAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (head)->stqh_first = (elm); \ +} while (/*CONSTCOND*/0) + +#define STAILQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.stqe_next = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &(elm)->field.stqe_next; \ +} while (/*CONSTCOND*/0) + +#define STAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.stqe_next = (listelm)->field.stqe_next) == NULL)\ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (listelm)->field.stqe_next = (elm); \ +} while (/*CONSTCOND*/0) + +#define STAILQ_REMOVE_HEAD(head, field) do { \ + if (((head)->stqh_first = (head)->stqh_first->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (/*CONSTCOND*/0) + +#define STAILQ_REMOVE(head, elm, type, field) do { \ + if ((head)->stqh_first == (elm)) { \ + STAILQ_REMOVE_HEAD((head), field); \ + } else { \ + struct type *curelm = (head)->stqh_first; \ + while (curelm->field.stqe_next != (elm)) \ + curelm = curelm->field.stqe_next; \ + if ((curelm->field.stqe_next = \ + curelm->field.stqe_next->field.stqe_next) == NULL) \ + (head)->stqh_last = &(curelm)->field.stqe_next; \ + } \ +} while (/*CONSTCOND*/0) + +#define STAILQ_FOREACH(var, head, field) \ + for ((var) = ((head)->stqh_first); \ + (var); \ + (var) = ((var)->field.stqe_next)) + +#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = STAILQ_FIRST((head)); \ + (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define STAILQ_CONCAT(head1, head2) do { \ + if (!STAILQ_EMPTY((head2))) { \ + *(head1)->stqh_last = (head2)->stqh_first; \ + (head1)->stqh_last = (head2)->stqh_last; \ + STAILQ_INIT((head2)); \ + } \ +} while (/*CONSTCOND*/0) + +#define STAILQ_LAST(head, type, field) \ + (STAILQ_EMPTY((head)) ? \ + NULL : \ + ((struct type *)(void *) \ + ((char *)((head)->stqh_last) - offsetof(struct type, field)))) + +#endif /* !_SYS_QUEUE_H_ */ From nobody Fri Sep 8 15:06:17 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Rhzw52W7rz4sLvc; Fri, 8 Sep 2023 15:06:29 +0000 (UTC) (envelope-from freebsd@igalic.co) Received: from mail-4018.proton.ch (mail-4018.proton.ch [185.70.40.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "protonmail.com", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Rhzw31KHDz3VNp; Fri, 8 Sep 2023 15:06:27 +0000 (UTC) (envelope-from freebsd@igalic.co) Authentication-Results: mx1.freebsd.org; dkim=pass header.d=igalic.co header.s=protonmail2 header.b=AvtwKLFk; spf=pass (mx1.freebsd.org: domain of freebsd@igalic.co designates 185.70.40.18 as permitted sender) smtp.mailfrom=freebsd@igalic.co; dmarc=none Date: Fri, 08 Sep 2023 15:06:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=igalic.co; s=protonmail2; t=1694185583; x=1694444783; bh=aq38UxGIxG6IEF9Ta/sqeVo3H6vFhg9u49aJCSUoYMo=; h=Date:To:From:Subject:Message-ID:Feedback-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=AvtwKLFkOAs5Oa8lJlSXIwZI126eLpxpfzSqgmCfvO+g3E8xTwM2Zyl8m50cKaNJ5 4r8ARsKo4PcQnw/RleR3XwV8pgv3L3g2z5BhMLiyDpOmyu/nxm5qR1ImwMwDqEkh/Q EJ0QmPvlL2wvBX/eOVBxFbr8Icd1RJnHP2RM/Id0PdiQmelE+z/DzXunhfZeRGNH8g k1YOKL5u0cldU7LI4UDvKN+gEJ4/jmHNFtjyzrX4njEVUelTkpopTOwEFuGBEeahd8 2FzmZ12iFFbmSY1u3nAnigecv/0ibJ37p17wDxhSO0VgmmH3Mmbf4u7O0X6nM5hWrD 4zohl9RuOPc7A== To: freebsd-hackers , "freebsd-virtualization@FreeBSD.org" From: =?utf-8?Q?Mina_Gali=C4=87?= Subject: Question about virtio_alloc_virtqueues Message-ID: Feedback-ID: 66573723:user:proton List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spamd-Bar: --- X-Spamd-Result: default: False [-3.07 / 15.00]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-1.000]; R_MIXED_CHARSET(0.83)[subject]; RWL_MAILSPIKE_EXCELLENT(-0.40)[185.70.40.18:from]; R_DKIM_ALLOW(-0.20)[igalic.co:s=protonmail2]; R_SPF_ALLOW(-0.20)[+ip4:185.70.40.0/24]; MIME_GOOD(-0.10)[text/plain]; MLMMJ_DEST(0.00)[freebsd-hackers@freebsd.org,freebsd-virtualization@FreeBSD.org]; RCVD_COUNT_ZERO(0.00)[0]; MIME_TRACE(0.00)[0:+]; FROM_EQ_ENVFROM(0.00)[]; RCPT_COUNT_TWO(0.00)[2]; TO_DN_EQ_ADDR_SOME(0.00)[]; ASN(0.00)[asn:62371, ipnet:185.70.40.0/24, country:CH]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; DKIM_TRACE(0.00)[igalic.co:+]; TO_DN_SOME(0.00)[]; DMARC_NA(0.00)[igalic.co]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MID_RHS_MATCH_FROM(0.00)[] X-Rspamd-Queue-Id: 4Rhzw31KHDz3VNp Hi folks, for the past two or so weeks, I've been trying to document the virtio functions: You can see some of my progress here: https://codeberg.org/meena/freebsd-src/commits/branch/improve/virtio I'm currently trying to document virtio_alloc_virtqueues. The second argument, flags, is only ever called with 0, and never passed on to anything. So I thought I'd remove it. However, there *is* this comment in if_vtnet.c: =09/* =09 * TODO: Enable interrupt binding if this is multiqueue. This will =09 * only matter when per-virtqueue MSIX is available. =09 */ =09if (sc->vtnet_flags & VTNET_FLAG_MQ) =09=09flags |=3D 0; after which flags are still set to 0. for now?? What does this mean? Kind regards, Mina Gali=C4=87 From nobody Sat Sep 9 10:53:01 2023 X-Original-To: freebsd-hackers@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RjVFP5lvpz4sxNV; Sat, 9 Sep 2023 10:53:13 +0000 (UTC) (envelope-from vmaffione@freebsd.org) Received: from smtp.freebsd.org (smtp.freebsd.org [96.47.72.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "smtp.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RjVFP5JrNz3bgZ; Sat, 9 Sep 2023 10:53:13 +0000 (UTC) (envelope-from vmaffione@freebsd.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1694256793; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=pExO+lt8UHmK0kjUOnu0vVtEyLRQxvtCu3q+Tjnt/CU=; b=FIv2Paie/wYW9ptwp7jy0HuJa6IzyE4wUNSu8P0TmpT23FO88DQutR2OuBcLD+r+BrL/kd KC4aZ4EfvomYljt/XiC7Gn5+jTOxNBYzb1UAt5KgCv4zKQVhFYRzNMfWp6m1TFa4ycfZe1 3Y3sTn6r+sex5yEsvloLmc8l+5LMTwm4JIYmyznC9XET8RAORIgLcgHQ27xWEIVKhyjrr/ L5KK147q/pp62XvETlR1ZVucE4I4eVUNgrnVdKnjBs7nmeClnk89g7n88ISHtrXNSbEzIO yRkiGynQVK+fD5OQppQhYiRshNV0NDBwDtBswOi+CNKtOOTpfZDqfzjIKfGs9w== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1694256793; a=rsa-sha256; cv=none; b=pIkn/SOImdB7IyCUFa1M3ChfOWtXTEfU5462mZ1QNfJoZ6hFEvI59aNVlKGay646CC42CJ h9v5rvP+LYK8EDRHV/JXyCV9klmf0nK2oWEoWKn6fYdCuxQdbODigWqKmKBKusP6zINaHc GQLTE8BuAAszAzZqegc4fObCD5nDxmTDpzsJRLyBsOSjYTOQ4sV9j8b9d9suoecClx2Vkc H1EP/7cPFi+ZZqMdLYzuDuI/r8gDuY6Db3K9kaUgX+6JDmal1ciBVtw6iSxQ2p8g/UAJ3z bGt6OCmGdy4Q3Jzw3GcqIHMwC49x+PTY6fYSBNLm70V7OFFJauKuHgutkMT8tw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1694256793; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=pExO+lt8UHmK0kjUOnu0vVtEyLRQxvtCu3q+Tjnt/CU=; b=A8vroCiEW2k9xY6tFRqrPazTZJLYsWeScbohnfn/bKBD3R09bDOxF8KLt5rfYn3+mLRQX9 ndRxwkEE5dFX0Zv0G62BDnlsqIT0w8YQ/28pUsL3C9cocSRO7bu1vq2fSPxFAty/zsxky/ h8609RWxIUhC9qzjHFIVo2kgUJUxWs8X1aBP+v2V7MVQGYAdy2t5T+2hvx2P+1BGs3NKho 4adtQ9AsZ1nGSMqzuzz4uRsnHHNmXhRMuTxU4gA33snNrvV21o2/PTs/lLMnxyLspvX/sz VbJmaz7D7fDT2S6zDcKg1ZsuiO45VqCj9CQNgUQLDOf8xw6CmLhAy3InmGvhLQ== Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) (Authenticated sender: vmaffione) by smtp.freebsd.org (Postfix) with ESMTPSA id 4RjVFP4FSCz13ZX; Sat, 9 Sep 2023 10:53:13 +0000 (UTC) (envelope-from vmaffione@freebsd.org) Received: by mail-pj1-f48.google.com with SMTP id 98e67ed59e1d1-26d0d376ec7so2232334a91.2; Sat, 09 Sep 2023 03:53:13 -0700 (PDT) X-Gm-Message-State: AOJu0YxcGvqP/pzEUxDbThuSFlq1CLRBHykRSpJ1ZNXMxb1AgBpNKPLB OVFWnLpvuxLe0AwZqZAuitO5cFW87GqdjS0ll28= X-Google-Smtp-Source: AGHT+IHWQ3ufNTrDziqMyUjhpaZg9HYDJRQX1akkIzQFQxGTbCm8AJTyOayShiYr7/MZdFQKMLgzHEF4bi+s89OlVfQ= X-Received: by 2002:a17:90a:660f:b0:267:909f:3719 with SMTP id l15-20020a17090a660f00b00267909f3719mr4884793pjj.19.1694256792512; Sat, 09 Sep 2023 03:53:12 -0700 (PDT) List-Id: Technical discussions relating to FreeBSD List-Archive: https://lists.freebsd.org/archives/freebsd-hackers List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-hackers@freebsd.org MIME-Version: 1.0 References: In-Reply-To: From: Vincenzo Maffione Date: Sat, 9 Sep 2023 12:53:01 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: Question about virtio_alloc_virtqueues To: =?UTF-8?Q?Mina_Gali=C4=87?= Cc: freebsd-hackers , "freebsd-virtualization@FreeBSD.org" Content-Type: multipart/alternative; boundary="00000000000046b0630604eae632" --00000000000046b0630604eae632 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi, Looking at the code, it looks like that comment was written at a time where per-virtqueue MSIX interrupts were not available, and virtio_alloc_virtqueues() API was already designed to receive a flag to indicate that per-virtqueue MSIX interrupts were requested. The code you quoted would likely have been a simple placeholder, to be replaced with something like "flags |=3D VIRTIO_PERVQ_INTR" once the support had come. It= 's a very common pattern to start with setting flags =3D 0, and then bitwise o= r |=3D flags depending on the situation. However: - per-virtqueue MSIX interrupts are now available (e.g. look at vtpci_setup_interrupts()), and - virtiqueues interrupt setup happens in a separate API, i.e. virtio_setup_intr(), which takes care all the possible cases So as far as I can tell that comment is not relevant anymore and can be removed together with the flags. Unless I'm wrong, ofc. Cheers, Vincenzo Il giorno ven 8 set 2023 alle ore 21:05 Mina Gali=C4=87 = ha scritto: > Hi folks, > > for the past two or so weeks, I've been trying to document the > virtio functions: You can see some of my progress here: > > https://codeberg.org/meena/freebsd-src/commits/branch/improve/virtio > > I'm currently trying to document virtio_alloc_virtqueues. > The second argument, flags, is only ever called with 0, and > never passed on to anything. So I thought I'd remove it. > However, there *is* this comment in if_vtnet.c: > > /* > * TODO: Enable interrupt binding if this is multiqueue. This wil= l > * only matter when per-virtqueue MSIX is available. > */ > if (sc->vtnet_flags & VTNET_FLAG_MQ) > flags |=3D 0; > > > after which flags are still set to 0. for now?? > What does this mean? > > Kind regards, > > Mina Gali=C4=87 > > --00000000000046b0630604eae632 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi,
=C2=A0 Looking at the code, it looks li= ke that comment was written at a time where per-virtqueue MSIX interrupts w= ere not available, and virtio_alloc_virtqueues() API was already designed t= o receive a flag to indicate that per-virtqueue MSIX interrupts were reques= ted. The code you quoted would likely have been a simple placeholder, to be= replaced with something like "flags |=3D VIRTIO_PERVQ_INTR" once= the support had come. It's a very common pattern to start with setting= flags =3D 0, and then bitwise or |=3D flags depending on the situation.

However:
  • per-virtqueue MSIX in= terrupts are now available (e.g. look at vtpci_setup_interrupts()), and
  • virtiqueues interrupt setup happens in a separate API, i.e. virtio_set= up_intr(), which takes care all the possible cases
So as = far as I can tell that comment is not relevant anymore and can be removed t= ogether with the flags.
Unless I'm wrong, ofc.
=
Cheers,
=C2=A0 Vincenzo

<= div class=3D"gmail_quote">
Il giorno v= en 8 set 2023 alle ore 21:05 Mina Gali=C4=87 <freebsd@igalic.co> ha scritto:
Hi folks,

for the past two or so weeks, I've been trying to document the
virtio functions: You can see some of my progress here:

https://codeberg.org/meena/freeb= sd-src/commits/branch/improve/virtio

I'm currently trying to document virtio_alloc_virtqueues.
The second argument, flags, is only ever called with 0, and
never passed on to anything. So I thought I'd remove it.
However, there *is* this comment in if_vtnet.c:

=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* TODO: Enable interrupt binding if this = is multiqueue. This will
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* only matter when per-virtqueue MSIX is = available.
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (sc->vtnet_flags & VTNET_FLAG_MQ)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 flags |=3D 0;


after which flags are still set to 0. for now??
What does this mean?

Kind regards,

Mina Gali=C4=87

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