Date: Fri, 8 Sep 2023 17:48:59 -0400 From: LuMiWa <lumiwa@dismail.de> To: FreeBSD Questions <freebsd-questions@freebsd.org> Subject: cp-microcode Message-ID: <20230908174859.67856bd8@dismail.de>
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[-- Attachment #1 --]
H!
Few day ago was update for cp-microcode. I have AMD cpu. Can I delete
cpu-microcode-intel and devcpu-data?
For now my settings are:
/boot/loader.conf :
cpu_microcode_load="YES"
cpu_microcode_name="/usr/local/share/cpucontrol/microcode_amd.bin
and in /etc/rc.conf:
microcode_update_enable="YES"
Are settings without devcpu-data different, please?
Today I ran x86info -a. Please, check attach results.
There are some errors which I do not understand.
Thank you.
lumiwa
--
“Life shrinks or expands in proportion to one's courage.”
― Anais Nin
[-- Attachment #2 --]
x86info v1.31pre
MP Configuration Table Header MISSING!
Found 8 identical CPUsMP Configuration Table Header MISSING!
Extended Family: 8 Extended Model: 1 Family: 15 Model: 24 Stepping: 1
CPU Model (x86info's best guess): Unknown CPU 0x810f81
Processor name string (BIOS programmed): AMD Ryzen 5 PRO 3500U w/ Radeon Vega Mobile Gfx
Number of reporting banks : 7
MCG_CTL:
Data cache check enabled
ECC 1 bit error reporting enabled
ECC multi bit error reporting enabled
Data cache data parity enabled
Data cache main tag parity enabled
Data cache snoop tag parity enabled
L1 TLB parity enabled
L2 TLB parity enabled
Instruction cache check enabled
ECC 1 bit error reporting enabled
ECC multi bit error reporting enabled
Instruction cache data parity enabled
IC main tag parity enabled
IC snoop tag parity enabled
L1 TLB parity enabled
L2 TLB parity enabled
Predecode array parity enabled
Target selector parity enabled
Read data error enabled
Bus unit check enabled
External L2 tag parity error enabled
L2 partial tag parity error enabled
System ECC TLB reload error enabled
L2 ECC TLB reload error enabled
L2 ECC K7 deallocate disabled
L2 ECC probe deallocate disabled
System datareaderror reporting disabled
Load/Store unit check enabled
Read data error enable (loads) enabled
Read data error enable (stores) enabled
31 23 15 7
Bank: 0 (0x400)
MC0CTL: 00000000 00011111 11111111 11111111
MC0STATUS: 00000000 00000000 00000000 00000000
MC0ADDR: 00000000 00000000 00000000 00000000
MC0MISC: 00000000 00000000 00000000 00000000
Bank: 1 (0x404)
MC1CTL: 00000000 00000000 00111111 11111111
MC1STATUS: 00000000 00000000 00000000 00000000
MC1ADDR: 00000000 00000000 00000000 00000000
MC1MISC: 00000000 00000000 00000000 00000000
Bank: 2 (0x408)
MC2CTL: 00000000 00000000 00000000 00001111
MC2STATUS: 00000000 00000000 00000000 00000000
MC2ADDR: 00000000 00000000 00000000 00000000
MC2MISC: 00000000 00000000 00000000 00000000
Bank: 3 (0x40c)
MC3CTL: 00000000 00000000 00000001 11111111
MC3STATUS: 00000000 00000000 00000000 00000000
MC3ADDR: 00000000 00000000 00000000 00000000
MC3MISC: 00000000 00000000 00000000 00000000
Bank: 4 (0x410)
MC4CTL: 00000000 00000000 00000000 00000000
MC4STATUS: 00000000 00000000 00000000 00000000
MC4ADDR: 00000000 00000000 00000000 00000000
MC4MISC: 00000000 00000000 00000000 00000000
Bank: 5 (0x414)
MC5CTL: 00000000 00000000 00000111 11111111
MC5STATUS: 00000000 00000000 00000000 00000000
MC5ADDR: 00000000 00000000 00000000 00000000
MC5MISC: 00000000 00000000 00000000 00000000
Bank: 6 (0x418)
MC6CTL: 00000000 00000000 00000000 01111111
MC6STATUS: 00000000 00000000 00000000 00000000
MC6ADDR: 00000000 00000000 00000000 00000000
MC6MISC: 00000000 00000000 00000000 00000000
Microcode patch level: 0x8108102
PowerNOW! Technology information
Available features:
Temperature sensing diode present.
Thermal Trip
Thermal Monitoring
Hardware P-state control
invariant TSC
read-only Effective Frequency Interface
Effective Frequency Interface
Pstate-P0: 2850MHz (current)
Pstate-P1: 2700MHz
Pstate-P2: 2500MHz
Monitor/Mwait: min/max line size 64/64, ecx bit 0 support, enumeration extension
SVM: revision 1, 32768 ASIDs, np, lbrVirt, SVMLock, NRIPSave, TscRateMsr, VmcbClean, FlushByAsid, DecodeAssists, PauseFilter, PauseFilterThreshold
Address Size: 48 bits virtual, 48 bits physical
The physical package has 8 of 16 possible cores implemented.
eax in: 0x00000000, eax = 0000000d ebx = 68747541 ecx = 444d4163 edx = 69746e65
eax in: 0x00000001, eax = 00810f81 ebx = 00080800 ecx = 7ed8320b edx = 178bfbff
eax in: 0x00000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x00000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x00000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x00000005, eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00000011
eax in: 0x00000006, eax = 00000004 ebx = 00000000 ecx = 00000001 edx = 00000000
eax in: 0x00000007, eax = 00000000 ebx = 209c01a9 ecx = 00000000 edx = 00000000
eax in: 0x00000008, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x00000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x0000000a, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x0000000b, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x0000000c, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x0000000d, eax = 00000007 ebx = 00000340 ecx = 00000340 edx = 00000000
eax in: 0x80000000, eax = 8000001f ebx = 68747541 ecx = 444d4163 edx = 69746e65
eax in: 0x80000001, eax = 00810f81 ebx = 00000000 ecx = 35c233ff edx = 2fd3fbff
eax in: 0x80000002, eax = 20444d41 ebx = 657a7952 ecx = 2035206e edx = 204f5250
eax in: 0x80000003, eax = 30303533 ebx = 2f772055 ecx = 64615220 edx = 206e6f65
eax in: 0x80000004, eax = 61676556 ebx = 626f4d20 ecx = 20656c69 edx = 00786647
eax in: 0x80000005, eax = ff40ff40 ebx = ff40ff40 ecx = 20080140 edx = 40040140
eax in: 0x80000006, eax = 26006400 ebx = 66006400 ecx = 02006140 edx = 00208140
eax in: 0x80000007, eax = 00000000 ebx = 0000001b ecx = 00000000 edx = 00006599
eax in: 0x80000008, eax = 00003030 ebx = 00001007 ecx = 00004007 edx = 00000000
eax in: 0x80000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x8000000a, eax = 00000001 ebx = 00008000 ecx = 00000000 edx = 0001bcff
eax in: 0x8000000b, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x8000000c, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x8000000d, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x8000000e, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x8000000f, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000010, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000011, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000012, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000013, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000014, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000015, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000016, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000017, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000018, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000019, eax = f040f040 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x8000001a, eax = 00000003 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x8000001b, eax = 000003ff ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x8000001c, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x8000001d, eax = 00004121 ebx = 01c0003f ecx = 0000003f edx = 00000000
eax in: 0x8000001e, eax = 00000000 ebx = 00000100 ecx = 00000000 edx = 00000000
eax in: 0x8000001f, eax = 0000000f ebx = 0000016f ecx = 0000000f edx = 00000000
L1 Data TLB (1G): Fully associative. 64 entries.
L1 Instruction TLB (1G): Fully associative. 64 entries.
L1 Data TLB (2M/4M): Fully associative. 64 entries.
L1 Instruction TLB (2M/4M): Fully associative. 64 entries.
L1 Data TLB (4K): Fully associative. 64 entries.
L1 Instruction TLB (4K): Fully associative. 64 entries.
L1 Data cache:
Size: 32Kb 8-way associative.
lines per tag=1 line size=64 bytes.
L1 Instruction cache:
Size: 64Kb 4-way associative.
lines per tag=1 line size=64 bytes.
L2 Data TLB (1G): Disabled. 0 entries.
L2 Instruction TLB (1G): Disabled. 0 entries.
L2 Data TLB (2M/4M): 2-way associative. 1536 entries.
L2 Instruction TLB (2M/4M): 8-way associative. 1024 entries.
L2 Data TLB (4K): 8-way associative. 1536 entries.
L2 Instruction TLB (4K): 8-way associative. 1024 entries.
L2 cache:
Size: 512Kb 8-way associative.
lines per tag=1 line size=64 bytes.
Feature flags:
fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh mmx fxsr sse sse2 ht sse3 pclmulqdq mwait ssse3 fma cmpxchg16b sse4_1 sse4_2 [1:ecx:22] popcnt aes xsave osxsave avx f16c [1:ecx:30]
Extended feature flags:
fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 nx mmxext mmx fxsr ffxsr page1gb rdtscp lm lahf/sahf CmpLegacy svm ExtApicSpace LockMovCr0 abm sse4a misalignsse 3dnowPref osvw skinit wdt tce TopoExt PerfCtrExtCore PerfCtrExtNB [80000001:ecx:26] [80000001:ecx:28] [80000001:ecx:29]
Long NOPs supported: yes
MTRR registers:
MTRRcap (0xfe): 0x0000000000000508 wc:1 fix:1 vcnt:8
MTRRphysBase0 (0x200): 0x0000000000000006 (physbase:0x000000 type: 0x06 (write-back))
MTRRphysMask0 (0x201): 0x0000ffff80000800 (physmask:0xf80000 valid:1)
MTRRphysBase1 (0x202): 0x0000000080000006 (physbase:0x080000 type: 0x06 (write-back))
MTRRphysMask1 (0x203): 0x0000ffffc0000800 (physmask:0xfc0000 valid:1)
MTRRphysBase2 (0x204): 0x00000000ff000005 (physbase:0x0ff000 type: 0x05 (write-protect))
MTRRphysMask2 (0x205): 0x0000ffffff000800 (physmask:0xfff000 valid:1)
MTRRphysBase3 (0x206): 0x00000000bf000000 (physbase:0x0bf000 type: 0x00 (uncacheable))
MTRRphysMask3 (0x207): 0x0000ffffff000800 (physmask:0xfff000 valid:1)
MTRRphysBase4 (0x208): 0x0000000000000000 (physbase:0x000000 type: 0x00 (uncacheable))
MTRRphysMask4 (0x209): 0x0000000000000000 (physmask:0x000000 valid:0)
MTRRphysBase5 (0x20a): 0x0000000000000000 (physbase:0x000000 type: 0x00 (uncacheable))
MTRRphysMask5 (0x20b): 0x0000000000000000 (physmask:0x000000 valid:0)
MTRRphysBase6 (0x20c): 0x0000000000000000 (physbase:0x000000 type: 0x00 (uncacheable))
MTRRphysMask6 (0x20d): 0x0000000000000000 (physmask:0x000000 valid:0)
MTRRphysBase7 (0x20e): 0x0000000000000000 (physbase:0x000000 type: 0x00 (uncacheable))
MTRRphysMask7 (0x20f): 0x0000000000000000 (physmask:0x000000 valid:0)
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0505050505050505
MTRRfix4K_D0000 0x26a: 0x0505050505050505
MTRRfix4K_D8000 0x26b: 0x0505050505050505
MTRRfix4K_E0000 0x26c: 0x0505050505050505
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c00 (fixed-range flag:1 enable flag:1 default type:0x00 (uncacheable))
APIC registers:
APIC MSR Base(0x1b): : 0x00000000fee00900
APIC Local ID : 0x00000000
APIC Local Version : 0x80050010
APIC Task Priority : 0x00000000
APIC Arbitration Priority : 0x00000000
APIC Processor Priority : 0x00000000
APIC EOI : 0x00000000
APIC Remote Read : 0x00000000
APIC Logical Destination : 0x00000000
APIC Destination Format : 0xffffffff
APIC Spurious Interrupt Vector : 0x000001ff
APIC In-Service (ISR0) : 0x00000000
APIC In-Service (ISR1) : 0x00000000
APIC In-Service (ISR2) : 0x00000000
APIC In-Service (ISR3) : 0x00000000
APIC In-Service (ISR4) : 0x00000000
APIC In-Service (ISR5) : 0x00000000
APIC In-Service (ISR6) : 0x00000000
APIC In-Service (ISR7) : 0x00000000
APIC Trigger Mode (TMR0) : 0x00000000
APIC Trigger Mode (TMR1) : 0x00010000
APIC Trigger Mode (TMR2) : 0x00000000
APIC Trigger Mode (TMR3) : 0x00000000
APIC Trigger Mode (TMR4) : 0x00000000
APIC Trigger Mode (TMR5) : 0x00000000
APIC Trigger Mode (TMR6) : 0x00000000
APIC Trigger Mode (TMR7) : 0x00000000
APIC Interrupt Request (IRR00) : 0x00000000
APIC Interrupt Request (IRR01) : 0x00000000
APIC Interrupt Request (IRR02) : 0x00000000
APIC Interrupt Request (IRR03) : 0x00000000
APIC Interrupt Request (IRR04) : 0x00000000
APIC Interrupt Request (IRR05) : 0x00000000
APIC Interrupt Request (IRR06) : 0x00000000
APIC Interrupt Request (IRR07) : 0x00000000
APIC Error Status : 0x00000080
APIC LVT CMCI : 0x00000000
APIC Interrupt Command (ICR0) : 0x000040f8
APIC Interrupt Command (ICR1) : 0x06000000
APIC LVT Timer : 0x000000ef
APIC Thermal Sensor : 0x00010000
APIC LVT Performance Monitoring Counters: 0x00010400
APIC LVT LINT0 : 0x00010700
APIC LVT LINT1 : 0x00000400
APIC LVT Error : 0x000000f0
APIC Initial Count (for Timer) : 0x00001296
APIC Current Count (for Timer) : 0x000001e4
APIC Divide Configuration (for Timer) : 0x00000000
Address sizes : 48 bits physical, 48 bits virtual
2.10GHz processor (estimate).
running at an estimated 2.10GHz
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