Date: Sun, 11 Jun 2023 01:17:57 +0100 From: Jessica Clarke <jrtc27@freebsd.org> To: S JG <sean.jensengrey@gmail.com> Cc: freebsd-riscv@freebsd.org Subject: Re: 64 core RISCV board program from riscv.org Message-ID: <22FB61E7-F3B2-4FEA-A8DA-10732EF7DB34@freebsd.org> In-Reply-To: <CAPZ0BvfDB203=D44bb8VHq6f19PJojfvvJcwn=Q5W1ucEOEsNA@mail.gmail.com> References: <CAPZ0BvfDB203=D44bb8VHq6f19PJojfvvJcwn=Q5W1ucEOEsNA@mail.gmail.com>
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On 11 Jun 2023, at 00:34, S JG <sean.jensengrey@gmail.com> wrote: >=20 > The RISC-V Intl has a program to get dev boards for OSS developers.=20 >=20 > https://riscv.org/risc-v-developer-boards/details/ >=20 > And they are offering up a "Pioneer Box from Milk" which contains a 64 = core RISCV CPU from Sophon. These are Thead C920 cores. >=20 > https://milkv.io/pioneer >=20 > https://en.sophgo.com/product/introduce/sg2042.html=20 >=20 > Looks like an ideal dev/test/build platform to support FreeBSD. >=20 > Apparently the C920 is nearly identical to the C910 (which is Open = Source) >=20 > https://www.t-head.cn/product/c910?lang=3Den >=20 > https://github.com/T-head-Semi/openc910 >=20 > = https://img.102.alibaba.com/1627958419409/49652c9412c41cb6f39b36fed1244e6e= .pdf >=20 > = https://www.reddit.com/r/RISCV/comments/10pvd96/64cores_c920_processor/ They also have a non-standard vendor extension for memory attributes and cache maintenance operations (conflicting with the standard ones) that you have to use in order to have working device drivers, which would mean writing and maintaining vendor-specific pmap and busdma changes. Up until now T-Head=E2=80=99s cores haven=E2=80=99t been in = anything particularly high-powered and so we=E2=80=99ve just ignored the problem, = but this may require a rethink. It is a real shame they couldn=E2=80=99t = have made the C920 follow the specs (like at least one of their more recent IP offerings does). Jess
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