Skip site navigation (1)Skip section navigation (2)
Date:      Sun, 21 Dec 1997 18:44:51 +1030
From:      Greg Lehey <grog@lemis.com>
To:        Jason Evans <jasone@canonware.com>
Cc:        Ric Flinn <rmf@radiks.net>, freebsd-sparc@FreeBSD.ORG
Subject:   Re: Register windowing
Message-ID:  <19971221184451.62453@lemis.com>
In-Reply-To: <Pine.BSF.3.96.971218020120.503D-100000@paladio>; from Jason Evans on Sat, Dec 20, 1997 at 10:54:11PM -0800
References:  <34988B26.7F0C8B1B@radiks.net> <Pine.BSF.3.96.971218020120.503D-100000@paladio>

next in thread | previous in thread | raw e-mail | index | archive | help
On Sat, Dec 20, 1997 at 10:54:11PM -0800, Jason Evans wrote:
> On Thu, 18 Dec 1997, Ric Flinn wrote:
>> I just recenly joined this list, and I'm no expert in the Sparc
>> architecture or Sparc OS's, but I'm curious about how FreeBSD for the
>> sparc will handle register windowing. I know there are several ways an
>> OS can use register windowing, perhaps there are obvious advantages to
>> one method or another that I don't know about.
>
> Well, I don't think I can answer your question, so let me outline what I
> understand of register windowing so that we can start a discussion that
> can lead to the OS register windowing handler methods you refer to.
>
> Here are basic bits of info that I think are true (correct me if I'm
> wrong):
>
> (etc)
>
> The main issue I can see here is how to decide how many register windows
> should be saved or restored when a trap occurs.
>
> (etc)

I think this sums up the issues pretty nicely.  I suppose the only
point to be made is that the number of windows in the register file
varies greatly from one processor to another.  Considering the
interest in older processors, the code should be flexible enough to
potentially be able to choose different strategies dependent on the
processor.

Greg



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?19971221184451.62453>