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Date:      Sat, 26 Feb 2005 18:10:01 -0800
From:      Kris Kennaway <kris@obsecurity.org>
To:        sparc64@FreeBSD.org
Subject:   "esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 4000" on e4500
Message-ID:  <20050227021000.GA47037@xor.obsecurity.org>

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--HcAYCG3uE/tztfnV
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An e4500 running RELENG_5 crashed overnight with the following.  I
asked Justin Gibbs about it, and he suggested that

"The driver seems to be complaining that its internal state is
indicating that a DMA is *not* in progress, but the chip is saying it
is."

Kris

db> show msgbuf
msgbufp = 0xfffff80001407fe0
magic = 63062, size = 32736, r= 115944, w = 116197, ptr = 0xfffff80001400000, cksum= 2460862
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
/var: bad dir ino 94212 at offset 0: mangled entry
panic: ufs_dirbad: bad dir
cpuid = 1
KDB: enter: panic
0, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
bad block 4763148255218685140, ino 382658
<3>pid 41 (syncer), uid 0 inumber 382658 on /usr: bad block
handle_workitem_freeblocks: block count
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
<118>Feb 26 04:35:51 e4500 kernel: pid 41 (syncer), uid 0 inumber 382658 on /usr: bad block
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 4000
bad block 4763148255213948044, ino 382790
<3>pid 41 (syncer), uid 0 inumber 382790 on /usr: bad block
handle_workitem_freeblocks: block count
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 4000
bad block 4764278571448611635, ino 404198
<3>pid 41 (syncer), uid 0 inumber 404198 on /usr: bad block
handle_workitem_freeblocks: block count
bad block 4763148255222369549, ino 424054
<3>pid 41 (syncer), uid 0 inumber 424054 on /usr: bad block
handle_workitem_freeblocks: block count
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
<118>Feb 26 04:35:52 e4500 kernel: pid 41 (syncer), uid 0 inumber 382790 on /usr: bad block
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
<118>Feb 26 04:35:52 e4500 kernel: pid 41 (syncer), uid 0 inumber 404198 on /usr: bad block
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 4000
<118>Feb 26 04:35:52 e4500 kernel: pid 41 (syncer), uid 0 inumber 424054 on /usr: bad block
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: unexpected disconnect [state 5, intr 20, stat 90, phase(c 100, p 0)]; sending REQUEST SENSE
(da0:esp0:0:0:0): esp0: timed out [ecb 0x10001ec48 (flags 0x5, dleft 20, stat 0)], <state 2, nexus 0x10001ec48, phase(l 12, c 100, p 0), resid 0, msg(q 0,o 0) >
(da0:esp0:0:0:0): sync negotiation disabled
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 20
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 1000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 2800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 1800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 3800
esp0: !TC on DATA XFER [intr 10, stat 87, step 4] prevphase 0, resid 4000
esp0: !TC on DATA XFER [intr 10, stat 83, step 4] prevphase 1, resid 800

db> wh
Tracing pid 6122 tid 100299 td 0xfffff8002a7e9c30
panic() at panic+0x16c
ufs_dirbad() at ufs_dirbad+0x38
ufs_lookup() at ufs_lookup+0x32c
ufs_vnoperate() at ufs_vnoperate+0x1c
vfs_cache_lookup() at vfs_cache_lookup+0x12c
ufs_vnoperate() at ufs_vnoperate+0x1c
lookup() at lookup+0x440
namei() at namei+0x274
stat() at stat+0x24
syscall() at syscall+0x318
-- syscall (188, FreeBSD ELF64, stat) %o7=0x105cc8 --
userland() at 0x40673728
user trace: trap %o7=0x105cc8
pc 0x40673728, sp 0x7fdffffbae1
pc 0x10560c, sp 0x7fdffffc0b1
pc 0x104584, sp 0x7fdffffc1b1
pc 0x1024f0, sp 0x7fdffffe391
pc 0x4025ac34, sp 0x7fdffffe451
done
db> 
--HcAYCG3uE/tztfnV
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