Date: Mon, 11 Dec 2006 08:05:21 -0800 (PST) From: ranjith kumar <ranjith_kumar_b4u@yahoo.com> To: freebsd-ia32@freebsd.org Subject: Re: prefetching on pentium 4 Message-ID: <234144.12400.qm@web58616.mail.re3.yahoo.com>
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--- Attilio Rao wrote: > 2006/12/6, ranjith kumar > : > > Hi, > > There are 4 types of prefetch instructions on > > pentium 4 (IA-32) processor. > > prefetchnta,prefetcht0,prefetcht1,prefetcht2. > > > > In case of pentium 4, IA-32 otimization manuvals > say > > that prefetcht0,prefetcht1,prefetcht2 are > identical. > > > > It also says ONLY prefetchnta instruction > prefetches > > data into L2 cache without poluting caches. > > > > When all the four instructions prefetches data > into > > L2 cache (not into L1 cache) , what is the meaning > in > > saying prefetchnta does not polute caches? > > > > ie)what is the difference between prefetchnta and > > other instructions? > > First of all, it is important to say that prefetch* > instruction is > only an hint for the CPU and not a *command* for > that, so the CPU > needs to evaluate (in a not precisated way) if > accept or not the > caching request. > From this point of view, prefetch* instruction might > be the more > accomodant possible for the CPU. > Different numbers mean different 'critical' level > for the CPU (0 - > high critical, 2 - low critical), which means > prefetching the cache > line to an higher level into the cache hierarchy. > This would means, in an hypotetical way: > > prefetch0 -> L1 prefetching > prefetch1 -> L2 prefetching > prefetch2 -> L3 prefetching > > And this is what really happens, for example, on P3 > (if you consider > P3 has not L3 cache, prefetch2 == prefetch1). > On P4 things are different beacause you would not > manipulate directly > L1 cache and, so, what happens is: > > prefetch0 -> L2 prefetching > prefetch1 -> L2 prefetching > prefetch2 -> L3 prefetching > (if L3 cache is not present prefetch2 is the same as > the other, from > this the assumption all the three instructions > behave at the same). > > prefetchnta is completely different beacause it > fetches a cache line > into the NT cache structure. > Non Temporal caches are global caches which are > particulary powerful > beacause they don't need of snooping messages > between CPUs (and, in > this way, they reduce the CPUs<->caches traffic) and > are used by NTI > family. Thanks. But when I executed two programs one prefetching using prefetchnta and the second using prefetcht0, the second program executed faster. (I used pentium4 processor and gcc compiler.)What could be the reason?When prefechnta is preferable over prefecht0? Also in "IA-32 systems programmers manual" nothing about nontemporal cache structure is written.The caches in IA-32 processors are L1 cache, L2 cache,write-combing cache,store buffer, instruction TLB and data TLB and L3 cache(not present in pentium4). Does non temporal cache and write combining buffer are same? Thanks in advance. > > Attilio > > > -- > Peace can only be achieved by understanding - A. > Einstein > ____________________________________________________________________________________ Want to start your own business? Learn how on Yahoo! Small Business. http://smallbusiness.yahoo.com/r-index
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