From owner-freebsd-arm@FreeBSD.ORG Mon Jan 24 11:06:57 2011 Return-Path: Delivered-To: freebsd-arm@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 5CFF810656A8 for ; Mon, 24 Jan 2011 11:06:57 +0000 (UTC) (envelope-from owner-bugmaster@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:4f8:fff6::28]) by mx1.freebsd.org (Postfix) with ESMTP id 4B88C8FC0A for ; Mon, 24 Jan 2011 11:06:57 +0000 (UTC) Received: from freefall.freebsd.org (localhost [127.0.0.1]) by freefall.freebsd.org (8.14.4/8.14.4) with ESMTP id p0OB6vYi077751 for ; Mon, 24 Jan 2011 11:06:57 GMT (envelope-from owner-bugmaster@FreeBSD.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.14.4/8.14.4/Submit) id p0OB6udu077749 for freebsd-arm@FreeBSD.org; Mon, 24 Jan 2011 11:06:56 GMT (envelope-from owner-bugmaster@FreeBSD.org) Date: Mon, 24 Jan 2011 11:06:56 GMT Message-Id: <201101241106.p0OB6udu077749@freefall.freebsd.org> X-Authentication-Warning: freefall.freebsd.org: gnats set sender to owner-bugmaster@FreeBSD.org using -f From: FreeBSD bugmaster To: freebsd-arm@FreeBSD.org Cc: Subject: Current problem reports assigned to freebsd-arm@FreeBSD.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 24 Jan 2011 11:06:57 -0000 Note: to view an individual PR, use: http://www.freebsd.org/cgi/query-pr.cgi?pr=(number). The following is a listing of current problems submitted by FreeBSD users. These represent problem reports covering all versions including experimental development code and obsolete releases. S Tracker Resp. Description -------------------------------------------------------------------------------- o arm/154227 arm [geli] using GELI leads to panic on ARM o arm/154189 arm lang/perl5.12 doesn't build on arm o arm/153380 arm Panic / translation fault with wlan on ARM o arm/150581 arm [irq] Unknown error generates IRQ address decoding err o arm/149288 arm mail/dovecot causes panic during configure on Sheevapl o arm/134368 arm [patch] nslu2_led driver for the LEDs on the NSLU2 p arm/134338 arm [patch] Lock GPIO accesses on ixp425 7 problems total. From owner-freebsd-arm@FreeBSD.ORG Wed Jan 26 14:34:26 2011 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id DFF3C106566C for ; Wed, 26 Jan 2011 14:34:26 +0000 (UTC) (envelope-from deveshkr@marvell.com) Received: from na3sys009aog109.obsmtp.com (na3sys009aog109.obsmtp.com [74.125.149.201]) by mx1.freebsd.org (Postfix) with SMTP id AED378FC16 for ; Wed, 26 Jan 2011 14:34:26 +0000 (UTC) Received: from source ([65.219.4.130]) (using TLSv1) by na3sys009aob109.postini.com ([74.125.148.12]) with SMTP ID DSNKTUAw8d+2gE6NFGnZfmIMXFZghatMCHli@postini.com; Wed, 26 Jan 2011 06:34:26 PST Received: from SC-vEXCH2.marvell.com ([10.93.76.134]) by sc-owa02.marvell.com ([10.93.76.22]) with mapi; Wed, 26 Jan 2011 06:34:24 -0800 From: Devesh Rai To: Mark Tinguely , "freebsd-arm@freebsd.org" Date: Wed, 26 Jan 2011 06:34:21 -0800 Thread-Topic: Changing virtual adress space layout Thread-Index: AcuzPzKYPeSG+g0fRfyNtPYB7ZHQggKIsvZA Message-ID: <0DB595A2CB707F458400BE9663B6A7225E42E359C8@SC-VEXCH2.marvell.com> In-Reply-To: <4D2F289C.9080908@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: Subject: RE: Changing virtual adress space layout X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Jan 2011 14:34:27 -0000 Hi Mark, Actually I want to map large portion of RAM in kernel virtual address space= . To achieve this in Linux, I did following 1) boot kernel with 256M by setting CONFIG_CMDLINE=3D"mem=3D256M". This fre= ed up more than 1GB of RAM for my module usages 2) increase KVA to 3GB by setting CONFIG_VMSPLIT_1G=3Dy ( 1G for user and 3= GB for kernel) 3) ioremap unused RAM ( 2GB - 256MB ) into Kernel virtual address space. Changing KERNBASE and KERNVIRTADDR "makeoption" from 0xc0000000 to 0x800000= 00 did not worked for me. Kernel hang while loading.=20 Thanks & Regards Devesh =20 -----Original Message----- From: Mark Tinguely [mailto:marktinguely@gmail.com]=20 Sent: Thursday, January 13, 2011 10:00 PM To: freebsd-arm@freebsd.org Cc: Devesh Rai Subject: Re: Changing virtual adress space layout On 1/13/2011 1:30 AM, Devesh Rai wrote: > Hi, > > I am new to FreeBSD. Can some tell how to change virtual address space la= yout in FreeBSD for arm? > For x86, KVA_PAGES=3DN option is there in FreeBSD. In Linux, I used CONF= IG_VMSPLIT option. > I am looking corresponding option for arm. > > Regards > Devesh I assume you have run out of space for the device virtual addresses. KERNBASE is hard coded in sys/arm/include/vm_param.h to be 0xc0000000. There is a related variable for each device configuration: the =20 KERNVIRTADDR "option" and "makeoption" values. This is usually in one=20 of the "std" file file for the device. KERNVIRTADDR sets the starting=20 location of the executable and is sometimes different than KERNBASE. The arm code does not map the from KERNBASE to 0xffff_ffff into the KVA.=20 Instead, there is a variable that determines the maximum size of the=20 kernel executable and kernel virtual address area. Above this defined=20 area lies the no-cache remap memory region, device map area, high=20 vector, etc. On a tangent note: There will be a great advantage in ARMv6/ARMv7 to go=20 to a 2GB UVA / 2GB KVA. --Mark. From owner-freebsd-arm@FreeBSD.ORG Wed Jan 26 15:38:33 2011 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id AEC0710656C1 for ; Wed, 26 Jan 2011 15:38:33 +0000 (UTC) (envelope-from marktinguely@gmail.com) Received: from mail-iy0-f182.google.com (mail-iy0-f182.google.com [209.85.210.182]) by mx1.freebsd.org (Postfix) with ESMTP id 6F67F8FC12 for ; Wed, 26 Jan 2011 15:38:33 +0000 (UTC) Received: by iyb26 with SMTP id 26so494489iyb.13 for ; Wed, 26 Jan 2011 07:38:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:message-id:date:from:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=IRvByHrcuCZZnf35/QcOILsh7gJqmB0v130qHmMIODk=; b=f/CFGx1fhvrWdt7iI2jL5xo1Kgd+UG1dQiYzFno/J2krENGZztIo69QeRUWYM3FA8l ckqGsvUL0qUwqEs3JkrmC8vBQCNdwnBbP6D5MjxRjb4k6BdsDSrpmsSyXBtDlD5h/yOV 5C5z6hbJHRiy/g1VBcqXP7HLutA4nOhYe6/pE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; b=uVps26xr0el0XZmoCupq6ERGYn5BBjSdew86/jCxkeD+9n9jtZem+VFFhokpBjeZFk T208EUweOjqGioetaJMnuD67ObAun++6ECgV4FaXRrJt/Ahr2GuH/3QJcTYS/ZlLNeC2 dil8R05HrXKAvan+OmUcs7qmAaOPHfA/+Kkd4= Received: by 10.231.205.132 with SMTP id fq4mr8366890ibb.17.1296056312823; Wed, 26 Jan 2011 07:38:32 -0800 (PST) Received: from [192.168.1.104] (c-24-245-26-12.hsd1.mn.comcast.net [24.245.26.12]) by mx.google.com with ESMTPS id 8sm13021341iba.22.2011.01.26.07.38.31 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 26 Jan 2011 07:38:32 -0800 (PST) Message-ID: <4D403FF3.7010500@gmail.com> Date: Wed, 26 Jan 2011 09:38:27 -0600 From: Mark Tinguely User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Devesh Rai References: <0DB595A2CB707F458400BE9663B6A7225E42E359C8@SC-VEXCH2.marvell.com> In-Reply-To: <0DB595A2CB707F458400BE9663B6A7225E42E359C8@SC-VEXCH2.marvell.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: "freebsd-arm@freebsd.org" Subject: Re: Changing virtual adress space layout X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Jan 2011 15:38:33 -0000 Reading your reply, it sounds like you want to directly map a full 1GB to the KVA. The upper 1GB will always be partially used; for example it has HIGH_VECTOR, and device mappings. So it sounds like you should set KERNBASE to 0x8000_0000, map the RAM at 0x8000_0000 and leave the KERNVIRTADDR where is was. The 1GB memory should be physically contiguous and properly aligned, so you be able to directly add the addresses into the KVA "level 1 pagetable entries" either manually or with pmap_map_chunk(). Sorry, I do not have my development machine, so I can't do the background work. Does changing the KERNBASE into a makeoption really overriding the static define in /sys/arm/include/vm_machdep.h? A "cc -E" (for example initarm() source file) would answer that question. The other place to look would be in /sys/conf, but after a quick look, I did not see any hardcoded values in the ARM specific files. Also, the KERNVIRTADDR does not equal KERNBASE on many ARM platforms ; the boot loader may have put the kernel text at an offset to pass parameters, and some older families use the ARM_USE_SMALL_ALLOC feature - a form of direct ARM pagetable map. For example, the Sheeva port has the KERNPHYSADDR/KERNVIRTADDR at 0x00900000/0xc0900000. --Mark. On 1/26/2011 8:34 AM, Devesh Rai wrote: > > Hi Mark, > > Actually I want to map large portion of RAM in kernel virtual address space. > To achieve this in Linux, I did following > > 1) boot kernel with 256M by setting CONFIG_CMDLINE="mem=256M". This freed up more than 1GB of RAM for my module usages > 2) increase KVA to 3GB by setting CONFIG_VMSPLIT_1G=y ( 1G for user and 3GB for kernel) > 3) ioremap unused RAM ( 2GB - 256MB ) into Kernel virtual address space. > > Changing KERNBASE and KERNVIRTADDR "makeoption" from 0xc0000000 to 0x80000000 did not worked for me. Kernel hang while loading. > > Thanks& Regards > Devesh > > -----Original Message----- > From: Mark Tinguely [mailto:marktinguely@gmail.com] > Sent: Thursday, January 13, 2011 10:00 PM > To: freebsd-arm@freebsd.org > Cc: Devesh Rai > Subject: Re: Changing virtual adress space layout > > On 1/13/2011 1:30 AM, Devesh Rai wrote: >> Hi, >> >> I am new to FreeBSD. Can some tell how to change virtual address space layout in FreeBSD for arm? >> For x86, KVA_PAGES=N option is there in FreeBSD. In Linux, I used CONFIG_VMSPLIT option. >> I am looking corresponding option for arm. >> >> Regards >> Devesh > I assume you have run out of space for the device virtual addresses. > > KERNBASE is hard coded in sys/arm/include/vm_param.h to be 0xc0000000. > > There is a related variable for each device configuration: the > KERNVIRTADDR "option" and "makeoption" values. This is usually in one > of the "std" file file for the device. KERNVIRTADDR sets the starting > location of the executable and is sometimes different than KERNBASE. > > The arm code does not map the from KERNBASE to 0xffff_ffff into the KVA. > Instead, there is a variable that determines the maximum size of the > kernel executable and kernel virtual address area. Above this defined > area lies the no-cache remap memory region, device map area, high > vector, etc. > > On a tangent note: There will be a great advantage in ARMv6/ARMv7 to go > to a 2GB UVA / 2GB KVA. > > --Mark. > From owner-freebsd-arm@FreeBSD.ORG Wed Jan 26 15:50:07 2011 Return-Path: Delivered-To: freebsd-arm@hub.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B0F5D1065672 for ; Wed, 26 Jan 2011 15:50:07 +0000 (UTC) (envelope-from gnats@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:4f8:fff6::28]) by mx1.freebsd.org (Postfix) with ESMTP id 741928FC18 for ; Wed, 26 Jan 2011 15:50:07 +0000 (UTC) Received: from freefall.freebsd.org (localhost [127.0.0.1]) by freefall.freebsd.org (8.14.4/8.14.4) with ESMTP id p0QFo78v034450 for ; Wed, 26 Jan 2011 15:50:07 GMT (envelope-from gnats@freefall.freebsd.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.14.4/8.14.4/Submit) id p0QFo7qe034449; Wed, 26 Jan 2011 15:50:07 GMT (envelope-from gnats) Resent-Date: Wed, 26 Jan 2011 15:50:07 GMT Resent-Message-Id: <201101261550.p0QFo7qe034449@freefall.freebsd.org> Resent-From: FreeBSD-gnats-submit@FreeBSD.org (GNATS Filer) Resent-To: freebsd-arm@FreeBSD.org Resent-Reply-To: FreeBSD-gnats-submit@FreeBSD.org, Michael Moll Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 74D51106566C for ; Wed, 26 Jan 2011 15:47:48 +0000 (UTC) (envelope-from nobody@FreeBSD.org) Received: from red.freebsd.org (red.freebsd.org [IPv6:2001:4f8:fff6::22]) by mx1.freebsd.org (Postfix) with ESMTP id 648508FC08 for ; Wed, 26 Jan 2011 15:47:48 +0000 (UTC) Received: from red.freebsd.org (localhost [127.0.0.1]) by red.freebsd.org (8.14.4/8.14.4) with ESMTP id p0QFllI5004171 for ; Wed, 26 Jan 2011 15:47:47 GMT (envelope-from nobody@red.freebsd.org) Received: (from nobody@localhost) by red.freebsd.org (8.14.4/8.14.4/Submit) id p0QFllRj004170; Wed, 26 Jan 2011 15:47:47 GMT (envelope-from nobody) Message-Id: <201101261547.p0QFllRj004170@red.freebsd.org> Date: Wed, 26 Jan 2011 15:47:47 GMT From: Michael Moll To: freebsd-gnats-submit@FreeBSD.org X-Send-Pr-Version: www-3.1 Cc: Subject: arm/154306: named crashes with signal 11 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Jan 2011 15:50:07 -0000 >Number: 154306 >Category: arm >Synopsis: named crashes with signal 11 >Confidential: no >Severity: serious >Priority: medium >Responsible: freebsd-arm >State: open >Quarter: >Keywords: >Date-Required: >Class: sw-bug >Submitter-Id: current-users >Arrival-Date: Wed Jan 26 15:50:07 UTC 2011 >Closed-Date: >Last-Modified: >Originator: Michael Moll >Release: CURRENT >Organization: >Environment: FreeBSD deskstar.kvedulv.de 9.0-CURRENT FreeBSD 9.0-CURRENT #0 r217665: Sat Jan 22 20:15:50 CET 2011 mmoll@emperor.kvedulv.de:/usr/obj/arm.arm/usr/current/src/sys/DESKSTAR arm >Description: When starting named on a Seagate Dockstar it crashes with signal 11 >How-To-Repeat: >Fix: A patch taken form http://cooltrainer.org/projects/freebsd-kirkwood/building/#patching is attached. It fixes the problem for me. Patch attached with submission follows: Index: contrib/bind9/lib/isc/arm/include/isc/atomic.h =================================================================== --- contrib/bind9/lib/isc/arm/include/isc/atomic.h (revision 217884) +++ contrib/bind9/lib/isc/arm/include/isc/atomic.h (working copy) @@ -49,26 +49,22 @@ static inline isc_int32_t isc_atomic_cmpxchg(isc_int32_t *p, isc_int32_t cmpval, isc_int32_t val) { - register int done, ras_start; + register int done, ras_start = 0xffff1004; __asm __volatile("1:\n" "adr %1, 1b\n" - "mov %0, #0xe0000004\n" "str %1, [%0]\n" - "mov %0, #0xe0000008\n" "adr %1, 2f\n" - "str %1, [%0]\n" + "str %1, [%0, #4]\n" "ldr %1, [%2]\n" "cmp %1, %3\n" "streq %4, [%2]\n" "2:\n" "mov %3, #0\n" - "mov %0, #0xe0000004\n" "str %3, [%0]\n" "mov %3, #0xffffffff\n" - "mov %0, #0xe0000008\n" - "str %3, [%0]\n" - : "=r" (ras_start), "=r" (done) + "str %3, [%0, #4]\n" + : "+r" (ras_start), "=r" (done) ,"+r" (p), "+r" (cmpval), "+r" (val) : : "memory"); return (done); >Release-Note: >Audit-Trail: >Unformatted: From owner-freebsd-arm@FreeBSD.ORG Wed Jan 26 20:24:37 2011 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 69D20106566B for ; Wed, 26 Jan 2011 20:24:37 +0000 (UTC) (envelope-from andrei.eltsov@gmail.com) Received: from mail-ey0-f182.google.com (mail-ey0-f182.google.com [209.85.215.182]) by mx1.freebsd.org (Postfix) with ESMTP id 4C7C98FC14 for ; Wed, 26 Jan 2011 20:24:36 +0000 (UTC) Received: by eyf6 with SMTP id 6so753471eyf.13 for ; Wed, 26 Jan 2011 12:24:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:message-id:date:from:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type; bh=3HX9uCSPyAB9mVdQvUvkTu87MQBy0SZ0wbnU15C+nrE=; b=QX+AbtIq9/E34iair6cXjoV3bbuGsgAckGO8AfKx6z0kFxTjo/Pl8bCLhbGoKZ8MP2 SuXJFU2KW/aOqqKF5WqOIb+ubH+ID+wZxVm/irwheJHcrMyEOQv/CV05MhkxKGsTlq7q NLvE/ccFw9FEZzs2fS4aoxgH1FArelPDiBPxE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type; b=JNIazRei+5mygZTs+lSvemZ2kFTBEKz3kaeXUqY9RsrQw4eYyPMbmC50VckCYLa9xX QNWyx7Z3W8VNIrdjPFfi0kvW4n0tHZpsbINmCCZ/KGm3i8uBydvda+45HUQSM6wKOyN3 0NVSujfWSBA7z1yMmnakuYukHXtTFjw/oyD0E= Received: by 10.213.29.16 with SMTP id o16mr1909876ebc.58.1296073475123; Wed, 26 Jan 2011 12:24:35 -0800 (PST) Received: from black.home ([95.79.150.100]) by mx.google.com with ESMTPS id b52sm12292837eei.13.2011.01.26.12.24.31 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 26 Jan 2011 12:24:32 -0800 (PST) Message-ID: <4D4082FD.9050208@gmail.com> Date: Wed, 26 Jan 2011 23:24:29 +0300 From: Andrey Eltsov User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: John Nicholls , Warner Losh , Andrew Turner , Guillaume Ballet , Ben Gray References: <1295613753.29290.6.camel@xeon.thinmesh.com> In-Reply-To: <1295613753.29290.6.camel@xeon.thinmesh.com> Content-Type: multipart/mixed; boundary="------------060403020603080904070903" X-Content-Filtered-By: Mailman/MimeDel 2.1.5 Cc: freebsd-arm@FreeBSD.org Subject: EMBEST devkit8000(TI OMAP3530) port FreeBSD 7.3 patch X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Jan 2011 20:24:37 -0000 This is a multi-part message in MIME format. --------------060403020603080904070903 Content-Type: text/plain; charset=windows-1251; format=flowed Content-Transfer-Encoding: 7bit Hi guys, I attached the patch for the RELEASE 7.3.0. System boots on DEVKIT8000 and basic utils work as expected, probably will work on Beagle Board also. However port has number of issues: - Timecounting is wrong - clock is running to fast. - Patch has a dirty hack for the generic UART: OMAP's UART does not untrigger the TXREADY interrupt when IIR is read, as the generic UART code expects so interrupt is masked manually inside 'uart_intr_txidle()'. - SDRAM size detection is not implemented, 128 mb is hardcoded. The kernel can be built as follows: 1. Set the MFS_IMAGE=path_to_your_md_root_image inside the kernel config file ('DK8000'). 2. $ make buildkernel KERNCONF=DK8000 TARGET=arm 3. Only binary kernel image were tested, devkit8000's uboot supports loading the kernel image over TFTP as follows # tftpboot 0x80200000 kernel.bin # go 0x80200000 For the instructions how to load kernel from the mmc card please refer to http://code.google.com/p/beagleboard-freebsd/wiki/BuildingAndBooting Be warned, this is the early development port addressed to deleopers only and just to play with the BB. :-) Regards, Andrey > On Fri, 2011-01-21 at 11:29 +0300, Andrey Eltsov wrote: > > Hi Audrey, > > I am playing with the Beagleboard XM board and we are very interested in > a FreeBSD port > > I would love to provide some feedback > > Thanks > > John > > > >> Hello everyone, >> >> Anybody interested in having EMBEST devkit8000(Beagle board clone) port? >> I've done basic support(MMU armv7, timers, uart, rootfs from MD) for the >> board in the context of the FreeBSD 7.3. Port in mostly based on the AVILA >> board code structure. Would someone like to review? >> >> Thanks, >> Andrey >> _______________________________________________ >> freebsd-arm@freebsd.org mailing list >> http://lists.freebsd.org/mailman/listinfo/freebsd-arm >> To unsubscribe, send any mail to "freebsd-arm-unsubscribe@freebsd.org" >> > > --------------060403020603080904070903 Content-Type: text/plain; name="dk8000.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="dk8000.diff" diff -rNup --exclude=.svn /usr/src/sys/arm/arm/cpufunc.c /usr/src.omap/sys/arm/arm/cpufunc.c --- /usr/src/sys/arm/arm/cpufunc.c 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/arm/cpufunc.c 2011-01-19 23:51:45.000000000 +0300 @@ -420,7 +420,127 @@ struct cpu_functions arm10_cpufuncs = { }; #endif /* CPU_ARM10 */ - +#if defined(CPU_ARM11) /* CPU_ARM11 */ +struct cpu_functions arm11_cpufuncs = { + /* CPU functions */ + + cpufunc_id, + cpufunc_nullop, + + /* MMU functions */ + + cpufunc_control, + cpufunc_domains, + arm11_setttb, + cpufunc_faultstatus, + cpufunc_faultaddress, + + /* TLB functions */ + + arm11_tlb_flushID, + arm11_tlb_flushID_SE, + arm11_tlb_flushI, + arm11_tlb_flushI_SE, + arm11_tlb_flushD, + arm11_tlb_flushD_SE, + + /* Cache operations */ + + armv6_icache_sync_all, + armv6_icache_sync_range, + + armv6_dcache_wbinv_all, + armv6_dcache_wbinv_range, + armv6_dcache_inv_range, + armv6_dcache_wb_range, + + armv6_idcache_wbinv_all, + armv6_idcache_wbinv_range, + cpufunc_nullop, + (void *)cpufunc_nullop, + (void *)cpufunc_nullop, + (void *)cpufunc_nullop, + + /* Other functions */ + + cpufunc_nullop, + arm11_drain_writebuf, + cpufunc_nullop, + (void *)cpufunc_nullop, + + (void *)cpufunc_nullop, + + /* Soft functions */ + + cpufunc_null_fixup, + cpufunc_null_fixup, + + arm11_context_switch, + + arm11_setup + + }; +#endif /* CPU_ARM11 */ +#if defined(CPU_OMAP3) /* CPU_OMAP */ +struct cpu_functions cortex_cpufuncs = { + /* CPU functions */ + + cpufunc_id, + cpufunc_nullop, + + /* MMU functions */ + + cpufunc_control, + cpufunc_domains, + armv7_setttb, + cpufunc_faultstatus, + cpufunc_faultaddress, + + /* TLB functions */ + + arm11_tlb_flushID, + armv7_tlb_flushID_SE, + arm11_tlb_flushI, + arm11_tlb_flushI_SE, + arm11_tlb_flushD, + arm11_tlb_flushD_SE, + + /* Cache operations */ + + armv7_icache_sync_all, + armv7_icache_sync_range, + armv7_dcache_wbinv_all, + armv7_dcache_wbinv_range, + armv7_dcache_inv_range, + armv7_dcache_wb_range, + + armv7_idcache_wbinv_all, + armv7_idcache_wbinv_range, + cpufunc_nullop, + (void *)cpufunc_nullop, + (void *)cpufunc_nullop, + (void *)cpufunc_nullop, + + /* Other functions */ + + cpufunc_nullop, + arm11_drain_writebuf, + cpufunc_nullop, + (void *)cpufunc_nullop, + + armv7_cpu_sleep, + + /* Soft functions */ + + cpufunc_null_fixup, + cpufunc_null_fixup, + + armv7_context_switch, + + armv7_setup, + + }; +#endif /* CPU_OMAP3 */ #ifdef CPU_SA110 struct cpu_functions sa110_cpufuncs = { /* CPU functions */ @@ -739,10 +859,10 @@ u_int cputype; u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */ #if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ - defined (CPU_ARM9E) || defined (CPU_ARM10) || \ + defined (CPU_ARM9E) || defined (CPU_ARM10) || defined (CPU_ARM11) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) + defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || defined(CPU_OMAP3) static void get_cachetype_cp15(void); @@ -876,6 +996,7 @@ get_cachetype_table() #endif /* SA110 || SA1100 || SA1111 || IXP12X0 */ + /* * Cannot panic here as we may not have a console yet ... */ @@ -962,6 +1083,28 @@ set_cpufuncs() goto out; } #endif /* CPU_ARM10 */ +#ifdef CPU_ARM11 + if (cputype == CPU_ID_ARM1136JS || + cputype == CPU_ID_ARM1136JSR1) { + cpufuncs = arm11_cpufuncs; + cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ + cpu_do_powersave = 1; /* Enable powersave */ + get_cachetype_cp15(); + pmap_pte_init_generic(); + goto out; + } +#endif +#ifdef CPU_OMAP3 + if (cputype == CPU_ID_CORTEXA8R1 || + cputype == CPU_ID_CORTEXA8R2) { + cpufuncs = cortex_cpufuncs; + cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ + cpu_do_powersave = 1; /* Enable powersave */ + get_cachetype_cp15(); + pmap_pte_init_armv7(); + goto out; + } +#endif #ifdef CPU_SA110 if (cputype == CPU_ID_SA110) { cpufuncs = sa110_cpufuncs; @@ -1512,7 +1655,7 @@ late_abort_fixup(arg) defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ - defined(CPU_ARM10) || defined(CPU_ARM11) + defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_OMAP3) #define IGN 0 #define OR 1 @@ -1810,8 +1953,127 @@ arm10_setup(args) cpu_idcache_wbinv_all(); } #endif /* CPU_ARM9E || CPU_ARM10 */ +#if defined(CPU_OMAP3) +struct cpu_option armv7_options[] = { + { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, + { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, + { "armv7.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, + { "armv7.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, + { "armv7.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, + { NULL, IGN, IGN, 0 } +}; -#ifdef CPU_ARM11 +void +armv7_setup(args) + char *args; +{ + int cpuctrl, cpuctrlmask; + cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_BPRD_ENABLE + | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE; + cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE + | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE + | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE + | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE + | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; + +#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS + cpuctrl |= CPU_CONTROL_AFLT_ENABLE; +#endif + cpuctrl = parse_cpu_options(args, armv7_options, cpuctrl); + +#ifdef __ARMEB__ + cpuctrl |= CPU_CONTROL_BEND_ENABLE; +#endif + if (vector_page == ARM_VECTORS_HIGH) { + cpuctrl |= CPU_CONTROL_VECRELOC; + } + + /* Clear out the cache */ + cpu_idcache_wbinv_all(); + + /* Now really make sure they are clean. - buggy on omap3 ???? */ + /* __asm __volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); */ + + /* Set the control register */ + ctrl = cpuctrl; + cpu_control(0xffffffff, cpuctrl); + /* And again. */ + cpu_idcache_wbinv_all(); +} +#define CPU_CSID_LEN(x) ((x) & 0x03) +#define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) +static inline u_int +get_cachesize_cp15(int cssr) +{ + u_int csid; + __asm volatile ("mcr p15, 2, %0, c0, c0, 0" :: "r"(cssr)); + __asm volatile ("mrc p15, 1, %0, c0, c0, 0" :: "r"(csid)); + return csid; + +} +static inline u_int popcnt(u_int x) +{ + x -= ((x >> 1) & 0x55555555); + x = (((x >> 2) & 0x33333333) + (x & 0x33333333)); + x = (((x >> 4) + x) & 0x0f0f0f0f); + x += (x >> 8); + x += (x >> 16); + return x & 0x0000003f; +} +static inline u_int clz(u_int x) +{ + x |= (x >> 1); + x |= (x >> 2); + x |= (x >> 4); + x |= (x >> 8); + x |= (x >> 16); + return 32 - popcnt(x); +} +/* Clean the data cache to the level of coherency. Slow. */ +void +armv7_dcache_wbinv_all() +{ + u_int clidr, loc, level; + + /* Cache Level ID Register */ + __asm volatile("mrc\tp15, 1, %0, c0, c0, 1" : "=r" (clidr)); + + loc = (clidr >> 24) & 7; /* Level of Coherency */ + + for (level = 0; level <= loc; level++) { + u_int ctype, csid; + int line_size, ways, nsets, wayshift, setshift; + + ctype = (clidr >> (level * 3)) & 7; + /* We're supposed to stop when ctype == 0, but we + * trust that loc isn't larger than necesssary. */ + if (ctype < 2) continue; /* no cache / only icache */ + + csid = get_cachesize_cp15(level << 1); + line_size = CPU_CSID_LEN(csid); + ways = CPU_CSID_ASSOC(csid); + nsets = (csid >> 13) & 0x7fff; + + wayshift = clz(ways); /* leading zeros */ + setshift = line_size + 4; + + for (; nsets >= 0; nsets--) { + int way; + + for (way = ways; way >= 0; way--) { + /* Clean by set/way */ + const u_int sw = (way << wayshift) + | (nsets << setshift) + | (level << 1); + __asm volatile("mcr\tp15, 0, %0, c7, c10, 2" + :: "r"(sw)); + } + } + } + +} +#endif +#if defined(CPU_ARM11) struct cpu_option arm11_options[] = { { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, @@ -1853,7 +2115,7 @@ arm11_setup(args) __asm __volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); /* Set the control register */ - curcpu()->ci_ctrl = cpuctrl; + ctrl = cpuctrl; cpu_control(0xffffffff, cpuctrl); /* And again. */ diff -rNup --exclude=.svn /usr/src/sys/arm/arm/cpufunc_asm_armv6.S /usr/src.omap/sys/arm/arm/cpufunc_asm_armv6.S --- /usr/src/sys/arm/arm/cpufunc_asm_armv6.S 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/arm/cpufunc_asm_armv6.S 2010-07-04 20:29:32.000000000 +0400 @@ -0,0 +1,134 @@ +/* $NetBSD: cpufunc_asm_armv6.S,v 1.2 2008/04/27 18:58:43 matt Exp $ */ + +/* + * Copyright (c) 2002, 2005 ARM Limited + * Portions Copyright (c) 2007 Microsoft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * ARMv6 assembly functions for manipulating caches. + * These routines can be used by any core that supports the mcrr address + * range operations. + */ + +#include + +/* + * Functions to set the MMU Translation Table Base register + * + * We need to clean and flush the cache as it uses virtual + * addresses that are about to change. + */ +ENTRY(armv6_setttb) +#ifdef PMAP_CACHE_VIVT + mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ + mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */ +#endif + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + + mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ + + mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ + RET + +/* + * Cache operations. + */ + +/* LINTSTUB: void armv6_icache_sync_range(vaddr_t, vsize_t); */ +ENTRY_NP(armv6_icache_sync_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */ + mcrr p15, 0, r1, r0, c12 /* clean D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_icache_sync_all(void); */ +ENTRY_NP(armv6_icache_sync_all) + /* + * We assume that the code here can never be out of sync with the + * dcache, so that we can safely flush the Icache and fall through + * into the Dcache cleaning code. + */ + mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ + mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_icache_sync_range(vaddr_t, vsize_t); */ +ENTRY(armv6_dcache_wb_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c12 /* clean D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_dcache_wbinv_range(vaddr_t, vsize_t); */ +ENTRY(armv6_dcache_wbinv_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c14 /* clean and invaliate D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* + * Note, we must not invalidate everything. If the range is too big we + * must use wb-inv of the entire cache. + * + * LINTSTUB: void armv6_dcache_inv_range(vaddr_t, vsize_t); + */ +ENTRY(armv6_dcache_inv_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c6 /* invaliate D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_idcache_wbinv_range(vaddr_t, vsize_t); */ +ENTRY(armv6_idcache_wbinv_range) + add r1, r1, r0 + sub r1, r1, #1 + mcrr p15, 0, r1, r0, c5 /* invaliate I cache range */ + mcrr p15, 0, r1, r0, c14 /* clean & invaliate D cache range */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET + +/* LINTSTUB: void armv6_idcache_wbinv_all(void); */ +ENTRY_NP(armv6_idcache_wbinv_all) + /* + * We assume that the code here can never be out of sync with the + * dcache, so that we can safely flush the Icache and fall through + * into the Dcache purging code. + */ + mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ + /* Fall through to purge Dcache. */ + +/* LINTSTUB: void armv6_dcache_wbinv_all(void); */ +ENTRY(armv6_dcache_wbinv_all) + mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + RET diff -rNup --exclude=.svn /usr/src/sys/arm/arm/cpufunc_asm_armv7.S /usr/src.omap/sys/arm/arm/cpufunc_asm_armv7.S --- /usr/src/sys/arm/arm/cpufunc_asm_armv7.S 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/arm/cpufunc_asm_armv7.S 2011-01-08 11:43:22.000000000 +0300 @@ -0,0 +1,157 @@ +/*- + * Copyright (c) 2010 Per Odlund + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* ARMv7 assembly functions for manipulating caches and other core functions. + * Based on cpufuncs for v6 and xscale. + */ + + +#include + +#define entrysize #32 + +ENTRY(armv7_cpu_sleep) + tst r0, #0x00000000 /* shouldn't sleep 0 */ + RET + + +ENTRY(armv7_wait) + mrc p15, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */ + add r0, r0, #0 /* a stall */ + RET + + +ENTRY(armv7_context_switch) + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ + mcr p15, 0, r0, c8, c7, 0 /* flush the I+D */ + RET + + +ENTRY(armv7_tlb_flushID_SE) + mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */ + mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + RET + + + +ENTRY(armv7_setttb) + stmdb sp!, {r0, lr} + bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */ + ldmia sp!, {r0, lr} + + mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ + + RET + +/* Cache operations. */ + +/* LINTSTUB: void armv7_icache_sync_range(vaddr_t, vsize_t); */ +ENTRY_NP(armv7_icache_sync_range) +1: + mcr p15, 0, r0, c7, c5, 1 /* invalidate the I-Cache line */ + mcr p15, 0, r0, c7, c10, 1 /* wb the D-Cache line */ + add r0, r0, entrysize + subs r1, r1, entrysize + bhi 1b + + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */ + RET + + +/* LINTSTUB: void armv7_icache_sync_all(void); */ +ENTRY_NP(armv7_icache_sync_all) + /* + * We assume that the code here can never be out of sync with the + * dcache, so that we can safely flush the Icache and fall through + * into the Dcache cleaning code. + */ + stmdb sp!, {r0, lr} + bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */ + ldmia sp!, {r0, lr} + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */ + RET + + +ENTRY(armv7_dcache_wb_range) +1: + mcr p15, 0, r0, c7, c10, 1 /* wb the D-Cache */ + add r0, r0, entrysize + subs r1, r1, entrysize + bhi 1b + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */ + RET + + +/* LINTSTUB: void armv7_dcache_wbinv_range(vaddr_t, vsize_t); */ +ENTRY(armv7_dcache_wbinv_range) +1: + mcr p15, 0, r0, c7, c14, 1 @wb and inv the D-Cache line + add r0, r0, entrysize + subs r1, r1, entrysize + bhi 1b + mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB + RET + +/* * LINTSTUB: void armv7_dcache_inv_range(vaddr_t, vsize_t); */ +ENTRY(armv7_dcache_inv_range) +1: + mcr p15, 0, r0, c7, c6, 1 @invalidate the D-Cache line + add r0, r0, entrysize + subs r1, r1, entrysize + bhi 1b + + mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB + RET + + +ENTRY(armv7_idcache_wbinv_range) +1: + mcr p15, 0, r0, c7, c5, 1 @invalidate the I-Cache line + mcr p15, 0, r0, c7, c14, 1 @wb and inv the D-Cache line + add r0, r0, entrysize + subs r1, r1, entrysize + bhi 1b + + mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB + RET + + +ENTRY_NP(armv7_idcache_wbinv_all) + /* + * We assume that the code here can never be out of sync with the + * dcache, so that we can safely flush the Icache and fall through + * into the Dcache purging code. + */ + mcr p15, 0, r0, c7, c5, 0 + b _C_LABEL(armv7_dcache_wbinv_all) + + +/* + * armv7_dcache_wbinv_all is in cpufunc.c. It's really too long to + * write in assembler. + */ diff -rNup --exclude=.svn /usr/src/sys/arm/arm/identcpu.c /usr/src.omap/sys/arm/arm/identcpu.c --- /usr/src/sys/arm/arm/identcpu.c 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/arm/identcpu.c 2010-07-04 20:29:32.000000000 +0400 @@ -303,6 +303,10 @@ const struct cpuidtab cpuids[] = { generic_steppings }, { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", generic_steppings }, + { CPU_ID_CORTEXA8R1, CPU_CLASS_ARM11J, "Cortex-A8 r1", + generic_steppings }, + { CPU_ID_CORTEXA8R2, CPU_CLASS_ARM11J, "Cortex-A8 r2", + generic_steppings }, { 0, CPU_CLASS_NONE, NULL, NULL } }; diff -rNup --exclude=.svn /usr/src/sys/arm/arm/locore.S /usr/src.omap/sys/arm/arm/locore.S --- /usr/src/sys/arm/arm/locore.S 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/arm/locore.S 2011-01-07 15:38:26.000000000 +0300 @@ -41,7 +41,8 @@ __FBSDID("$FreeBSD: src/sys/arm/arm/loco /* What size should this really be ? It is only used by initarm() */ #define INIT_ARM_STACK_SIZE 2048 - +#define OMAP_IO_BASE 0x48000000 +#define OMAP_IO_SECT_NUM 0x11 /* * This is for kvm_mkdb, and should be the address of the beginning * of the kernel text segment (not necessarily the same as kernbase). @@ -51,6 +52,13 @@ __FBSDID("$FreeBSD: src/sys/arm/arm/loco #define CPWAIT_BRANCH \ sub pc, pc, #4 +#define RESET_OMAP3 \ + ldr r0,=0x48307250 ; \ + ldr r1,=0x2 ; \ + str r1,[r0] ; \ +_rst_loop: b _rst_loop; + + #define CPWAIT(tmp) \ mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ mov tmp, tmp /* wait for it to complete */ ;\ @@ -123,6 +131,7 @@ disable_mmu: Lunmapped: #ifdef STARTUP_PAGETABLE_ADDR /* build page table from scratch */ + ldr r0, Lstartup_pagetable adr r4, mmu_init_table b 3f @@ -140,10 +149,8 @@ Lunmapped: bicne r5, r5, #0xff000000 orrne r5, r5, #PHYSADDR movne pc, r5 - mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ - /* Set the Domain Access register. Very important! */ mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) mcr p15, 0, r0, c3, c0, 0 @@ -158,11 +165,13 @@ Lunmapped: #endif mmu_done: + nop adr r1, .Lstart ldmia r1, {r1, r2, sp} /* Set initial stack and */ sub r2, r2, r1 /* get zero init data */ mov r3, #0 + .L1: str r3, [r1], #0x0004 /* get zero init data */ subs r2, r2, #4 @@ -203,7 +212,10 @@ mmu_init_table: MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) /* map VA 0xc0000000..0xc3ffffff to PA */ MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) - +#if defined(CPU_OMAP3) + /* map OMAP io so devices will work early on boot */ + MMU_INIT(OMAP_IO_BASE, OMAP_IO_BASE, OMAP_IO_SECT_NUM, L1_TYPE_S|L1_S_AP(AP_KRW)) +#endif .word 0 /* end of table */ #endif .Lstart: diff -rNup --exclude=.svn /usr/src/sys/arm/arm/pmap.c /usr/src.omap/sys/arm/arm/pmap.c --- /usr/src/sys/arm/arm/pmap.c 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/arm/pmap.c 2011-01-26 21:06:28.000000000 +0300 @@ -459,7 +459,7 @@ kernel_pt_lookup(vm_paddr_t pa) return (0); } -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 +#if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V7) != 0 void pmap_pte_init_generic(void) { @@ -1596,7 +1596,7 @@ pmap_clearbit(struct vm_page *pg, u_int pv->pv_flags &= ~PVF_NC; } } else - if (opte & L2_S_PROT_W) { + if (l2pte_writable_p(opte)) { vm_page_dirty(pg); /* * Entry is writable/cacheable: check if pmap @@ -1615,7 +1615,7 @@ pmap_clearbit(struct vm_page *pg, u_int } /* make the pte read only */ - npte &= ~L2_S_PROT_W; + npte = l2pte_set_readonly(npte); if (maskbits & PVF_WRITE) { /* @@ -2036,7 +2036,7 @@ pmap_fault_fixup(pmap_t pm, vm_offset_t pa = l2pte_pa(pte); - if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { + if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { /* * This looks like a good candidate for "page modified" * emulation... @@ -2077,7 +2077,7 @@ pmap_fault_fixup(pmap_t pm, vm_offset_t * changing. We've already set the cacheable bits based on * the assumption that we can write to this page. */ - *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; + *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); PTE_SYNC(ptep); rv = 1; } else @@ -2092,7 +2092,7 @@ pmap_fault_fixup(pmap_t pm, vm_offset_t /* Extract the physical address of the page */ if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) goto out; - /* Get the current flags for this page. */ + /* Get the current flags for this page1. */ pv = pmap_find_pv(pg, pm, va); if (pv == NULL) @@ -2102,7 +2102,7 @@ pmap_fault_fixup(pmap_t pm, vm_offset_t pv->pv_flags |= PVF_REF; - *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; + *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); PTE_SYNC(ptep); rv = 1; } @@ -3264,12 +3264,12 @@ pmap_protect(pmap_t pm, vm_offset_t sva, ptep = &l2b->l2b_kva[l2pte_index(sva)]; while (sva < next_bucket) { - if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { + if ((pte = *ptep) != 0 && l2pte_writable_p(pte)) { struct vm_page *pg; u_int f; pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); - pte &= ~L2_S_PROT_W; + pte = l2pte_set_readonly(pte); *ptep = pte; PTE_SYNC(ptep); @@ -3415,7 +3415,7 @@ do_l2b_alloc: * - The physical page has already been referenced * so no need to re-do referenced emulation here. */ - npte |= L2_S_PROTO; + npte |= l2pte_set_readonly(L2_S_PROTO); nflags |= PVF_REF; @@ -3441,7 +3441,7 @@ do_l2b_alloc: } if (prot & VM_PROT_WRITE) { - npte |= L2_S_PROT_W; + npte = l2pte_set_writable(npte); if (m != NULL) vm_page_flag_set(m, PG_WRITEABLE); } @@ -3460,7 +3460,7 @@ do_l2b_alloc: */ if (pmap_is_current(pmap) && (oflags & PVF_NC) == 0 && - (opte & L2_S_PROT_W) != 0 && + l2pte_writable_p(opte) && (prot & VM_PROT_WRITE) == 0) cpu_dcache_wb_range(va, PAGE_SIZE); } else { @@ -4060,7 +4060,7 @@ pmap_remove(pmap_t pm, vm_offset_t sva, * StrongARM accesses to non-cached pages are non-burst making writing * _any_ bulk data very slow. */ -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3) +#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3) || defined(CPU_OMAP3) void pmap_zero_page_generic(vm_paddr_t phys, int off, int size) { @@ -4322,7 +4322,7 @@ pmap_clean_page(struct pv_entry *pv, boo * hook points. The same comment regarding cachability as in * pmap_zero_page also applies here. */ -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3) +#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3) || defined (CPU_OMAP3) void pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) { @@ -4899,4 +4899,30 @@ pmap_devmap_find_va(vm_offset_t va, vm_s return (NULL); } - +#if defined(CPU_OMAP3) +void +pmap_pte_init_armv7(void) +{ + /* + * The ARMv7-A MMU is mostly compatible with generic. If the + * AP field is zero, that now means "no access" rather than + * read-only. The prototypes are a little different because of + * the XN bit. + */ + pmap_pte_init_generic(); + + pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; + pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; + pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; + + pte_l2_s_prot_u = L2_S_PROT_U_armv7; + pte_l2_s_prot_w = L2_S_PROT_W_armv7; + pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; + + pte_l1_s_proto = L1_S_PROTO_armv7; + pte_l1_c_proto = L1_C_PROTO_armv7; + pte_l2_s_proto = L2_S_PROTO_armv7; + pmap_copy_page_func = pmap_copy_page_generic; + pmap_zero_page_func = pmap_zero_page_generic; +} +#endif diff -rNup --exclude=.svn /usr/src/sys/arm/conf/DK8000 /usr/src.omap/sys/arm/conf/DK8000 --- /usr/src/sys/arm/conf/DK8000 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/conf/DK8000 2011-01-26 16:56:45.000000000 +0300 @@ -0,0 +1,132 @@ +# DEVKIT8000 -- DEVKIT8000 omap3530 board config +# kernel configuration file for FreeBSD/arm +# +# For more information on this file, please read the handbook section on +# Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD: src/sys/arm/conf/AVILA,v 1.6.2.3.4.1 2010/02/10 00:26:20 kensmith Exp $ + +# Kernel is to be loader by +# tftpboot 0x80200000 kernel.bin +# go 0x80200000 + +machine arm +ident DEVKIT8000 + +options PHYSADDR=0x80000000 +options KERNPHYSADDR=0x80200000 +options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm +#options FLASHADDR=0x50000000 +#options LOADERRAMADDR=0x00000000 +options STARTUP_PAGETABLE_ADDR=0x80000000 + +include "../omap3/std.devkit8000" +#To statically compile in device wiring instead of /boot/device.hints +hints "DK8000.hints" #Default places to look for devices. +makeoptions MODULES_OVERRIDE="" + +makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols +# TODO compile flags +#makeoptions CONF_CFLAGS=-mcpu=xscale +options HZ=100 +options DEVICE_POLLING + +# Debugging for use in -current +options KDB +#options GDB +options DDB #Enable the kernel debugger +#options INVARIANTS #Enable calls of extra sanity checking +#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS +#options WITNESS #Enable checks to detect deadlocks and cycles +#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed +#options DIAGNOSTIC + +options SCHED_4BSD #4BSD scheduler +options KSE +options NO_SWAPPING +options OMAP_MPU_TIMER_CLOCK_FREQ=12000000 +device loop +device ether +device bpf +device pty +device random +#device if_bridge + +options INET #InterNETworking +#options INET6 #IPv6 communications protocols +options FFS #Berkeley Fast Filesystem +options SOFTUPDATES #Enable FFS soft updates support +options UFS_ACL #Support for access control lists +options UFS_DIRHASH #Improve performance on big directories +#options NFSCLIENT #Network Filesystem Client +#options NFSSERVER #Network Filesystem Server +#options NFSLOCKD #Network Lock Manager +#options NFS_ROOT #NFS usable as /, requires NFSCLIENT +#options MSDOSFS #MSDOS Filesystem +#options CD9660 #ISO 9660 Filesystem +#options PROCFS #Process filesystem (requires PSEUDOFS) +options PSEUDOFS #Pseudo-filesystem framework +options SCSI_DELAY=5000 #Delay (in ms) before probing SCSI +options KTRACE #ktrace(1) support +options SYSVSHM #SYSV-style shared memory +options SYSVMSG #SYSV-style message queues +options SYSVSEM #SYSV-style semaphores +options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions +options KBD_INSTALL_CDEV # install a CDEV entry in /dev +#options BOOTP +#options BOOTP_NFSROOT +#options BOOTP_NFSV3 +#options BOOTP_WIRED_TO=npe0 +#options BOOTP_WIRED_TO=ath0 +#options BOOTP_COMPAT +#options PREEMPTION + + +device genclock +device nexus # ompio parent +device mem # Memory and kernel memory devices +#device saarm + +#device pci + +device uart + +#device dm9000 + +#DEBUG + +#options UNIONFS_DEBUG +#options VERBOSE_SYSINIT +#options VERBOSE_INIT_ARM + +#ROOT ramdisk +device md +#options unionfs +options MD_ROOT +options MD_ROOT_SIZE=10240 +makeoptions MFS_IMAGE=/home/urich/rootfs.img +options ROOTDEVNAME=\"/dev/md0\" +#env DK8000.env + + +#device usb +#options USB_DEBUG +#device uhci +#device ohci +#device ehci +#device ugen +#device umass +#device scbus # SCSI bus (required for SCSI) +#device da # Direct Access (disks) \ No newline at end of file diff -rNup --exclude=.svn /usr/src/sys/arm/conf/DK8000.hints /usr/src.omap/sys/arm/conf/DK8000.hints --- /usr/src/sys/arm/conf/DK8000.hints 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/conf/DK8000.hints 2011-01-09 16:04:46.000000000 +0300 @@ -0,0 +1,12 @@ +# $FreeBSD: src/sys/arm/conf/AVILA.hints,v 1.2.2.1.6.1 2010/02/10 00:26:20 kensmith Exp $ + +# +# Device wiring for the OMAP3. +# + +# DBGU is unit 0 +hint.uart.0.at="ompio0" +hint.uart.0.addr=0x49020000 +hint.uart.0.irq=74 +hint.uart.0.flags=0x10 + diff -rNup --exclude=.svn /usr/src/sys/arm/include/armreg.h /usr/src.omap/sys/arm/include/armreg.h --- /usr/src/sys/arm/include/armreg.h 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/include/armreg.h 2010-07-04 20:29:33.000000000 +0400 @@ -145,6 +145,8 @@ #define CPU_ID_ARM1026EJS 0x4106a260 #define CPU_ID_ARM1136JS 0x4107b360 #define CPU_ID_ARM1136JSR1 0x4117b360 +#define CPU_ID_CORTEXA8R1 0x411fc080 +#define CPU_ID_CORTEXA8R2 0x412fc080 #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 #define CPU_ID_TI925T 0x54029250 diff -rNup --exclude=.svn /usr/src/sys/arm/include/cpuconf.h /usr/src.omap/sys/arm/include/cpuconf.h --- /usr/src/sys/arm/include/cpuconf.h 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/include/cpuconf.h 2011-01-17 22:00:33.000000000 +0300 @@ -61,7 +61,8 @@ defined(CPU_XSCALE_80200) + \ defined(CPU_XSCALE_80321) + \ defined(CPU_XSCALE_PXA2X0) + \ - defined(CPU_XSCALE_IXP425)) + defined(CPU_XSCALE_IXP425) + \ + defined(CPU_OMAP3)) /* * Step 2: Determine which ARM architecture versions are configured. @@ -83,7 +84,7 @@ #define ARM_ARCH_5 0 #endif -#if defined(CPU_ARM11) +#if defined(CPU_ARM11) || defined(CPU_OMAP3) #define ARM_ARCH_6 1 #else #define ARM_ARCH_6 0 @@ -127,10 +128,15 @@ defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ defined(CPU_ARM10) || defined(CPU_ARM11)) #define ARM_MMU_GENERIC 1 + #else #define ARM_MMU_GENERIC 0 #endif - +#if defined(CPU_OMAP3) +#define ARM_MMU_V7 1 +#else +#define ARM_MMU_V7 0 +#endif #if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ defined(CPU_IXP12X0)) #define ARM_MMU_SA1 1 @@ -147,7 +153,7 @@ #endif #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ - ARM_MMU_SA1 + ARM_MMU_XSCALE) + ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_V7) #if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) #error ARM_NMMUS is 0 #endif diff -rNup --exclude=.svn /usr/src/sys/arm/include/cpufunc.h /usr/src.omap/sys/arm/include/cpufunc.h --- /usr/src/sys/arm/include/cpufunc.h 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/include/cpufunc.h 2011-01-07 00:44:48.000000000 +0300 @@ -378,7 +378,23 @@ extern unsigned arm10_dcache_index_max; extern unsigned arm10_dcache_index_inc; #endif -#ifdef CPU_ARM11 +#if defined(CPU_OMAP3) +void armv7_setttb (u_int); +void armv7_cpu_sleep (int); +void armv7_context_switch (void); +void armv7_setup (char *string); +void armv7_tlb_flushID_SE (u_int); +void armv7_icache_sync_all (void); +void armv7_icache_sync_range (vm_offset_t, vm_size_t); +void armv7_dcache_wbinv_all (void); +void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); +void armv7_dcache_inv_range (vm_offset_t, vm_size_t); +void armv7_dcache_wb_range (vm_offset_t, vm_size_t); +void armv7_idcache_wbinv_all (void); +void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); +#endif + +#if defined(CPU_ARM11) || defined(CPU_OMAP3) void arm11_setttb (u_int); void arm11_tlb_flushID_SE (u_int); @@ -393,6 +409,15 @@ void arm11_tlb_flushD (void); void arm11_tlb_flushD_SE (u_int va); void arm11_drain_writebuf (void); + +void armv6_icache_sync_all (void); +void armv6_icache_sync_range (vm_offset_t, vm_size_t); +void armv6_dcache_wbinv_all (void); +void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); +void armv6_dcache_inv_range (vm_offset_t, vm_size_t); +void armv6_dcache_wb_range (vm_offset_t, vm_size_t); +void armv6_idcache_wbinv_all (void); +void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t); #endif #if defined(CPU_ARM9E) || defined (CPU_ARM10) @@ -410,7 +435,7 @@ void armv5_ec_idcache_wbinv_all(void); void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); #endif -#if defined (CPU_ARM10) || defined (CPU_ARM11) +#if defined (CPU_ARM10) || defined (CPU_ARM11) || defined (CPU_OMAP3) void armv5_setttb(u_int); void armv5_icache_sync_all(void); diff -rNup --exclude=.svn /usr/src/sys/arm/include/intr.h /usr/src.omap/sys/arm/include/intr.h --- /usr/src/sys/arm/include/intr.h 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/include/intr.h 2011-01-11 23:38:44.000000000 +0300 @@ -43,6 +43,8 @@ #define NIRQ 128 #elif defined(CPU_ARM9) #define NIRQ 64 +#elif defined(CPU_OMAP3) +#define NIRQ 96 #else #define NIRQ 32 #endif diff -rNup --exclude=.svn /usr/src/sys/arm/include/pmap.h /usr/src.omap/sys/arm/include/pmap.h --- /usr/src/sys/arm/include/pmap.h 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/include/pmap.h 2011-01-26 21:41:29.000000000 +0300 @@ -262,18 +262,10 @@ extern int pmap_needs_pte_sync; * We use these macros since we use different bits on different processor * models. */ -#define L1_S_PROT_U (L1_S_AP(AP_U)) -#define L1_S_PROT_W (L1_S_AP(AP_W)) -#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) - #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\ L1_S_XSCALE_TEX(TEX_XSCALE_T)) -#define L2_L_PROT_U (L2_AP(AP_U)) -#define L2_L_PROT_W (L2_AP(AP_W)) -#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) - #define L2_L_CACHE_MASK_generic (L2_B|L2_C) #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \ L2_XSCALE_L_TEX(TEX_XSCALE_T)) @@ -301,6 +293,28 @@ extern int pmap_needs_pte_sync; #define L2_S_PROTO_generic (L2_TYPE_S) #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) +#define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) +#define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) +#define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) +#define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) + +#define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C) + +#define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) +#define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) +#define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) +#define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) + +#define L2_L_CACHE_MASK_armv7 (L2_B|L2_C) + +#define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) +#define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) +#define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) +#define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) +#define L2_S_CACHE_MASK_armv7 (L2_B|L2_C) +#define L1_S_PROTO_armv7 (L1_TYPE_S) +#define L1_C_PROTO_armv7 (L1_TYPE_C) +#define L2_S_PROTO_armv7 (L2_TYPE_S) /* * User-visible names for the ones that vary with MMU class. */ @@ -319,7 +333,51 @@ extern int pmap_needs_pte_sync; #define L1_C_PROTO pte_l1_c_proto #define L2_S_PROTO pte_l2_s_proto +#elif ARM_MMU_V7 == 1 +/* XXX: OMAP3 needs this fix */ +#if 0 +#define L1_S_PROT_U L1_S_PROT_U_armv7 +#define L1_S_PROT_W L1_S_PROT_W_armv7 +#define L1_S_PROT_RO L1_S_PROT_RO_armv7 +#define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 +#else +#define L1_S_PROT_U (L1_S_AP(AP_U)) +#define L1_S_PROT_W (L1_S_AP(AP_W)) +#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) +#define L1_S_PROT_RO (0) +#endif + +#define L2_S_PROT_U L2_S_PROT_U_armv7 +#define L2_S_PROT_W L2_S_PROT_W_armv7 +#define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 +#define L2_S_PROT_RO L2_S_PROT_RO_armv7 + +#define L2_L_PROT_U L2_L_PROT_U_armv7 +#define L2_L_PROT_W L2_L_PROT_W_armv7 +#define L2_L_PROT_RO L2_L_PROT_RO_armv7 +#define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 + +#define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 +#define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 +#define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 + + +/* These prototypes make writeable mappings, while the other MMU types + * make read-only mappings. */ +#define L1_S_PROTO L1_S_PROTO_armv7 +#define L1_C_PROTO L1_C_PROTO_armv7 +#define L2_S_PROTO L2_S_PROTO_armv7 + #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 + +#define L1_S_PROT_U (L1_S_AP(AP_U)) +#define L1_S_PROT_W (L1_S_AP(AP_W)) +#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) +#define L2_L_PROT_U (L2_AP(AP_U)) +#define L2_L_PROT_W (L2_AP(AP_W)) +#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) + + #define L2_S_PROT_U L2_S_PROT_U_generic #define L2_S_PROT_W L2_S_PROT_W_generic #define L2_S_PROT_MASK L2_S_PROT_MASK_generic @@ -351,7 +409,7 @@ extern int pmap_needs_pte_sync; #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC #else -#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) +#if (ARM_MMU_SA1 + ARM_MMU_V7 != 0) && (ARM_NMMUS == 1) #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC #elif defined(CPU_XSCALE_81342) @@ -362,19 +420,40 @@ extern int pmap_needs_pte_sync; #endif #endif +#if (ARM_MMU_V7 == 0) /* * These macros return various bits based on kernel/user and protection. * Note that the compiler will usually fold these at compile time. */ #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ - (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) + (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) +#else +#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ + (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO)) + +#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ + (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO)) +#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ + (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO)) +#endif +/* + * Macros to set and query the write permission on page descriptors. + */ +#define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) +#define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) +#define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) +#define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) + +#define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ + (L2_S_PROT_RO == 0 || \ + ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) /* * Macros to test if a mapping is mappable with an L1 Section mapping * or an L2 Large Page mapping. @@ -436,7 +515,7 @@ extern pt_entry_t pte_l2_s_proto; extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342) +#if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V7) != 0 || defined(CPU_XSCALE_81342) void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); void pmap_zero_page_generic(vm_paddr_t, int, int); @@ -450,6 +529,9 @@ void pmap_pte_init_arm9(void); #if defined(CPU_ARM10) void pmap_pte_init_arm10(void); #endif /* CPU_ARM10 */ +#if defined(CPU_OMAP3) +void pmap_pte_init_armv7(void); +#endif /* CPU_OMAP3 */ #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ #if /* ARM_MMU_SA1 == */1 diff -rNup --exclude=.svn /usr/src/sys/arm/include/pte.h /usr/src.omap/sys/arm/include/pte.h --- /usr/src/sys/arm/include/pte.h 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/arm/include/pte.h 2011-01-17 22:00:33.000000000 +0300 @@ -268,6 +268,9 @@ typedef uint32_t pt_entry_t; /* page ta #define AP_W 0x01 /* writable */ #define AP_U 0x02 /* user */ +#define AP_R 0x01 /* readable armv7 */ +#define AP_RO 0x20 /* read-only armv7 */ + /* * Short-hand for common AP_* constants. * diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/devkit8000_machdep.c /usr/src.omap/sys/arm/omap3/devkit8000_machdep.c --- /usr/src/sys/arm/omap3/devkit8000_machdep.c 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/devkit8000_machdep.c 2011-01-26 21:47:52.000000000 +0300 @@ -0,0 +1,496 @@ +/* $FreeBSD: devkit8000_machdep.c$ */ +/* + * + * Copyright (c) 2010-2011 Andrey Eltsov + * This file is based on avila_machdep.c and hpc_machdep.c + * THIS SOFTWARE IS PROVIDED BY ANDREY ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#define EARLY_DEBUG +#undef EARLY_DEBUG + +#include "opt_msgbuf.h" + +#include +__FBSDID("$FreeBSD: src/sys/arm/omap3/devkit8000_machdep.c$"); +#define _ARM32_BUS_DMA_PRIVATE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "uart_ll.h" +#include +#include + +#define SDRAM_START 0x80000000 + +#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ +#define KERNEL_PT_AFKERNEL 1 /* L2 table for mapping after kernel */ +#define KERNEL_PT_AFKERNEL_NUM 9 + +/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ +#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) + +/* Define various stack sizes in pages */ +#define IRQ_STACK_SIZE 1 +#define ABT_STACK_SIZE 1 +#define UND_STACK_SIZE 1 + +extern u_int data_abort_handler_address; +extern u_int prefetch_abort_handler_address; +extern u_int undefined_handler_address; + +struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; + +extern void *_end; + +extern int *end; + +struct pcpu __pcpu; +struct pcpu *pcpup = &__pcpu; + +/* Physical and virtual addresses for some global pages */ + +vm_paddr_t phys_avail[10]; +vm_paddr_t dump_avail[4]; +vm_offset_t physical_pages; + +struct pv_addr systempage; +struct pv_addr msgbufpv; +struct pv_addr irqstack; +struct pv_addr undstack; +struct pv_addr abtstack; +struct pv_addr kernelstack; +struct pv_addr minidataclean; + +static struct trapframe proc0_tf; + + + + + +/* Static device mappings. */ +static const struct pmap_devmap omap3_devmap[] = { + /* Physical/Virtual address for I/O space */ + { + OMAP3_IO_VBASE, + OMAP3_IO_HWBASE, + OMAP3_IO_SIZE, + VM_PROT_READ|VM_PROT_WRITE, + PTE_NOCACHE, + }, + { + 0, + 0, + 0, + 0, + 0, + } +}; + +#ifdef EARLY_DEBUG +/*XXX: this stuff will only work if the 1:1 OMAP3 IO mapping is done in the locore.S */ +/* 1:1 IO mapping at early boot */ +static vm_paddr_t omap3_io_base_vaddr = OMAP3_IO_HWBASE; +static unsigned char uart_read_reg_early(unsigned long* base_addr, int offset) +{ + return *(base_addr+offset); +} +static void uart_barrier(char* base_addr) +{ +} +static void uart_set_reg_early(unsigned long* base_addr, int offset, unsigned char val) +{ + *(base_addr+offset) = val; +} + +static void early_console_init() +{ + int divisor; + uint8_t lcr; + u_char ier; + lcr = 0; + lcr |= LCR_8BITS; + divisor = 2995200 / 115200; + uart_set_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_LCR, lcr | LCR_DLAB); + uart_barrier(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE); + uart_set_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_DLL, divisor & 0xff); + uart_set_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_DLH, (divisor >> 8) & 0xff); + uart_barrier(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE); + + /* Set LCR and clear DLAB. */ + uart_set_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_LCR, lcr); + uart_barrier(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE); + + /* Disable all interrupt sources. */ + ier = uart_read_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_IER) & 0xf0; + uart_set_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_IER, ier); + uart_barrier(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE); + + /* Disable the FIFO (if present). */ + uart_set_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_FCR, 0); + uart_barrier(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE); + +} + +static void +early_putchar(int c) +{ + int limit; + + limit = 25000; + while ((uart_read_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_LSR) & LSR_THRE) == 0 && --limit){}; + uart_set_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_DATA, c); + uart_barrier(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE); + limit = 25000; + while ((uart_read_reg_early(omap3_io_base_vaddr+OMAP3_CONSOLE_BASE, REG_LSR) & LSR_TEMT) == 0 && --limit) {}; +} + +static void early_xputchar(int ch) +{ + if (ch == '\n') + early_putchar('\r'); + early_putchar(ch); +} + +void early_printf(const char *fmt,...) +{ + va_list ap; + const char *hex = "0123456789abcdef"; + char buf[10]; + char *s; + unsigned u; + int c; + + va_start(ap, fmt); + while ((c = *fmt++)) { + if (c == '%') { + c = *fmt++; + switch (c) { + case 'c': + early_xputchar(va_arg(ap, int)); + continue; + case 's': + for (s = va_arg(ap, char *); *s; s++) + early_xputchar(*s); + continue; + case 'd': /* A lie, always prints unsigned */ + case 'u': + u = va_arg(ap, unsigned); + s = buf; + do + *s++ = '0' + u % 10U; + while (u /= 10U); + dumpbuf:; + while (--s >= buf) + early_xputchar(*s); + continue; + case 'x': + u = va_arg(ap, unsigned); + s = buf; + do + *s++ = hex[u & 0xfu]; + while (u >>= 4); + goto dumpbuf; + } + } + early_xputchar(c); + } + va_end(ap); + + return; +} +#endif + +uint32_t +omap3_sdram_size(void) +{ + return (128 * 1024 * 1024); +} + +void * +initarm(void *arg, void *arg2) +{ +/* Here we already have the initial pagetable from locore.S with PA == VA and PA to 0xc0000000(KERNBASE), running pc > KERNBASE */ + struct pv_addr kernel_l1pt; + int loop, i; + u_int l1pagetable; + vm_offset_t freemempos; + vm_offset_t freemem_pt; + vm_offset_t afterkern; + vm_offset_t freemem_after; + vm_offset_t lastaddr; + uint32_t memsize; +#ifdef EARLY_DEBUG + early_console_init(); +#endif + + if(set_cpufuncs()) { +#ifdef EARLY_DEBUG + early_printf("Unknown CPUID\n"); +#endif + return; + } + + lastaddr = fake_preload_metadata(); + pcpu_init(pcpup, 0, sizeof(struct pcpu)); + PCPU_SET(curthread, &thread0); + freemempos = SDRAM_START + 0x200000; + /* Define a macro to simplify memory allocation */ +#define valloc_pages(var, np) \ + alloc_pages((var).pv_pa, (np)); \ + (var).pv_va = (var).pv_pa - SDRAM_START + KERNBASE; + +#define alloc_pages(var, np) \ + freemempos -= (np * PAGE_SIZE); \ + (var) = freemempos; \ + memset((char *)(var), 0, ((np) * PAGE_SIZE)); + + while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) + freemempos -= PAGE_SIZE; + valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); + for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { + if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { + valloc_pages(kernel_pt_table[loop], + L2_TABLE_SIZE / PAGE_SIZE); + } else { + kernel_pt_table[loop].pv_pa = freemempos + + (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * + L2_TABLE_SIZE_REAL; + kernel_pt_table[loop].pv_va = + kernel_pt_table[loop].pv_pa - SDRAM_START + KERNBASE; + } + } + + freemem_pt = freemempos; + freemempos = SDRAM_START + 0x100000; + + /* + * Allocate a page for the system page mapped to V0x00000000 + * This page will just contain the system vectors and can be + * shared by all processes. + */ + valloc_pages(systempage, 1); + + /* Allocate stacks for all modes */ + valloc_pages(irqstack, IRQ_STACK_SIZE); + valloc_pages(abtstack, ABT_STACK_SIZE); + valloc_pages(undstack, UND_STACK_SIZE); + valloc_pages(kernelstack, KSTACK_PAGES); + alloc_pages(minidataclean.pv_pa, 1); + valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE); + /* + * Allocate memory for the l1 and l2 page tables. The scheme to avoid + * wasting memory by allocating the l1pt on the first 16k memory was + * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for + * this to work (which is supposed to be the case). + */ + + /* + * Now we start construction of the L1 page table + * We start by mapping the L2 page tables into the L1. + * This means that we can replace L1 mappings later on if necessary + */ + l1pagetable = kernel_l1pt.pv_va; + + /* Map the L2 pages tables in the L1 page table */ + pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), + &kernel_pt_table[KERNEL_PT_SYS]); + /* Following pieces will be mapped as sections */ + pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000, + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000, + 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); +#ifdef EARLY_DEBUG + early_printf("lastaddr = 0x%x\n",lastaddr); +#endif + pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000, + (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1), + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1); + afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE + - 1)); + + for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { + pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, + &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); + } + pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + + + /* Map the Mini-Data cache clean area. */ + + /* xscale_setup_minidata(l1pagetable, afterkern, + minidataclean.pv_pa); + */ + + /* Map the vector page. */ + pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + + pmap_devmap_bootstrap(l1pagetable, omap3_devmap); + + /* + * Give the XScale global cache clean code an appropriately + * sized chunk of unmapped VA space starting at 0xff000000 + * (our device mappings end before this address). + + xscale_cache_clean_addr = 0xff000000U; + + */ + /* Load new kernel pagetable */ +#ifdef EARLY_DEBUG + early_printf("before setttb\n"); +#endif + cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); + setttb(kernel_l1pt.pv_pa); + cpu_tlb_flushID(); + cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); + +#ifdef EARLY_DEBUG + omap3_io_base_vaddr = OMAP3_IO_VBASE; + early_printf("new kernel pagetable loaded omap3_io_base_vaddr=0x%x OMAP3_IO_VBASE=0x%x\n",omap3_io_base_vaddr,OMAP3_IO_VBASE); + early_printf("new I/O ok\n"); +#endif + /* + * Pages were allocated during the secondary bootstrap for the + * stacks for different CPU modes. + * We must now set the r13 registers in the different CPU modes to + * point to these stacks. + * Since the ARM stacks use STMFD etc. we must set r13 to the top end + * of the stack memory. + */ + + + set_stackptr(PSR_IRQ32_MODE, + irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); + set_stackptr(PSR_ABT32_MODE, + abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); + set_stackptr(PSR_UND32_MODE, + undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); + + + + /* + * We must now clean the cache again.... + * Cleaning may be done by reading new data to displace any + * dirty data in the cache. This will have happened in setttb() + * but since we are boot strapping the addresses used for the read + * may have just been remapped and thus the cache could be out + * of sync. A re-clean after the switch will cure this. + * After booting there are no gross reloations of the kernel thus + * this problem will not occur after initarm(). + */ + cpu_idcache_wbinv_all(); + /* + * Fetch the SDRAM start/size from the omap3 SDRAM configration + * registers. + */ + cninit(); + memsize = omap3_sdram_size(); + physmem = memsize / PAGE_SIZE; + + /* Set stack for exception handlers */ + + data_abort_handler_address = (u_int)data_abort_handler; + prefetch_abort_handler_address = (u_int)prefetch_abort_handler; + undefined_handler_address = (u_int)undefinedinstruction_bounce; + undefined_init(); + + proc_linkup0(&proc0, &thread0); + thread0.td_kstack = kernelstack.pv_va; + thread0.td_pcb = (struct pcb *) + (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; + thread0.td_pcb->pcb_flags = 0; + thread0.td_frame = &proc0_tf; + pcpup->pc_curpcb = thread0.td_pcb; + + /* Enable MMU, I-cache, D-cache, write buffer. */ + arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); + pmap_curmaxkvaddr = afterkern + PAGE_SIZE; + dump_avail[0] = SDRAM_START; + dump_avail[1] = SDRAM_START + memsize; + dump_avail[2] = 0; + dump_avail[3] = 0; + printf("DK8000: pmap_curmaxkvaddr 0x%x\n",pmap_curmaxkvaddr); + pmap_bootstrap(pmap_curmaxkvaddr, + KERNBASE + 0x10000000, &kernel_l1pt); + msgbufp = (void*)msgbufpv.pv_va; + msgbufinit(msgbufp, MSGBUF_SIZE); + mutex_init(); + i = 0; + + phys_avail[i++] = round_page(virtual_avail - KERNBASE + SDRAM_START); + phys_avail[i++] = trunc_page(SDRAM_START + memsize - 1); + phys_avail[i++] = 0; + phys_avail[i] = 0; + init_param1(); + init_param2(physmem); + kdb_init(); + return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - + sizeof(struct pcb))); +} + +void resolve_symb(void *ptr) +{ + const char *name; + c_db_sym_t sym; + db_expr_t offset; + sym = db_search_symbol((vm_offset_t)ptr,DB_STGY_PROC, &offset); + db_symbol_values(sym, &name, NULL); + if (name != NULL) { + printf("Addr 0x%p Symbol %s\n", ptr, name); + } + else { + printf("Addr 0x%p Symbol %s\n", ptr, "no"); + } +} diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/files.devkit8000 /usr/src.omap/sys/arm/omap3/files.devkit8000 --- /usr/src/sys/arm/omap3/files.devkit8000 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/files.devkit8000 2011-01-26 21:48:14.000000000 +0300 @@ -0,0 +1,3 @@ +#$FreeBSD: src/sys/arm/omap3/files.devkit8000,v 1.2.4.2.6.1 2010/02/10 00:26:20 kensmith Exp $ +arm/omap3/devkit8000_machdep.c standard +#arm/omap3/dm9000.c optional dm9000 diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/files.omap3 /usr/src.omap/sys/arm/omap3/files.omap3 --- /usr/src/sys/arm/omap3/files.omap3 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/files.omap3 2011-01-09 23:39:03.000000000 +0300 @@ -0,0 +1,16 @@ +#$FreeBSD: src/sys/arm/omap3/files.omap3,v 1.4.2.1.6.1 2010/02/10 00:26:20 kensmith Exp $ +arm/arm/bus_space_generic.c standard +arm/arm/cpufunc_asm_arm11.S standard +arm/arm/cpufunc_asm_armv7.S standard +arm/arm/cpufunc_asm_armv6.S standard +arm/arm/cpufunc_asm_armv5.S standard +arm/arm/irq_dispatch.S standard +arm/omap3/omap3.c standard +arm/omap3/omap3_space.c standard +arm/omap3/omap3_timer.c standard +arm/arm/bus_space_asm_generic.S standard +arm/omap3/omap3_a4x_io.S optional uart +arm/omap3/uart_cpu_omap3.c optional uart +arm/omap3/uart_bus_omap3.c optional uart +arm/omap3/omap3_a4x_space.c optional uart +dev/uart/uart_dev_ns8250.c optional uart diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/omap3.c /usr/src.omap/sys/arm/omap3/omap3.c --- /usr/src/sys/arm/omap3/omap3.c 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/omap3.c 2011-01-26 21:30:03.000000000 +0300 @@ -0,0 +1,397 @@ +/* $FreeBSD: omap.c Exp $ */ + +/* + * Copyright (c) 2010-2011 + * Andrey Eltsov. + * All rights reserved. + * THIS SOFTWARE IS PROVIDED BY ANDREY ELTSOV ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/arm/omap3/omap3.c,v 1.8.2.1.6.1 2010/02/10 00:26:20 kensmith Exp $"); + +#define _ARM32_BUS_DMA_PRIVATE +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define DEBUG_OMAP3_IRQ_ALL +#undef DEBUG_OMAP3_IRQ_ALL + +volatile uint32_t intr_enabled; +uint32_t intr_steer = 0; + +struct omap3_softc *omap3_softc = NULL; + +static int omap3_probe(device_t); +static void omap3_identify(driver_t *, device_t); +static int omap3_attach(device_t); + +static struct { + uint32_t hwbase; + uint32_t size; + uint32_t vbase; +} hwvtrans[] = { + { OMAP3_IO_HWBASE, OMAP3_IO_SIZE, OMAP3_IO_VBASE }, +}; + +int +getvbase(uint32_t hwbase, uint32_t size, uint32_t *vbase) +{ + int i; + + for (i = 0; i < sizeof hwvtrans / sizeof *hwvtrans; i++) { + if (hwbase >= hwvtrans[i].hwbase && + hwbase + size <= hwvtrans[i].hwbase + hwvtrans[i].size) { + *vbase = hwbase - hwvtrans[i].hwbase + hwvtrans[i].vbase; + return (0); + } + } + + return (ENOENT); +} + +struct arm32_dma_range * +bus_dma_get_range(void) +{ + return (NULL); +} + +int +bus_dma_get_range_nb(void) +{ + return (0); +} + +void +arm_mask_irq(uintptr_t nb) +{ + int offset = nb & (~(OMAP3_INT_BITS_PER_REG - 1)); + /*XXX: TODO check for spurious int */ + nb &= (OMAP3_INT_BITS_PER_REG - 1); +#ifdef DEBUG_OMAP3_IRQ + printf("arm_mask_irq offset=0x%x, nb=%d\n",offset,nb); +#endif + bus_space_write_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_INTC_BASE, + OMAP3_INTC_MIR_SET0 + offset, 1 << nb); +} + +void +arm_unmask_irq(uintptr_t nb) +{ + int offset = nb & (~(OMAP3_INT_BITS_PER_REG - 1)); + nb &= (OMAP3_INT_BITS_PER_REG - 1); +#ifdef DEBUG_OMAP3_IRQ + printf("arm_unmask_irq offset=0x%x, nb=%d\n",offset,nb); +#endif + bus_space_write_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_INTC_BASE, + OMAP3_INTC_MIR_CLEAR0 + offset, 1 << nb); +} + +static int prev_irq=-1; + +int +arm_get_next_irq(void) +{ + uint32_t val; +#ifdef DEBUG_OMAP3_IRQ + printf("arm_get_next_irq\n"); +#endif + if(prev_irq == -1) { + val = bus_space_read_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_INTC_BASE, + OMAP3_INTC_SIR); + if(val & OMAP3_SINT_MASK) { + printf("Spurious interrupt detected!\n"); + prev_irq = (-1); + return (prev_irq); + } + + val &= OMAP3_ACTIVEIRQ_MASK; + + bus_space_write_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_INTC_BASE, + OMAP3_INTC_CONTROL,OMAP3_NEW_IRQ); + if(val) { + + prev_irq = (int)val; +#ifdef DEBUG_OMAP3_IRQ_ALL + printf("IRQ %d\n",prev_irq); +#endif + } + else { + prev_irq = (-1); + } + } + else { + prev_irq = -1; + } + + return prev_irq; +} + +void cpu_reset(void) +{ + uint32_t val; + /* Reset OMAP3 using global reset via PRM */ + val = bus_space_read_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_PRM_IOMEM_BASE, + OMAP3_GR_MOD+OMAP3_RM_RSTCTRL); + bus_space_write_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_PRM_IOMEM_BASE, + OMAP3_GR_MOD+OMAP3_RM_RSTCTRL, val | OMAP3_RST_DPLL3); + printf("Reset failed!\n"); + for(;;); +} + +static void +omap3_identify(driver_t *driver, device_t parent) +{ + BUS_ADD_CHILD(parent, 0, "ompio", 0); +} + +static int +omap3_probe(device_t dev) +{ + device_set_desc(dev, "Ti OMAP3xxx"); + return (0); +} +static int omap3_init_intc() +{ + uint32_t val; + val = bus_space_read_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_INTC_BASE,OMAP3_INTC_REVISION) & 0xff; + printf("IRQ: Found an INTC at 0x%p " + "(revision %ld.%ld) with %d interrupts\n", + OMAP3_IO_VBASE+OMAP3_INTC_BASE, val >> 4, val & 0xf, 96); + + val = bus_space_read_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_INTC_BASE, OMAP3_INTC_SYSCONFIG); + val |= 1 << 1; /* soft reset */ + bus_space_write_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_INTC_BASE, OMAP3_INTC_SYSCONFIG,val); + + while (!(bus_space_read_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_INTC_BASE, OMAP3_INTC_SYSSTATUS) & 0x1)) + /* Wait for reset to complete */; + + /* Enable autoidle */ + bus_space_write_4(&omap3_bs_tag, OMAP3_IO_VBASE+OMAP3_INTC_BASE, OMAP3_INTC_SYSCONFIG,0x1); +} + +static int +omap3_attach(device_t dev) +{ + struct omap3_softc *sc; + + sc = device_get_softc(dev); + sc->sc_iot = &omap3_bs_tag; + KASSERT(omap3_softc == NULL, ("omap3_attach called twice?")); + omap3_softc = sc; + omap3_init_intc(); + /*XXX: mask irqs???*/ + + if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, + NULL, NULL, &sc->sc_dmat)) + panic("couldn't create the OMAP3xxx dma tag !"); + + sc->sc_irq_rman.rm_type = RMAN_ARRAY; + sc->sc_irq_rman.rm_descr = "OMAP3 IRQs"; + if (rman_init(&sc->sc_irq_rman) != 0 || + rman_manage_region(&sc->sc_irq_rman, 0, 96) != 0) + panic("omap3_attach: failed to set up IRQ rman"); + + sc->sc_mem_rman.rm_type = RMAN_ARRAY; + sc->sc_mem_rman.rm_descr = "OMAP3 Memory"; + if (rman_init(&sc->sc_mem_rman) != 0 || + rman_manage_region(&sc->sc_mem_rman, 0, ~0) != 0) + panic("omap3_attach: failed to set up memory rman"); + BUS_ADD_CHILD(dev,0,"omap3clk",0); + /* attach wired devices via hints */ + bus_enumerate_hinted_children(dev); + + bus_generic_probe(dev); + bus_generic_attach(dev); + + return (0); +} + +static void +omap3_hinted_child(device_t bus, const char *dname, int dunit) +{ + device_t child; + struct omap3_ivar *ivar; + + child = BUS_ADD_CHILD(bus, 0, dname, dunit); + ivar = OMAP3_IVAR(child); + resource_int_value(dname, dunit, "addr", &ivar->addr); + resource_int_value(dname, dunit, "irq", &ivar->irq); +} + +static device_t +omap3_add_child(device_t dev, int order, const char *name, int unit) +{ + device_t child; + struct omap3_ivar *ivar; + + child = device_add_child_ordered(dev, order, name, unit); + if (child == NULL) + return NULL; + ivar = malloc(sizeof(struct omap3_ivar), M_DEVBUF, M_NOWAIT); + if (ivar == NULL) { + device_delete_child(dev, child); + return NULL; + } + ivar->addr = 0; + ivar->irq = -1; + device_set_ivars(child, ivar); + return child; +} + +static int +omap3_read_ivar(device_t bus, device_t child, int which, u_char *result) +{ + struct omap3_ivar *ivar = OMAP3_IVAR(child); + + switch (which) { + case OMAP3_IVAR_ADDR: + if (ivar->addr != 0) { + *(uint32_t *)result = ivar->addr; + return 0; + } + break; + case OMAP3_IVAR_IRQ: + if (ivar->irq != -1) { + *(int *)result = ivar->irq; + return 0; + } + break; + } + return EINVAL; +} + +static struct resource * +omap3_alloc_resource(device_t dev, device_t child, int type, int *rid, + u_long start, u_long end, u_long count, u_int flags) +{ + struct omap3_softc *sc = device_get_softc(dev); + struct rman *rmanp; + struct resource *rv; + uint32_t vbase, addr; + int irq; + + switch (type) { + case SYS_RES_IRQ: + rmanp = &sc->sc_irq_rman; + /* override per hints */ + if (BUS_READ_IVAR(dev, child, OMAP3_IVAR_IRQ, &irq) == 0) + start = end = irq; + rv = rman_reserve_resource(rmanp, start, end, count, + flags, child); + if (rv != NULL) + rman_set_rid(rv, *rid); + break; + + case SYS_RES_MEMORY: + rmanp = &sc->sc_mem_rman; + /* override per hints */ + if (BUS_READ_IVAR(dev, child, OMAP3_IVAR_ADDR, &addr) == 0) { + start = addr; + end = start + 0x1000; /* XXX */ + } + if (getvbase(start, end - start, &vbase)) + return NULL; + rv = rman_reserve_resource(rmanp, start, end, count, + flags, child); + if (rv != NULL) { + rman_set_rid(rv, *rid); + if (strcmp(device_get_name(child), "uart") == 0) + rman_set_bustag(rv, &omap3_a4x_bs_tag); + else + rman_set_bustag(rv, sc->sc_iot); + rman_set_bushandle(rv, vbase); + } + break; + default: + rv = NULL; + break; + } + return rv; +} + +static int +omap3_setup_intr(device_t dev, device_t child, + struct resource *ires, int flags, driver_filter_t *filt, + driver_intr_t *intr, void *arg, void **cookiep) +{ + + int i; +#ifdef DEBUG_OMAP3_IRQ + printf("omap3_setup_intr\n"); +#endif + BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, + arg, cookiep); + + + for (i = rman_get_start(ires); i <= rman_get_end(ires); i++) { +#ifdef DEBUG_OMAP3_IRQ + printf("omap3_setup_intr arm_unmask_irq(0x%x)\n",i); +#endif + arm_unmask_irq(i); + } + + return (0); +} + +static int +omap3_teardown_intr(device_t dev, device_t child, struct resource *res, + void *cookie) +{ + int i; + + for (i = rman_get_start(res); i <= rman_get_end(res); i++) { + arm_mask_irq(i); + } + return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); +} + +static device_method_t omap3_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, omap3_probe), + DEVMETHOD(device_attach, omap3_attach), + DEVMETHOD(device_identify, omap3_identify), + + /* Bus interface */ + DEVMETHOD(bus_add_child, omap3_add_child), + DEVMETHOD(bus_hinted_child, omap3_hinted_child), + DEVMETHOD(bus_read_ivar, omap3_read_ivar), + + DEVMETHOD(bus_alloc_resource, omap3_alloc_resource), + DEVMETHOD(bus_setup_intr, omap3_setup_intr), + DEVMETHOD(bus_teardown_intr, omap3_teardown_intr), + + {0, 0}, +}; + +static driver_t omap3_driver = { + "ompio", + omap3_methods, + sizeof(struct omap3_softc), +}; +static devclass_t omap3_devclass; + +DRIVER_MODULE(ompio, nexus, omap3_driver, omap3_devclass, 0, 0); diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/omap3_a4x_io.S /usr/src.omap/sys/arm/omap3/omap3_a4x_io.S --- /usr/src/sys/arm/omap3/omap3_a4x_io.S 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/omap3_a4x_io.S 2010-07-04 20:29:33.000000000 +0400 @@ -0,0 +1,142 @@ +/* $NetBSD: ixp425_a4x_io.S,v 1.2 2005/12/11 12:16:51 christos Exp $ */ + +/* + * Copyright 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Steve C. Woodford for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * There are simple bus space functions for IO registers mapped at + * 32-bit aligned positions. offset is multiplied by 4. + * + * Based loosely on pxa2x0_a2x_io.S + */ + +#include +__FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/ixp425_a4x_io.S,v 1.1.14.1 2010/02/10 00:26:20 kensmith Exp $"); + +/* + * bus_space I/O functions with offset*4 + */ + +/* + * Read single + */ +ENTRY(a4x_bs_r_1) + ldr r0, [r1, r2, LSL #2] + and r0, r0, #0xff + mov pc, lr + +ENTRY(a4x_bs_r_2) + ldr r0, [r1, r2, LSL #2] + mov r1, #0xff + orr r1, r1, r1, lsl #8 + and r0, r0, r1 + mov pc, lr + +ENTRY(a4x_bs_r_4) + ldr r0, [r1, r2, LSL #2] + mov pc, lr + +/* + * Write single + */ +ENTRY(a4x_bs_w_1) + and r3, r3, #0xff + str r3, [r1, r2, LSL #2] + mov pc, lr + +ENTRY(a4x_bs_w_2) + mov r0, #0xff + orr r0, r0, r0, lsl #8 + and r3, r3, r0 + str r3, [r1, r2, LSL #2] + mov pc, lr + +ENTRY(a4x_bs_w_4) + str r3, [r1, r2, LSL #2] + mov pc, lr + +/* + * Read multiple + */ +ENTRY(a4x_bs_rm_1) + add r0, r1, r2, lsl #2 + ldr r2, [sp, #0] + mov r1, r3 + teq r2, #0 + moveq pc, lr +1: ldr r3, [r0] + subs r2, r2, #1 + strb r3, [r1], #1 + bne 1b + mov pc, lr + +ENTRY(a4x_bs_rm_2) + add r0, r1, r2, lsl #2 + ldr r2, [sp, #0] + mov r1, r3 + teq r2, #0 + moveq pc, lr +1: ldr r3, [r0] + subs r2, r2, #1 + strh r3, [r1], #2 + bne 1b + mov pc, lr + +/* + * Write multiple + */ +ENTRY(a4x_bs_wm_1) + add r0, r1, r2, lsl #2 + ldr r2, [sp, #0] + mov r1, r3 + teq r2, #0 + moveq pc, lr +1: ldrb r3, [r1], #1 + subs r2, r2, #1 + str r3, [r0] + bne 1b + mov pc, lr + +ENTRY(a4x_bs_wm_2) + add r0, r1, r2, lsl #2 + ldr r2, [sp, #0] + mov r1, r3 + teq r2, #0 + moveq pc, lr +1: ldrh r3, [r1], #2 + subs r2, r2, #1 + str r3, [r0] + bne 1b + mov pc, lr diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/omap3_a4x_space.c /usr/src.omap/sys/arm/omap3/omap3_a4x_space.c --- /usr/src/sys/arm/omap3/omap3_a4x_space.c 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/omap3_a4x_space.c 2011-01-08 18:12:38.000000000 +0300 @@ -0,0 +1,114 @@ +/* $NetBSD: ixp425_a4x_space.c,v 1.2 2005/12/11 12:16:51 christos Exp $ */ + +/* + * Copyright 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Steve C. Woodford for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Bus space tag for 8/16-bit devices on 32-bit bus. + * all registers are located at the address of multiple of 4. + * + * Based on pxa2x0_a4x_space.c + */ + +#include +__FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/ixp425_a4x_space.c,v 1.1.4.1.6.1 2010/02/10 00:26:20 kensmith Exp $"); + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include +/* Prototypes for all the bus_space structure functions */ +bs_protos(a4x); +bs_protos(generic); +bs_protos(generic_armv4); + +struct bus_space omap3_a4x_bs_tag = { + /* cookie */ + .bs_cookie = (void *) 0, + + /* mapping/unmapping */ + .bs_map = generic_bs_map, + .bs_unmap = generic_bs_unmap, + .bs_subregion = generic_bs_subregion, + + /* allocation/deallocation */ + .bs_alloc = generic_bs_alloc, /* XXX not implemented */ + .bs_free = generic_bs_free, /* XXX not implemented */ + + /* barrier */ + .bs_barrier = generic_bs_barrier, + + /* read (single) */ + .bs_r_1 = a4x_bs_r_1, + .bs_r_2 = a4x_bs_r_2, + .bs_r_4 = a4x_bs_r_4, + + /* read multiple */ + .bs_rm_1 = a4x_bs_rm_1, + .bs_rm_2 = a4x_bs_rm_2, + + /* read region */ + /* XXX not implemented */ + + /* write (single) */ + .bs_w_1 = a4x_bs_w_1, + .bs_w_2 = a4x_bs_w_2, + .bs_w_4 = a4x_bs_w_4, + + /* write multiple */ + .bs_wm_1 = a4x_bs_wm_1, + .bs_wm_2 = a4x_bs_wm_2, + + /* write region */ + /* XXX not implemented */ + + /* set multiple */ + /* XXX not implemented */ + + /* set region */ + /* XXX not implemented */ + + /* copy */ + /* XXX not implemented */ +}; diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/omap3_regs.h /usr/src.omap/sys/arm/omap3/omap3_regs.h --- /usr/src/sys/arm/omap3/omap3_regs.h 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/omap3_regs.h 2011-01-25 21:17:20.000000000 +0300 @@ -0,0 +1,220 @@ +#ifndef __OMAP3_regs_inluded +#define __OMAP3_regs_inluded +#define OMAP3_IO_VBASE 0xe0000000 +#define OMAP3_IO_HWBASE 0x48000000 +#define OMAP3_IO_SIZE 0x01100000 +/* CM */ +#define OMAP3_CM_BASE 0x4A00 +#define OMAP3_CM_CLKSEL_MPU 0x140 +#define OMAP3_CM_FCLKEN1_CORE 0x00 +#define OMAP3_CM_FCLKEN2_CORE 0x204 +#define OMAP3_CM_ICLKEN1_CORE 0x10 +#define OMAP3_CM_ICLKEN2_CORE 0x14 +#define OMAP3_CM_CLKSEL2_CORE 0x244 +/* PRM */ +#define OMAP3_PRM_IOMEM_BASE 0x306800 +#define OMAP3_RM_RSTCTRL 0x0050 +#define OMAP3_RST_DPLL3 (1 << 2) +#define OMAP3_GR_MOD 0xa00 +/* IC */ +#define OMAP3_INTC_BASE 0x200000 +#define OMAP3_INTC_REVISION 0x0000 +#define OMAP3_INTC_SYSCONFIG 0x0010 +#define OMAP3_INTC_SYSSTATUS 0x0014 +#define OMAP3_INTC_SIR 0x0040 +#define OMAP3_INTC_CONTROL 0x0048 +#define OMAP3_INTC_MIR_CLEAR0 0x0088 +#define OMAP3_INTC_MIR_SET0 0x008c +#define OMAP3_INTC_PENDING_IRQ0 0x0098 +#define OMAP3_INT_BITS_PER_REG 32 +#define OMAP3_ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ +#define OMAP3_SINT_MASK 0xffffff80 /* Spurious int mask */ +#define OMAP3_NEW_IRQ 0x01 +#define OMAP3_UART1_BASE 0x06a000 +#define OMAP3_UART2_BASE 0x06c000 +#define OMAP3_UART3_BASE 0x1020000 +#define OMAP3_CONSOLE_BASE OMAP3_UART3_BASE +#define OMAP3_UART_FREQ 48000000 +#define OMAP3_UART_IER 4 +#define OMAP3_UART_IER_RTOIE 1 + +/* timers */ +#define __BIT(__n) \ + (((uintmax_t)(__n) >= NBBY * sizeof(uintmax_t)) ? 0 : ((uintmax_t)1 << (uintmax_t)(__n))) +#define MPU_CNTL_TIMER 0x00 +#define MPU_FREE (1<<6) +#define MPU_CLOCK_ENABLE (1<<5) +#define MPU_PTV_SHIFT 2 +#define MPU_AR (1<<1) +#define MPU_ST (1<<0) +#define MPU_LOAD_TIMER 0x04 +#define MPU_READ_TIMER 0x08 +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT2 __BIT(4) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT3 __BIT(5) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT4 __BIT(6) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT5 __BIT(7) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT6 __BIT(8) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT7 __BIT(9) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT8 __BIT(10) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT9 __BIT(11) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT10 __BIT(12) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT11 __BIT(13) +#define OMAP2_CM_FCLKEN1_CORE_EN_GPT12 __BIT(14) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT2 __BIT(4) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT3 __BIT(5) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT4 __BIT(6) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT5 __BIT(7) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT6 __BIT(8) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT7 __BIT(9) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT8 __BIT(10) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT9 __BIT(11) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT10 __BIT(12) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT11 __BIT(13) +#define OMAP2_CM_ICLKEN1_CORE_EN_GPT12 __BIT(14) +#define OMAP2_CM_CLKSEL2_CORE_GPTn(n, v) \ + (((v) & 0x3) << (2 + ((((n) - 2) << 1)))) +#define CLKSEL2_CORE_GPT_FUNC_32K_CLK 0x0 +#define CLKSEL2_CORE_GPT_SYS_CLK 0x1 +#define CLKSEL2_CORE_GPT_ALT_CLK 0x2 +#define CLKSEL2_CORE_GPT_ALT_RESV 0x3 + +#define GPT1_BASE 0x48318000 +#define GPT2_BASE 0x49032000 +#define GPT3_BASE 0x49034000 +#define GPT4_BASE 0x49036000 +#define GPT5_BASE 0x49038000 +#define GPT6_BASE 0x4903A000 +#define GPT7_BASE 0x4903C000 +#define GPT8_BASE 0x4903E000 +#define GPT9_BASE 0x49040000 +#define GPT10_BASE 0x48086000 +#define GPT11_BASE 0x48088000 +#define GPT12_BASE 0x48304000 + +/*IRQs */ + +#define IRQ_EMUINT 0 /* MPU emulation (1) */ +#define IRQ_COMMRX 1 /* MPU emulation (1) */ +#define IRQ_COMMTX 2 /* MPU emulation (1) */ +#define IRQ_BENCH 3 /* MPU emulation (1) */ +#define IRQ_XTI 4 /* (2430) XTI module (2) (3) */ +#define IRQ_MCBSP2_ST 4 /* (3530) Sidetone MCBSP2 overflow */ +#define IRQ_XTI_WKUP 5 /* (2430) XTI module (3) */ +#define IRQ_MCBSP3_ST 5 /* (3530) Sidetone MCBSP3 overflow */ +#define IRQ_SSM_ABORT 6 /* (2430) MPU subsystem secure state-machine abort */ +#define IRQ_SYS_nIRQ0 7 /* External interrupt (active low) */ +#define IRQ_D2D_FW_STACKED 8 /* (2430) Occurs when modem does a security violation and has been automatically put DEVICE_SECURITY [0] under reset. */ +#define IRQ_RSVD8 8 /* (3530) */ +#define IRQ_SMX_DBG 9 /* (3530) SMX error for debug */ +#define IRQ_RSVD9 9 /* Reserved */ +#define IRQ_SMX_APP 10 /* (3530) SMX error for application */ +#define IRQ_L3 10 /* (2420) L2 interconnect (transaction error) */ +#define IRQ_SMX_APE_IA_ARM1136 10 /* (2430) Error flag for reporting application and unknown errors from SMX-APE (4) rd_wrSError_o */ +#define IRQ_PRCM_MPU 11 /* PRCM */ +#define IRQ_SDMA0 12 /* System DMA interrupt request 0 (5) */ +#define IRQ_SDMA1 13 /* System DMA interrupt request 1 (5) */ +#define IRQ_SDMA2 14 /* System DMA interrupt request 2 */ +#define IRQ_SDMA3 15 /* System DMA interrupt request 3 */ +#define IRQ_McBSP2_COMMON 16 /* (2430) McBSP2 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */ +#define IRQ_McBSP3_COMMON 17 /* (2430) McBSP3 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */ +#define IRQ_McBSP4_COMMON 18 /* (2430) McBSP4 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */ +#define IRQ_SR1 18 /* (3530) SmartReflex 1 */ +#define IRQ_McBSP5_COMMON 19 /* (2430) McBSP5 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */ +#define IRQ_SR2 19 /* (3530) SmartReflex 2 */ +#define IRQ_GPMC 20 /* General-purpose memory controller module */ +#define IRQ_GFX 21 /* (2430) 2D/3D graphics module */ +#define IRQ_RSVD22 22 /* Reserved */ +#define IRQ_MCBSP3 22 /* McBSP module 3 */ +#define IRQ_EAC 23 /* Audio Controller (2420) */ +#define IRQ_MCBSP4 22 /* McBSP module 4 */ +#define IRQ_CAM0 24 /* Camera interface interrupt request 0 */ +#define IRQ_DSS 25 /* Display subsystem module (5) */ +#define IRQ_MAIL_U0_MPU 26 /* Mailbox user 0 interrupt request */ +#define IRQ_DSP_UMA 27 /* (2420) DSP UMA core s/w interrupt */ +#define IRQ_MCBSP5 27 /* McBSP module 5 */ +#define IRQ_DSP_MMU 28 /* (2420) DSP MMU interrupt */ +#define IRQ_IVA2_MMU 28 /* (2430) IVA2 MMU interrupt */ +#define IRQ_GPIO1_MPU 29 /* GPIO module 1 (5) (3) */ +#define IRQ_GPIO2_MPU 30 /* GPIO module 2 (5) (3) */ +#define IRQ_GPIO3_MPU 31 /* GPIO module 3 (5) (3) */ +#define IRQ_GPIO4_MPU 32 /* GPIO module 4 (5) (3) */ +#define IRQ_GPIO5_MPU 33 /* (2430/2530) GPIO module 5 */ +#define IRQ_GPIO6_MPU 34 /* (3530) GPIO module 5 */ +#define IRQ_MAIL_U2_MPU 34 /* (2420) Mailbox user 2 */ +#define IRQ_WDT3 35 /* (2420) Watchdog timer module 3 overflow */ +#define IRQ_USIM 35 /* (3530) USIM interrupt (HS devices only) */ +#define IRQ_WDT4 36 /* (2420) Watchdog timer module 4 overflow */ +#define IRQ_WDT3_3530 36 /* (3530) Watchdog timer module 3 overflow */ +#define IRQ_IVA2WDT 36 /* (2430) IVA2 watchdog timer interrupt */ +#define IRQ_GPT1 37 /* General-purpose timer module 1 */ +#define IRQ_GPT2 38 /* General-purpose timer module 2 */ +#define IRQ_GPT3 39 /* General-purpose timer module 3 */ +#define IRQ_GPT4 40 /* General-purpose timer module 4 */ +#define IRQ_GPT5 41 /* General-purpose timer module 5 (5) */ +#define IRQ_GPT6 42 /* General-purpose timer module 6 (5) (3) */ +#define IRQ_GPT7 43 /* General-purpose timer module 7 (5) (3) */ +#define IRQ_GPT8 44 /* General-purpose timer module 8 (5) (3) */ +#define IRQ_GPT9 45 /* General-purpose timer module 9 (3) */ +#define IRQ_GPT10 46 /* General-purpose timer module 10 */ +#define IRQ_GPT11 47 /* General-purpose timer module 11 (PWM) */ +#define IRQ_GPT12 48 /* General-purpose timer module 12 (PWM) */ +#define IRQ_SPI4_IRQ 48 /* (3530) McSPI module 4 */ +#define IRQ_RSVD49 49 /* Reserved */ +#define IRQ_SHA1MD5_2 49 /* (350) SHA-1/MD5 crypto-accelerator 2 */ +#define IRQ_PKA 50 /* (2430) PKA crypto-accelerator */ +#define IRQ_SHA1MD5 51 /* (2430) SHA-1/MD5 crypto-accelerator */ +#define IRQ_RNG 52 /* (2430) RNG module */ +#define IRQ_MG 53 /* (2430) MG function (5) */ +#define IRQ_MCBSP4_TX 54 /* (2430) McBSP module 4 transmit (5) */ +#define IRQ_MCBSP4_RX 55 /* (2430) McBSP module 4 receive (5) */ +#define IRQ_I2C1 56 /* I2C module 1 */ +#define IRQ_I2C2 57 /* I2C module 2 */ +#define IRQ_HDQ 58 /* HDQ/1-wire */ +#define IRQ_McBSP1_TX 59 /* McBSP module 1 transmit (5) */ +#define IRQ_McBSP1_RX 60 /* McBSP module 1 receive (5) */ +#define IRQ_MCBSP1_OVR 61 /* (2430) McBSP module 1 overflow interrupt (5) */ +#define IRQ_I2C3 61 /* (3530) I2C module 3 */ +#define IRQ_McBSP2_TX 62 /* McBSP module 2 transmit (5) */ +#define IRQ_McBSP2_RX 63 /* McBSP module 2 receive (5) */ +#define IRQ_McBSP1_COMMON 64 /* (2430) McBSP1 common IRQ. This IRQ regroups all the interrupt sources of the McBSPLP. Not backward compatible with previous McBSP. */ +#define IRQ_FPKA_ERROR 64 /* (3530) PKA crypto-accelerator */ +#define IRQ_SPI1 65 /* McSPI module 1 */ +#define IRQ_SPI2 66 /* McSPI module 2 */ +#define IRQ_SSI_P1_MPU0 67 /* (2430) Dual SSI port 1 interrupt request 0 (5) */ +#define IRQ_SSI_P1_MPU1 68 /* (2430) Dual SSI port 1 interrupt request 1 (5) */ +#define IRQ_SSI_P2_MPU0 69 /* (2430) Dual SSI port 2 interrupt request 0 (5) */ +#define IRQ_SSI_P2_MPU1 70 /* (2430) Dual SSI port 2 interrupt request 1 (5) */ +#define IRQ_SSI_GDD_MPU 71 /* (2430) Dual SSI GDD (5) */ +#define IRQ_UART1 72 /* UART module 1 (3) */ +#define IRQ_UART2 73 /* UART module 2 (3) */ +#define IRQ_UART3 74 /* UART module 3 (also infrared) (5) (3) */ +#define IRQ_PBIAS 75 /* (3530) Merged intr. for PBIASite 1 & 2 */ +#define IRQ_USB_GEN 75 /* USB device general interrupt (3) */ +#define IRQ_OCHI 76 /* (3530) OHCI controller HSUSB MP Host Interrupt */ +#define IRQ_USB_NISO 76 /* USB device non-ISO (3) */ +#define IRQ_EHCI 77 /* (3530) EHCI controller HSUSB MP Host Interrupt */ +#define IRQ_USB_ISO 77 /* USB device ISO (3) */ +#define IRQ_TLL 78 /* (3530) HSUSB MP TLL interrupt (3) */ +#define IRQ_USB_HGEN 78 /* USB host general interrupt (3) */ +#define IRQ_PARTHASH 79 /* (3530) SHA2/MD5 accel 1 */ +#define IRQ_USB_HSOF 79 /* USB host start-of-frame (3) */ +#define IRQ_USB_OTG 80 /* USB OTG */ +#define IRQ_MCBSP5_TX 81 /* (2430/3530) McBSP module 5 transmit (5) */ +#define IRQ_MCBSP5_RX 82 /* (2430/3530) McBSP module 5 receive (5) */ +#define IRQ_MMC1 83 /* (2430/3530) MMC/SD module 1 (3) */ +#define IRQ_MS 84 /* (2430/3530) MS-PRO module */ +#define IRQ_FAC 85 /* (2430) FAC module */ +#define IRQ_MMC2 86 /* (2430/3530) MMC/SD module 2 */ +#define IRQ_ARM11_ICR 87 /* (2430) ARM11 ICR interrupt */ +#define IRQ_MPU_ICR 87 /* (3530) MPU ICR interrupt */ +#define IRQ_D2DFRINT 88 /* (2430) From 3G coprocessor hardware when used in chassis mode */ +#define IRQ_MCBSP3_TX 89 /* (2430) McBSP module 3 transmit (5) */ +#define IRQ_MCBSP3_RX 90 /* (2430) McBSP module 3 receive (5) */ +#define IRQ_SPI3 91 /* (2430) Module McSPI 3 */ +#define IRQ_HS_USB_MC 92 /* (2430) Module HS USB OTG controller (3) */ +#define IRQ_HS_USB_MC 92 /* (2430) Module HS USB OTG controller (3) */ +#define IRQ_Carkit 94 /* (2430) Carkit interrupt when the external HS USB transceiver is used in carkit mode (2) */ +#define IRQ_MMC3 94 /* (3530) MMC/SD module 3 */ +#define IRQ_GPT12_3530 95 /* (3530) GPT12 */ +#define OMAP3_REG_SIZE 0x1000 +#endif diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/omap3_space.c /usr/src.omap/sys/arm/omap3/omap3_space.c --- /usr/src/sys/arm/omap3/omap3_space.c 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/omap3_space.c 2011-01-09 00:42:37.000000000 +0300 @@ -0,0 +1,130 @@ +/* $NetBSD: ixp425_space.c,v 1.6 2006/04/10 03:36:03 simonb Exp $ */ + +/* + * Copyright (c) 2003 + * Ichiro FUKUHARA . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Ichiro FUKUHARA. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/ixp425_space.c,v 1.1.4.1.6.1 2010/02/10 00:26:20 kensmith Exp $"); + +/* + * bus_space I/O functions for omap3 + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include + + + +/* Proto types for all the bus_space structure functions */ +bs_protos(generic); +bs_protos(generic_armv4); + +struct bus_space omap3_bs_tag = { + /* cookie */ + .bs_cookie = (void *) 0, + + /* mapping/unmapping */ + .bs_map = generic_bs_map, + .bs_unmap = generic_bs_unmap, + .bs_subregion = generic_bs_subregion, + + /* allocation/deallocation */ + .bs_alloc = generic_bs_alloc, + .bs_free = generic_bs_free, + + /* barrier */ + .bs_barrier = generic_bs_barrier, + + /* read (single) */ + .bs_r_1 = generic_bs_r_1, + .bs_r_2 = NULL, + .bs_r_4 = generic_bs_r_4, + .bs_r_8 = NULL, + + /* read multiple */ + .bs_rm_1 = generic_bs_rm_1, + .bs_rm_2 = NULL, + .bs_rm_4 = generic_bs_rm_4, + .bs_rm_8 = NULL, + + /* read region */ + .bs_rr_1 = generic_bs_rr_1, + .bs_rr_2 = NULL, + .bs_rr_4 = generic_bs_rr_4, + .bs_rr_8 = NULL, + + /* write (single) */ + .bs_w_1 = generic_bs_w_1, + .bs_w_2 = NULL, + .bs_w_4 = generic_bs_w_4, + .bs_w_8 = NULL, + + /* write multiple */ + .bs_wm_1 = generic_bs_wm_1, + .bs_wm_2 = NULL, + .bs_wm_4 = generic_bs_wm_4, + .bs_wm_8 = NULL, + + /* write region */ + .bs_wr_1 = generic_bs_wr_1, + .bs_wr_2 = NULL, + .bs_wr_4 = generic_bs_wr_4, + .bs_wr_8 = NULL, + + /* set multiple */ + /* XXX not implemented */ + + /* set region */ + .bs_sr_1 = NULL, + .bs_sr_2 = NULL, + .bs_sr_4 = generic_bs_sr_4, + .bs_sr_8 = NULL, + + /* copy */ + .bs_c_1 = NULL, + .bs_c_2 = NULL, + .bs_c_4 = NULL, + .bs_c_8 = NULL, +}; diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/omap3_timer.c /usr/src.omap/sys/arm/omap3/omap3_timer.c --- /usr/src/sys/arm/omap3/omap3_timer.c 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/omap3_timer.c 2011-01-26 22:47:27.000000000 +0300 @@ -0,0 +1,503 @@ +/* $FreeBSD: omap3_timer.c $ */ + +/* + * Copyright (c) 2010-2011 + * Andrey Eltsov. + * All rights reserved. + * Parts are from omap2_mputmr.c + * THIS SOFTWARE IS PROVIDED BY ANDREY ELTSOV ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* $NetBSD: omap2_mputmr.c,v 1.3 2010/06/19 19:44:58 matt Exp $ */ + +/* + * OMAP 2430 GP timers + */ + +/* + * Based on i80321_timer.c and arch/arm/sa11x0/sa11x0_ost.c + * + * Copyright (c) 1997 Mark Brinicombe. + * Copyright (c) 1997 Causality Limited. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by IWAMOTO Toshihiro and Ichiro FUKUHARA. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Copyright (c) 2001, 2002 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +__FBSDID("$FreeBSD: src/sys/arm/omap3/omap3_timer.c $"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_DEBUG_INTR +#undef TIMER_DEBUG_INTR + +#ifndef OMAP_MPU_TIMER_CLOCK_FREQ +#error Specify the timer frequency in Hz with the OMAP_MPU_TIMER_CLOCK_FREQ option. +#endif + + +static uint32_t counts_per_usec, counts_per_hz; +typedef struct { + uint32_t gptn; + bus_addr_t offset; + uint32_t intr; + uint32_t clksel2; + uint32_t fclken1; + uint32_t iclken1; +} gptimer_instance_t; + +#define GPT_ENTRY(n) { \ + .gptn = (n), \ + .offset = GPT ## n ## _BASE - OMAP3_IO_HWBASE, \ + .intr = IRQ_ ## GPT ## n, \ + .clksel2 = OMAP2_CM_CLKSEL2_CORE_GPTn(n, \ + CLKSEL2_CORE_GPT_SYS_CLK), \ + .fclken1 = OMAP2_CM_FCLKEN1_CORE_EN_GPT ## n, \ + .iclken1 = OMAP2_CM_ICLKEN1_CORE_EN_GPT ## n, \ + } +/* callback functions for intr_functions */ +int omap3clk_intr(void *); +void +calc_timer_factors(int ints_per_sec, timer_factors *tf); + +/* GPT2 will be used */ +static gptimer_instance_t gpt_timer=GPT_ENTRY(2); + +struct omap3clk_softc { + device_t sc_dev; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; + uint32_t intr; +}; + +static unsigned omap3_timer_get_timecount(struct timecounter *tc); + + +static struct omap3clk_softc *omap3clk_sc = NULL; + + +static struct timecounter omap3_timer_timecounter = { + omap3_timer_get_timecount, /* get_timecount */ + NULL, /* no poll_pps */ + 0xffffffff, /* counter_mask */ + OMAP_MPU_TIMER_CLOCK_FREQ, /* frequency */ + "OMAP3 Timer", /* name */ + 100, /* quality */ +}; + +static int +omap3clk_probe(device_t dev) +{ + device_set_desc(dev, "OMAP3 Timer"); + return (0); +} + +static int +omap3clk_attach(device_t dev) +{ + struct omap3clk_softc *sc = device_get_softc(dev); + struct omap3_softc *sa = device_get_softc(device_get_parent(dev)); + omap3clk_sc = sc; + + sc->sc_dev = dev; + sc->sc_iot = sa->sc_iot; + sc->sc_ioh = OMAP3_IO_VBASE+gpt_timer.offset; + sc->intr = gpt_timer.intr; + printf("%s: sc_ioh = 0x%x, sc->intr = 0x%x\n",__func__,sc->sc_ioh,sc->intr); + return (0); +} + +static device_method_t omap3clk_methods[] = { + DEVMETHOD(device_probe, omap3clk_probe), + DEVMETHOD(device_attach, omap3clk_attach), + {0, 0}, +}; + +static driver_t omap3clk_driver = { + "omap3clk", + omap3clk_methods, + sizeof(struct omap3clk_softc), +}; +static devclass_t omap3clk_devclass; + +DRIVER_MODULE(omap3clk, ompio, omap3clk_driver, omap3clk_devclass, 0, 0); + +static inline void + _timer_intr_dis(struct omap3clk_softc *sc) +{ + bus_space_write_4(sc->sc_iot, sc->sc_ioh, TIER, 0); +} + +static inline void +_timer_intr_enb(struct omap3clk_softc *sc) +{ + bus_space_write_4(sc->sc_iot, sc->sc_ioh, TIER, TIER_OVF_IT_ENA); +} + +static inline uint32_t +_timer_intr_sts(struct omap3clk_softc *sc) +{ + return bus_space_read_4(sc->sc_iot, sc->sc_ioh, TISR); +} + +static inline void +_timer_intr_ack(struct omap3clk_softc *sc) +{ + bus_space_write_4(sc->sc_iot, sc->sc_ioh, TISR, TIER_OVF_IT_ENA); +} + +static inline uint32_t +_timer_read(struct omap3clk_softc *sc) +{ + return bus_space_read_4(sc->sc_iot, sc->sc_ioh, TCRR); +} + +static inline void +_timer_stop(struct omap3clk_softc *sc) +{ + uint32_t r; + r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, TCLR); + r &= ~TCLR_ST; + bus_space_write_4(sc->sc_iot, sc->sc_ioh, TCLR, r); +} + +static inline void +_timer_reload(struct omap3clk_softc *sc, uint32_t val) +{ + bus_space_write_4(sc->sc_iot, sc->sc_ioh, TLDR, val); + bus_space_write_4(sc->sc_iot, sc->sc_ioh, TCRR, val); +} + +static inline void +_timer_start(struct omap3clk_softc *sc, timer_factors *tfp) +{ + uint32_t r=0; + + if (tfp->ptv != 0) { + r |= TCLR_PRE(1); + r |= (TCLR_PTV(tfp->ptv - 1) & TCLR_PTV_MASK); + } + r |= (TCLR_CE | TCLR_AR | TCLR_ST); + + bus_space_write_4(sc->sc_iot, sc->sc_ioh, TCLR, r); +} + +static void +setclockrate(struct omap3clk_softc *sc, int schz) +{ + timer_factors tf; + _timer_stop(sc); + calc_timer_factors(schz, &tf); + _timer_reload(sc, tf.reload); + _timer_start(sc, &tf); +} + +static unsigned +omap3_timer_get_timecount(struct timecounter *tc) +{ + uint32_t ret; + if (omap3clk_sc == NULL) + panic("get_timecount: The timer must be initialized sooner."); + ret = _timer_read(omap3clk_sc); + return (ret); +} + +/* + * cpu_initclocks: + * + * Initialize the clock and get them going. + */ +void +cpu_initclocks(void) +{ + struct omap3clk_softc* sc = omap3clk_sc; + struct resource *irq; + timer_factors tf; + device_t dev; + u_int oldirqstate; + int rid = 0; + void *ihl; +#ifdef TIMER_DEBUG + uint32_t val,ii; +#endif + if(sc == NULL) { + panic("cpu_initclocks: : The timer must be initialized sooner."); + } + dev = sc->sc_dev; + tick = 1000000 / hz; /* number of microseconds between interrupts */ + + /* + * We only have one timer available; stathz and profhz are + * always left as 0 (the upper-layer clock code deals with + * this situation). + */ + + if (stathz != 0) + printf("Cannot get %d Hz statclock\n", stathz); + stathz = 0; + + if (profhz != 0) + printf("Cannot get %d Hz profclock\n", profhz); + profhz = 0; + +#ifdef TIMER_DEBUG + printf("OMAP MPU Timer: ioh 0x%x\n",sc->sc_ioh); +#endif + printf("OMAP timer enabled\n"); + /* Stop the timer from counting, but keep the timer module working. */ + bus_space_write_4(sc->sc_iot, sc->sc_ioh, MPU_CNTL_TIMER, + MPU_CLOCK_ENABLE); + + calc_timer_factors(hz, &tf); + counts_per_hz = tf.reload + 1; + counts_per_usec = tf.counts_per_usec; +#ifdef TIMER_DEBUG + printf("OMAP timer tf.reload=0x%x\n",tf.reload); +#endif + /* Set the reload value. */ + bus_space_write_4(sc->sc_iot, sc->sc_ioh, MPU_LOAD_TIMER, tf.reload); + /* Set the PTV and the other required bits and pieces. */ + bus_space_write_4(sc->sc_iot, sc->sc_ioh, MPU_CNTL_TIMER, + ( MPU_CLOCK_ENABLE + | (tf.ptv << MPU_PTV_SHIFT) + | MPU_AR + | MPU_ST)); + /* The clock is now running, but is not generating interrupts. */ +#ifdef TIMER_DEBUG + printf("Before disable_interrupts\n"); +#endif + oldirqstate = disable_interrupts(I32_bit); +#ifdef TIMER_DEBUG + printf("oldirqstate=0x%x\n",oldirqstate); +#endif + /* reload value */ + setclockrate(sc, hz); + irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, sc->intr, + sc->intr, 1, RF_ACTIVE); + if (!irq) + panic("Unable to setup the clock irq handler.\n"); + else + bus_setup_intr(dev, irq, INTR_TYPE_CLK, omap3clk_intr, NULL, + NULL, &ihl); + + /* Set up the new clock parameters. */ + /* Timer enable */ + _timer_intr_enb(sc); + tc_init(&omap3_timer_timecounter); + restore_interrupts(oldirqstate); + rid = 0; +#ifdef TIMER_DEBUG + for(ii=0;ii<100;ii++) { + val = _timer_read(sc); + printf("val=0x%x\n",val); + } +#endif + +} +/* + * DELAY: + * + * Delay for at least N microseconds. + */ +void +DELAY(int n) +{ + uint32_t cur, last, delta, usecs; + + if (omap3clk_sc == NULL) { + /* panic("DELAY:The timer must be initialized sooner"); */ + for(cur=0; cur< 10000; cur++) { + } + return; + } + /* + * This works by polling the timer and counting the + * number of microseconds that go by. + */ + last = _timer_read(omap3clk_sc); + + delta = usecs = 0; + + while (n > usecs) { + cur = _timer_read(omap3clk_sc); + + /* Check to see if the timer has wrapped around. */ + if (last < cur) + delta += (last + (counts_per_hz - cur)); + else + delta += (last - cur); + + last = cur; + + if (delta >= counts_per_usec) { + usecs += delta / counts_per_usec; + delta %= counts_per_usec; + } + } +} + +/* + * OVF_Rate = + * (0xFFFFFFFF - GPTn.TLDR + 1) * (timer functional clock period) * PS + */ +void +calc_timer_factors(int ints_per_sec, timer_factors *tf) +{ + uint32_t ptv_power; /* PS */ + uint32_t count_freq; + const uint32_t us_per_sec = 1000000; + + if (ints_per_sec == 0) { + /* + * When ints_per_sec equal to zero there is mean full range + * timer usage. Nevertheless autoreload mode is still enabled. + */ + tf->ptv = 0; + tf->reload = 0; + tf->counts_per_usec = OMAP_MPU_TIMER_CLOCK_FREQ / us_per_sec; + return; + } + + + tf->ptv = 8; + for (;;) { + ptv_power = 1 << tf->ptv; + count_freq = OMAP_MPU_TIMER_CLOCK_FREQ; + count_freq /= hz; + count_freq /= ptv_power; + tf->reload = -count_freq; + tf->counts_per_usec = count_freq / us_per_sec; + if ((tf->reload * ptv_power * ints_per_sec + == OMAP_MPU_TIMER_CLOCK_FREQ) + && (tf->counts_per_usec * ptv_power * us_per_sec + == OMAP_MPU_TIMER_CLOCK_FREQ)) + { /* Exact match. Life is good. */ + /* Currently reload is MPU_LOAD_TIMER+1. Fix it. */ + tf->reload--; + return; + } + if (tf->ptv == 0) { + tf->counts_per_usec++; + return; + } + tf->ptv--; + } +} + +/* + * omap3clk_intr: + * + * Handle the hardclock interrupt. + */ +int +omap3clk_intr(void *arg) +{ + struct omap3clk_softc* sc = omap3clk_sc; + struct trapframe *frame = arg; +#ifdef TIMER_DEBUG_INTR + printf("clk\n"); +#endif + _timer_intr_ack(sc); + hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); + return (FILTER_HANDLED); +} + +void +cpu_startprofclock(void) +{ +} + +void +cpu_stopprofclock(void) +{ +} diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/omap3var.h /usr/src.omap/sys/arm/omap3/omap3var.h --- /usr/src/sys/arm/omap3/omap3var.h 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/omap3var.h 2011-01-08 18:11:46.000000000 +0300 @@ -0,0 +1,77 @@ +/* $NetBSD: ixp425var.h,v 1.10 2006/04/10 03:36:03 simonb Exp $ */ + +/* + * Copyright (c) 2003 + * Ichiro FUKUHARA . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Ichiro FUKUHARA. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/arm/xscale/ixp425/ixp425var.h,v 1.4.10.1 2010/02/10 00:26:20 kensmith Exp $ + * + */ + +#ifndef _OMAP3VAR_H_ +#define _OMAP3VAR_H_ + +#include +#include + +#include + +#include + +struct omap3_softc { + device_t sc_dev; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_gpio_ioh; + bus_space_handle_t sc_exp_ioh; + + u_int32_t sc_intrmask; + + struct rman sc_irq_rman; + struct rman sc_mem_rman; + bus_dma_tag_t sc_dmat; +}; +extern struct bus_space omap3_bs_tag; +extern struct bus_space omap3_a4x_bs_tag; + +int getvbase(uint32_t, uint32_t, uint32_t *); + +struct omap3_ivar { + uint32_t addr; + int irq; +}; +#define OMAP3_IVAR(d) ((struct omap3_ivar *) device_get_ivars(d)) + +enum { + OMAP3_IVAR_ADDR, /* base physical address */ + OMAP3_IVAR_IRQ /* irq/gpio pin assignment */ +}; + +#endif /* _IXP425VAR_H_ */ diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/omap_gptmrreg.h /usr/src.omap/sys/arm/omap3/omap_gptmrreg.h --- /usr/src/sys/arm/omap3/omap_gptmrreg.h 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/omap_gptmrreg.h 2011-01-09 23:51:14.000000000 +0300 @@ -0,0 +1,79 @@ +#ifndef _ARM_OMAP_OMAP_GPTMRREG_H_ +#define _ARM_OMAP_OMAP_GPTMRREG_H_ +typedef struct timer_factors { + uint32_t ptv; + uint32_t reload; + uint32_t counts_per_usec; +} timer_factors; +/* Registers */ +#define TIDR 0x00 +#define TIOCP_CFG 0x10 +#define TISTAT 0x14 +#define TISR 0x18 +#define TIER 0x1C +#define TWER 0x20 +#define TCLR 0x24 +#define TCRR 0x28 +#define TLDR 0x2C +#define TTGR 0x30 +#define TWPS 0x34 +#define TMAR 0x38 +#define TCAR 0x3C +#define TSICR 0x40 + + +#define TIDR_TID_REV_MASK 0xF + +#define TIOCP_CFG_AUTOIDLE (1<<0) +#define TIOCP_CFG_SOFTRESET (1<<1) +#define TIOCP_CFG_ENAWAKEUP (1<<2) +#define TIOCP_CFG_IDLEMODE_MASK (3<<3) +#define TIOCP_CFG_IDLEMODE(n) (((n)&0x3)<<3) +#define TIOCP_CFG_EMUFREE (1<<5) + +#define TISTAT_RESETDONE (1<<0) + +#define TISR_MAT_IT_FLAG (1<<0) +#define TISR_OVF_IT_FLAG (1<<1) +#define TISR_TCAR_IT_FLAG (1<<2) + +#define TIER_MAT_IT_ENA (1<<0) +#define TIER_OVF_IT_ENA (1<<1) +#define TIER_TCAR_IT_ENA (1<<2) + +#define TWER_MAT_WUP_ENA (1<<0) +#define TWER_OVF_WUP_ENA (1<<2) +#define TWER_TCAR_WUP_ENA (1<<3) + +#define TCLR_ST (1<<0) +#define TCLR_AR (1<<1) +#define TCLR_PTV_MASK (7<<2) +#define TCLR_PTV(n) ((n)<<2) +#define TCLR_PRE(n) ((n)<<5) +#define TCLR_CE (1<<6) +#define TCLR_SCPWM (1<<7) +#define TCLR_TCM(n) ((n)<<8) +#define TCLR_TCM_MASK (3<<8) +#define TCLR_TRG(n) ((n)<<10) +#define TCLR_TRG_MASK (3<<10) +#define TCLR_PT (1<<12) + +#define TCLR_TCM_NONE 0 +#define TCLR_TCM_RISING 1 +#define TCLR_TCM_FALLING 2 +#define TCLR_TCM_BOTH 3 + +#define TCLR_TRG_NONE 0 +#define TCLR_TRG_OVERFLOW 1 +#define TCLR_TRG_OVERFLOW_AND_MATCH 2 + +#define TWPS_W_PEND__TCLR (1<<0) +#define TWPS_W_PEND__TCRR (1<<1) +#define TWPS_W_PEND__TLDR (1<<2) +#define TWPS_W_PEND__TTGR (1<<3) +#define TWPS_W_PEND__TMAR (1<<4) + +#define TSICR_POSTED (1<<2) +#define TSICR_SFT (1<<1) + +#endif diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/std.devkit8000 /usr/src.omap/sys/arm/omap3/std.devkit8000 --- /usr/src/sys/arm/omap3/std.devkit8000 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/std.devkit8000 2010-07-04 20:29:32.000000000 +0400 @@ -0,0 +1,6 @@ +#DEVKIT8000 board configuration +#$FreeBSD: src/sys/arm/omap3/std.devkit,v 1.1.12.1 2010/02/10 00:26:20 kensmith Exp $ +include "../omap3/std.omap3" +files "../omap3/files.devkit8000" +makeoptions KERNPHYSADDR=0x80200000 +makeoptions KERNVIRTADDR=0xc0200000 diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/std.omap3 /usr/src.omap/sys/arm/omap3/std.omap3 --- /usr/src/sys/arm/omap3/std.omap3 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/std.omap3 2011-01-09 16:32:28.000000000 +0300 @@ -0,0 +1,4 @@ +#TI OMAP3 generic configuration +#$FreeBSD: src/sys/arm/omap3/std.omap3,v 1.1.14.1 2010/02/10 00:26:20 kensmith Exp $ +files "../omap3/files.omap3" +cpu CPU_OMAP3 diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/uart_bus_omap3.c /usr/src.omap/sys/arm/omap3/uart_bus_omap3.c --- /usr/src/sys/arm/omap3/uart_bus_omap3.c 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/uart_bus_omap3.c 2011-01-25 22:55:01.000000000 +0300 @@ -0,0 +1,90 @@ +/*- + * Copyright (c) 2006 Kevin Lo. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/uart_bus_ixp425.c,v 1.3.10.1 2010/02/10 00:26:20 kensmith Exp $"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include "uart_if.h" +static int uart_omap3_probe(device_t dev); + +static device_method_t uart_omap3_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, uart_omap3_probe), + DEVMETHOD(device_attach, uart_bus_attach), + DEVMETHOD(device_detach, uart_bus_detach), + { 0, 0 } +}; + +static driver_t uart_omap3_driver = { + uart_driver_name, + uart_omap3_methods, + sizeof(struct uart_softc), +}; +DRIVER_MODULE(uart, ompio, uart_omap3_driver, uart_devclass, 0, 0); + +static int +uart_omap3_probe(device_t dev) +{ + struct uart_softc *sc; + sc = device_get_softc(dev); + sc->sc_class = &uart_ns8250_class; + sc->sc_rrid = 0; + sc->sc_rtype = SYS_RES_MEMORY; + sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid, + 0, ~0, uart_getrange(sc->sc_class), RF_ACTIVE); + if (sc->sc_rres == NULL) { + return (ENXIO); + } + sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); + sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); + + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, 0x08, + 0x07); + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, 0x10, + 0x08); + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, 0x08, + 0x0); + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, 0x15, + (0x02 << 3) | (1 << 2) | (1 << 0)); + bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); + + return uart_bus_probe(dev, 0, OMAP3_UART_FREQ, 0, 0); +} diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/uart_cpu_omap3.c /usr/src.omap/sys/arm/omap3/uart_cpu_omap3.c --- /usr/src/sys/arm/omap3/uart_cpu_omap3.c 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/uart_cpu_omap3.c 2011-01-25 22:40:46.000000000 +0300 @@ -0,0 +1,95 @@ +/*- + * Copyright (c) 2003 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/uart_cpu_ixp425.c,v 1.3.12.1 2010/02/10 00:26:20 kensmith Exp $"); + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +bus_space_tag_t uart_bus_space_io; +bus_space_tag_t uart_bus_space_mem; + +int +uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) +{ + return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); +} + +int +uart_cpu_getdev(int devtype, struct uart_devinfo *di) +{ + uint32_t i, ivar, vaddr; + + /* + * Scan the hints. The DEVKIT8000 only have 3 serial ports, so only + * scan them. + */ + for (i = 0; i < 3; i++) { + if (resource_int_value("uart", i, "flags", &ivar)) + continue; + if (devtype == UART_DEV_CONSOLE && !UART_FLAGS_CONSOLE(ivar)) + continue; + if (devtype == UART_DEV_DBGPORT && !UART_FLAGS_DBGPORT(ivar)) + continue; + /* + * We have a possible device. Make sure it's enabled and + * that we have an I/O port. + */ + if (resource_int_value("uart", i, "disabled", &ivar) == 0 && + ivar != 0) + continue; + if (resource_int_value("uart", i, "addr", &ivar) != 0 || + ivar == 0) + continue; + /* Got it. Fill in the instance and return it. */ + di->ops = uart_getops(&uart_ns8250_class); + di->bas.chan = 0; + di->bas.bst = &omap3_a4x_bs_tag; + di->bas.regshft = 0; + di->bas.rclk = OMAP3_UART_FREQ; + di->baudrate = 115200; + di->databits = 8; + di->stopbits = 1; + di->parity = UART_PARITY_NONE; + uart_bus_space_io = NULL; + uart_bus_space_mem = &omap3_a4x_bs_tag; + getvbase(ivar, OMAP3_REG_SIZE, &vaddr); + di->bas.bsh = vaddr; + return (0); + } + + return (ENXIO); +} diff -rNup --exclude=.svn /usr/src/sys/arm/omap3/uart_ll.h /usr/src.omap/sys/arm/omap3/uart_ll.h --- /usr/src/sys/arm/omap3/uart_ll.h 1970-01-01 03:00:00.000000000 +0300 +++ /usr/src.omap/sys/arm/omap3/uart_ll.h 2010-07-04 20:29:32.000000000 +0400 @@ -0,0 +1,223 @@ +/*- + * Copyright (c) 1991 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 + * $FreeBSD: src/sys/dev/ic/ns16550.h,v 1.17.10.1 2010/02/10 00:26:20 kensmith Exp $ + */ + +/* + * NS8250... UART registers. + */ + +/* 8250 registers #[0-6]. */ + +#define com_data 0 /* data register (R/W) */ +#define REG_DATA com_data + +#define com_ier 1 /* interrupt enable register (W) */ +#define REG_IER com_ier +#define IER_ERXRDY 0x1 +#define IER_ETXRDY 0x2 +#define IER_ERLS 0x4 +#define IER_EMSC 0x8 + +#define com_iir 2 /* interrupt identification register (R) */ +#define REG_IIR com_iir +#define IIR_IMASK 0xf +#define IIR_RXTOUT 0xc +#define IIR_RLS 0x6 +#define IIR_RXRDY 0x4 +#define IIR_TXRDY 0x2 +#define IIR_NOPEND 0x1 +#define IIR_MLSC 0x0 +#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ + +#define com_lcr 3 /* line control register (R/W) */ +#define com_cfcr com_lcr /* character format control register (R/W) */ +#define REG_LCR com_lcr +#define LCR_DLAB 0x80 +#define CFCR_DLAB LCR_DLAB +#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ +#define CFCR_EFR_ENABLE LCR_EFR_ENABLE +#define LCR_SBREAK 0x40 +#define CFCR_SBREAK LCR_SBREAK +#define LCR_PZERO 0x30 +#define CFCR_PZERO LCR_PZERO +#define LCR_PONE 0x20 +#define CFCR_PONE LCR_PONE +#define LCR_PEVEN 0x10 +#define CFCR_PEVEN LCR_PEVEN +#define LCR_PODD 0x00 +#define CFCR_PODD LCR_PODD +#define LCR_PENAB 0x08 +#define CFCR_PENAB LCR_PENAB +#define LCR_STOPB 0x04 +#define CFCR_STOPB LCR_STOPB +#define LCR_8BITS 0x03 +#define CFCR_8BITS LCR_8BITS +#define LCR_7BITS 0x02 +#define CFCR_7BITS LCR_7BITS +#define LCR_6BITS 0x01 +#define CFCR_6BITS LCR_6BITS +#define LCR_5BITS 0x00 +#define CFCR_5BITS LCR_5BITS + +#define com_mcr 4 /* modem control register (R/W) */ +#define REG_MCR com_mcr +#define MCR_PRESCALE 0x80 /* only available on 16650 up */ +#define MCR_LOOPBACK 0x10 +#define MCR_IE 0x08 +#define MCR_IENABLE MCR_IE +#define MCR_DRS 0x04 +#define MCR_RTS 0x02 +#define MCR_DTR 0x01 + +#define com_lsr 5 /* line status register (R/W) */ +#define REG_LSR com_lsr +#define LSR_RCV_FIFO 0x80 +#define LSR_TEMT 0x40 +#define LSR_TSRE LSR_TEMT +#define LSR_THRE 0x20 +#define LSR_TXRDY LSR_THRE +#define LSR_BI 0x10 +#define LSR_FE 0x08 +#define LSR_PE 0x04 +#define LSR_OE 0x02 +#define LSR_RXRDY 0x01 +#define LSR_RCV_MASK 0x1f + +#define com_msr 6 /* modem status register (R/W) */ +#define REG_MSR com_msr +#define MSR_DCD 0x80 +#define MSR_RI 0x40 +#define MSR_DSR 0x20 +#define MSR_CTS 0x10 +#define MSR_DDCD 0x08 +#define MSR_TERI 0x04 +#define MSR_DDSR 0x02 +#define MSR_DCTS 0x01 + +/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ +#define com_dll 0 /* divisor latch low (R/W) */ +#define com_dlbl com_dll +#define com_dlm 1 /* divisor latch high (R/W) */ +#define com_dlbh com_dlm +#define REG_DLL com_dll +#define REG_DLH com_dlm + +/* 16450 register #7. Not multiplexed. */ +#define com_scr 7 /* scratch register (R/W) */ + +/* 16550 register #2. Not multiplexed. */ +#define com_fcr 2 /* FIFO control register (W) */ +#define com_fifo com_fcr +#define REG_FCR com_fcr +#define FCR_ENABLE 0x01 +#define FIFO_ENABLE FCR_ENABLE +#define FCR_RCV_RST 0x02 +#define FIFO_RCV_RST FCR_RCV_RST +#define FCR_XMT_RST 0x04 +#define FIFO_XMT_RST FCR_XMT_RST +#define FCR_DMA 0x08 +#define FIFO_DMA_MODE FCR_DMA +#define FCR_RX_LOW 0x00 +#define FIFO_RX_LOW FCR_RX_LOW +#define FCR_RX_MEDL 0x40 +#define FIFO_RX_MEDL FCR_RX_MEDL +#define FCR_RX_MEDH 0x80 +#define FIFO_RX_MEDH FCR_RX_MEDH +#define FCR_RX_HIGH 0xc0 +#define FIFO_RX_HIGH FCR_RX_HIGH + +/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ + +#define com_efr 2 /* enhanced features register (R/W) */ +#define REG_EFR com_efr +#define EFR_CTS 0x80 +#define EFR_AUTOCTS EFR_CTS +#define EFR_RTS 0x40 +#define EFR_AUTORTS EFR_RTS +#define EFR_EFE 0x10 /* enhanced functions enable */ + +#define com_xon1 4 /* XON 1 character (R/W) */ +#define com_xon2 5 /* XON 2 character (R/W) */ +#define com_xoff1 6 /* XOFF 1 character (R/W) */ +#define com_xoff2 7 /* XOFF 2 character (R/W) */ + +/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ +#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ + +/* 16950 register #3. R/W access enabled by ACR[7]. */ +#define com_rfl 3 /* receiver fifo level (R) */ + +/* + * 16950 register #4. Access enabled by ACR[7]. Also requires + * !LCR_EFR_ENABLE. + */ +#define com_tfl 4 /* transmitter fifo level (R) */ + +/* + * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also + * requires ACR[6]. + */ +#define com_icr 5 /* index control register (R/W) */ + +/* + * 16950 register #7. It is the same as com_scr except it has a different + * abbreviation in the manufacturer's data sheet and it also serves as an + * index into the Indexed Control register set. + */ +#define com_spr com_scr /* scratch pad (and index) register (R/W) */ +#define REG_SPR com_scr + +/* + * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, + * data in ICR (if ICR is accessible). + */ + +#define com_acr 0 /* additional control register (R/W) */ +#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ +#define ACR_ICRE 0x40 /* ICR enable */ +#define ACR_TLE 0x20 /* TTL/RTL enable */ + +#define com_cpr 1 /* clock prescaler register (R/W) */ +#define com_tcr 2 /* times clock register (R/W) */ +#define com_ttl 4 /* transmitter trigger level (R/W) */ +#define com_rtl 5 /* receiver trigger level (R/W) */ +/* ... */ + +#ifdef PC98 +/* Hardware extension mode register for RSB-2000/3000. */ +#define com_emr com_msr +#define EMR_EXBUFF 0x04 +#define EMR_CTSFLW 0x08 +#define EMR_DSRFLW 0x10 +#define EMR_RTSFLW 0x20 +#define EMR_DTRFLW 0x40 +#define EMR_EFMODE 0x80 +#endif diff -rNup --exclude=.svn /usr/src/sys/conf/kern.post.mk /usr/src.omap/sys/conf/kern.post.mk --- /usr/src/sys/conf/kern.post.mk 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/conf/kern.post.mk 2011-01-23 01:48:47.000000000 +0300 @@ -101,6 +101,13 @@ ${FULLKERNEL}: ${SYSTEM_DEP} vers.o strings ${FULLKERNEL} | \ grep 'MFS Filesystem had better STOP here' > /dev/null || \ (rm ${FULLKERNEL} && echo 'MFS image too large' && false) + @dd if="${MFS_IMAGE}" ibs=8192 of=kernel.bin \ + obs=`strings -at d kernel.bin | \ + grep "MFS Filesystem goes here" | awk '{print $$1}'` \ + oseek=1 conv=notrunc 2>/dev/null && \ + strings kernel.bin | \ + grep 'MFS Filesystem had better STOP here' > /dev/null || \ + (rm kernel.bin && echo 'MFS image too large' && false) .endif .if !exists(${.OBJDIR}/.depend) diff -rNup --exclude=.svn /usr/src/sys/conf/options.arm /usr/src.omap/sys/conf/options.arm --- /usr/src/sys/conf/options.arm 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/conf/options.arm 2011-01-09 23:43:10.000000000 +0300 @@ -13,6 +13,8 @@ CPU_XSCALE_80219 opt_global.h CPU_XSCALE_80321 opt_global.h CPU_XSCALE_81342 opt_global.h CPU_XSCALE_IXP425 opt_global.h +CPU_OMAP3 opt_global.h +OMAP_MPU_TIMER_CLOCK_FREQ opt_global.h FLASHADDR opt_global.h KERNPHYSADDR opt_global.h KERNVIRTADDR opt_global.h diff -rNup --exclude=.svn /usr/src/sys/dev/uart/uart_core.c /usr/src.omap/sys/dev/uart/uart_core.c --- /usr/src/sys/dev/uart/uart_core.c 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/dev/uart/uart_core.c 2011-01-26 22:41:08.000000000 +0300 @@ -234,11 +234,13 @@ uart_intr_sigchg(void *arg) /* * The transmitter can accept more data. */ -static __inline int +extern int ns8250_mask_txidle(struct uart_softc *); + +static int uart_intr_txidle(void *arg) { struct uart_softc *sc = arg; - + ns8250_mask_txidle(sc); if (sc->sc_txbusy) { sc->sc_txbusy = 0; uart_sched_softih(sc, SER_INT_TXIDLE); @@ -251,7 +253,7 @@ uart_intr(void *arg) { struct uart_softc *sc = arg; int flag = 0, ipend; - + while (!sc->sc_leaving && (ipend = UART_IPEND(sc)) != 0) { flag = 1; if (ipend & SER_INT_OVERRUN) @@ -262,8 +264,12 @@ uart_intr(void *arg) uart_intr_rxready(sc); if (ipend & SER_INT_SIGCHG) uart_intr_sigchg(sc); - if (ipend & SER_INT_TXIDLE) - uart_intr_txidle(sc); + if (ipend & SER_INT_TXIDLE) { + uart_intr_txidle(sc); +#if defined(CPU_OMAP3) + break; +#endif + } } return((flag)?FILTER_HANDLED:FILTER_STRAY); } diff -rNup --exclude=.svn /usr/src/sys/dev/uart/uart_dev_ns8250.c /usr/src.omap/sys/dev/uart/uart_dev_ns8250.c --- /usr/src/sys/dev/uart/uart_dev_ns8250.c 2010-02-10 03:26:20.000000000 +0300 +++ /usr/src.omap/sys/dev/uart/uart_dev_ns8250.c 2011-01-26 22:41:40.000000000 +0300 @@ -831,3 +831,16 @@ ns8250_bus_transmit(struct uart_softc *s uart_unlock(sc->sc_hwmtx); return (0); } + +#if defined(CPU_OMAP3) +int +ns8250_mask_txidle(struct uart_softc *sc) +{ + struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; + struct uart_bas *bas; + bas = &sc->sc_bas; + uart_setreg(bas, REG_IER, ns8250->ier & ~IER_ETXRDY); + uart_barrier(bas); + return (0); +} +#endif --------------060403020603080904070903-- From owner-freebsd-arm@FreeBSD.ORG Fri Jan 28 13:36:27 2011 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 4E0EF1065670 for ; Fri, 28 Jan 2011 13:36:27 +0000 (UTC) (envelope-from deveshkr@marvell.com) Received: from na3sys009aog113.obsmtp.com (na3sys009aog113.obsmtp.com [74.125.149.209]) by mx1.freebsd.org (Postfix) with ESMTP id 1C8B38FC15 for ; Fri, 28 Jan 2011 13:36:26 +0000 (UTC) Received: from source ([65.219.4.129]) (using TLSv1) by na3sys009aob113.postini.com ([74.125.148.12]) with SMTP ID DSNKTULGUJnxe9JcSVvmdcsXuoXj/4fgetST@postini.com; Fri, 28 Jan 2011 05:36:27 PST Received: from SC-vEXCH2.marvell.com ([10.93.76.134]) by SC-OWA01.marvell.com ([10.93.76.21]) with mapi; Fri, 28 Jan 2011 05:35:49 -0800 From: Devesh Rai To: Mark Tinguely Date: Fri, 28 Jan 2011 05:35:47 -0800 Thread-Topic: Changing virtual adress space layout Thread-Index: Acu9bxeLmsoYZ3yuQp6AellPvfFTEwBfyEWg Message-ID: <0DB595A2CB707F458400BE9663B6A7225E42E36569@SC-VEXCH2.marvell.com> In-Reply-To: <4D403FF3.7010500@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "freebsd-arm@freebsd.org" Subject: RE: Changing virtual adress space layout X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Jan 2011 13:36:27 -0000 Hi Mark, Thank you very much for your detail response. Trick of not changing KERNVIR= TADDR worked. I was able to map 1GB of RAM into kva from KERNBASE(0x8000_0000) to OLD_KER= NBASE(0xC000_0000) using pmap_map_chunk api. I was able to write some data into mapped space and print it back.=20 But some doubt I still have 1) What is L1 and L2 page table in FreeBSD? Is there document which explain= s these vm concepts for arm? 2) How do I verify that this mapping indeed happened? Thanks & Regards Devesh -----Original Message----- From: Mark Tinguely [mailto:marktinguely@gmail.com]=20 Sent: Wednesday, January 26, 2011 9:08 PM To: Devesh Rai Cc: freebsd-arm@freebsd.org Subject: Re: Changing virtual adress space layout Reading your reply, it sounds like you want to directly map a full 1GB=20 to the KVA. The upper 1GB will always be partially used; for example it=20 has HIGH_VECTOR, and device mappings. So it sounds like you should set=20 KERNBASE to 0x8000_0000, map the RAM at 0x8000_0000 and leave the=20 KERNVIRTADDR where is was. The 1GB memory should be physically contiguous and properly aligned, so=20 you be able to directly add the addresses into the KVA "level 1=20 pagetable entries" either manually or with pmap_map_chunk(). Sorry, I do not have my development machine, so I can't do the=20 background work. Does changing the KERNBASE into a makeoption really=20 overriding the static define in /sys/arm/include/vm_machdep.h? A "cc -E"=20 (for example initarm() source file) would answer that question. The=20 other place to look would be in /sys/conf, but after a quick look, I did=20 not see any hardcoded values in the ARM specific files. Also, the KERNVIRTADDR does not equal KERNBASE on many ARM platforms ;=20 the boot loader may have put the kernel text at an offset to pass=20 parameters, and some older families use the ARM_USE_SMALL_ALLOC feature=20 - a form of direct ARM pagetable map. For example, the Sheeva port has=20 the KERNPHYSADDR/KERNVIRTADDR at 0x00900000/0xc0900000. --Mark. On 1/26/2011 8:34 AM, Devesh Rai wrote: > > Hi Mark, > > Actually I want to map large portion of RAM in kernel virtual address spa= ce. > To achieve this in Linux, I did following > > 1) boot kernel with 256M by setting CONFIG_CMDLINE=3D"mem=3D256M". This f= reed up more than 1GB of RAM for my module usages > 2) increase KVA to 3GB by setting CONFIG_VMSPLIT_1G=3Dy ( 1G for user and= 3GB for kernel) > 3) ioremap unused RAM ( 2GB - 256MB ) into Kernel virtual address space. > > Changing KERNBASE and KERNVIRTADDR "makeoption" from 0xc0000000 to 0x8000= 0000 did not worked for me. Kernel hang while loading. > > Thanks& Regards > Devesh > > -----Original Message----- > From: Mark Tinguely [mailto:marktinguely@gmail.com] > Sent: Thursday, January 13, 2011 10:00 PM > To: freebsd-arm@freebsd.org > Cc: Devesh Rai > Subject: Re: Changing virtual adress space layout > > On 1/13/2011 1:30 AM, Devesh Rai wrote: >> Hi, >> >> I am new to FreeBSD. Can some tell how to change virtual address space l= ayout in FreeBSD for arm? >> For x86, KVA_PAGES=3DN option is there in FreeBSD. In Linux, I used CON= FIG_VMSPLIT option. >> I am looking corresponding option for arm. >> >> Regards >> Devesh > I assume you have run out of space for the device virtual addresses. > > KERNBASE is hard coded in sys/arm/include/vm_param.h to be 0xc0000000. > > There is a related variable for each device configuration: the > KERNVIRTADDR "option" and "makeoption" values. This is usually in one > of the "std" file file for the device. KERNVIRTADDR sets the starting > location of the executable and is sometimes different than KERNBASE. > > The arm code does not map the from KERNBASE to 0xffff_ffff into the KVA. > Instead, there is a variable that determines the maximum size of the > kernel executable and kernel virtual address area. Above this defined > area lies the no-cache remap memory region, device map area, high > vector, etc. > > On a tangent note: There will be a great advantage in ARMv6/ARMv7 to go > to a 2GB UVA / 2GB KVA. > > --Mark. > From owner-freebsd-arm@FreeBSD.ORG Fri Jan 28 14:36:23 2011 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6B114106564A for ; Fri, 28 Jan 2011 14:36:23 +0000 (UTC) (envelope-from marktinguely@gmail.com) Received: from mail-iy0-f182.google.com (mail-iy0-f182.google.com [209.85.210.182]) by mx1.freebsd.org (Postfix) with ESMTP id 2D3748FC28 for ; Fri, 28 Jan 2011 14:36:23 +0000 (UTC) Received: by iyb26 with SMTP id 26so2677076iyb.13 for ; Fri, 28 Jan 2011 06:36:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:message-id:date:from:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=jid4SKXxUpxP9sdLIYB4SOpWMmegKpFlVUXxkj1XhhE=; b=MnFkmHuGgSy8kRw2L/xlVvSxUPsRA9FayoaUgky8HP53WuQ3OoafuZC5kEmBk5LBNn Or/NUFz75aCYCJ1taqOZlKqrVZhrp4bGX2mDs49rbj2/hyFjFrlWUC4fduj2Eg3vNMdm yk64+T4LIWa94bLReXgXzFf+yOLZqkXy4qFZ0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; b=SpeVXAC/lqlECEsXPJzHrx7PaJUNY9s/JH/z1KZg5g26JCqVzAgfGz9VV+g68zYMHo uNYYQmFjebhHp6VaUEGv7ghNOD7MFp5AZiymFmkQjVruSAupeNW7SrRNADr8n0hYXaco EYJKW4D4U/RXHuRO5CQE17K2dbP+I1/QZpkiE= Received: by 10.42.172.67 with SMTP id m3mr3985894icz.95.1296225382138; Fri, 28 Jan 2011 06:36:22 -0800 (PST) Received: from [192.168.1.104] (c-24-245-26-12.hsd1.mn.comcast.net [24.245.26.12]) by mx.google.com with ESMTPS id u5sm13397192ics.18.2011.01.28.06.36.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 28 Jan 2011 06:36:20 -0800 (PST) Message-ID: <4D42D45D.5080200@gmail.com> Date: Fri, 28 Jan 2011 08:36:13 -0600 From: Mark Tinguely User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Devesh Rai References: <0DB595A2CB707F458400BE9663B6A7225E42E36569@SC-VEXCH2.marvell.com> In-Reply-To: <0DB595A2CB707F458400BE9663B6A7225E42E36569@SC-VEXCH2.marvell.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Cc: "freebsd-arm@freebsd.org" Subject: Re: Changing virtual adress space layout X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Jan 2011 14:36:23 -0000 On 1/28/2011 7:35 AM, Devesh Rai wrote: > Hi Mark, > > Thank you very much for your detail response. Trick of not changing KERNVIRTADDR worked. > I was able to map 1GB of RAM into kva from KERNBASE(0x8000_0000) to OLD_KERNBASE(0xC000_0000) using pmap_map_chunk api. > I was able to write some data into mapped space and print it back. > > But some doubt I still have > > 1) What is L1 and L2 page table in FreeBSD? Is there document which explains these vm concepts for arm? > 2) How do I verify that this mapping indeed happened? > > Thanks& Regards > Devesh Good news. The ARMŽ Architecture Reference Manual is available for download on the website www.arm.com. There is a document that covers ARMv4-ARMv6 and a document for ARMv7. The L1 maps 1MB of contiguous memory or has a pointer to a 1KB l2 page table entry that maps 256 4KB pages. Sounds like you are mapping a 1MB contiuous area of memory that is on a 1 MB boundary, but If you were not then, you first need to allocate 1KB for the l2 page table and install it into the kernel page table using the pmap_link_l2pt() routine. The pmap_map_chunk() routine can then be used to install the l1/l2 mapping. You may want to think about the appropriate caching of this memory. You can look at the l1 (and l2 if used) page tables to verify that the KVA is mapped to the proper PA. I suppose you could remap the PA to another KVA to verify values too, but you have to understand caching principles to do this correctly. --Mark.