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Date:      Mon, 9 Apr 2012 10:50:14 GMT
From:      Kristof Provost <kristof@sigsegv.be>
To:        freebsd-arm@FreeBSD.org
Subject:   Re: arm/156814: OpenRD Ultimate does not boot on DB-%38%38F%36XXX or SHEEVAPLUG kernel configurations
Message-ID:  <201204091050.q39AoE3F021562@freefall.freebsd.org>

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The following reply was made to PR arm/156814; it has been noted by GNATS.

From: Kristof Provost <kristof@sigsegv.be>
To: bug-followup@FreeBSD.org, vancorte@biologie.ens.fr
Cc:  
Subject: Re: arm/156814: OpenRD Ultimate does not boot on DB-%38%38F%36XXX or
 SHEEVAPLUG kernel configurations
Date: Mon, 9 Apr 2012 12:41:03 +0200

 --G4iJoqBmSsgzjUCe
 Content-Type: text/plain; charset=utf-8
 Content-Disposition: inline
 
 Hi,
 
 I've updated the config and device tree. 
 With the attached patch both MGE interfaces work, as does the crypto 
 accelerator.
 
 (Against current r234000)
 
 Regards,
 Kristof
 
 
 --G4iJoqBmSsgzjUCe
 Content-Type: text/x-diff; charset=utf-8
 Content-Disposition: attachment; filename="openrd-cl.patch"
 
 diff --git a/sys/arm/conf/OPENRD-CL b/sys/arm/conf/OPENRD-CL
 new file mode 100644
 index 0000000..25707ed
 --- /dev/null
 +++ b/sys/arm/conf/OPENRD-CL
 @@ -0,0 +1,81 @@
 +#
 +# Custom kernel for OpenRD Client/Ultimate devices.
 +#
 +# $FreeBSD$
 +#
 +
 +ident		OPENRD-CL
 +include		"../mv/kirkwood/std.sheevaplug"
 +
 +options 	SOC_MV_KIRKWOOD
 +makeoptions	MODULES_OVERRIDE=""
 +
 +makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
 +makeoptions	WERROR="-Werror"
 +makeoptions     INVARIANTS
 +
 +options 	SCHED_4BSD		#4BSD scheduler
 +options 	INET			#InterNETworking
 +options 	INET6			#IPv6 communications protocols
 +options 	FFS			#Berkeley Fast Filesystem
 +options 	NFSCL			#New Network Filesystem Client
 +options 	NFSLOCKD		#Network Lock Manager
 +options 	NFS_ROOT		#NFS usable as /, requires NFSCL
 +options 	BOOTP
 +options 	BOOTP_NFSROOT
 +options 	BOOTP_NFSV3
 +options 	BOOTP_WIRED_TO=mge0
 +
 +# Root fs on USB device
 +#options 	ROOTDEVNAME=\"ufs:/dev/da0a\"
 +
 +options 	SYSVSHM			#SYSV-style shared memory
 +options 	SYSVMSG			#SYSV-style message queues
 +options 	SYSVSEM			#SYSV-style semaphores
 +options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
 +options 	MUTEX_NOINLINE
 +options 	RWLOCK_NOINLINE
 +options 	NO_FFS_SNAPSHOT
 +options 	NO_SWAPPING
 +
 +# Debugging
 +options 	ALT_BREAK_TO_DEBUGGER
 +options 	DDB
 +options 	KDB
 +
 +# Pseudo devices
 +device		random
 +device		pty
 +device		loop
 +
 +# Serial ports
 +device		uart
 +
 +# Networking
 +device		ether
 +device		mge			# Marvell Gigabit Ethernet controller
 +device		mii
 +device		e1000phy
 +device		bpf
 +options		HZ=1000
 +options		DEVICE_POLLING
 +device		vlan
 +
 +device		cesa			# Marvell security engine
 +device		crypto
 +device		cryptodev
 +
 +# USB
 +options 	USB_DEBUG	# enable debug msgs
 +device		usb
 +device		ehci
 +device		umass
 +device		scbus
 +device		pass
 +device		da
 +
 +# Flattened Device Tree
 +options 	FDT
 +options		FDT_DTB_STATIC
 +makeoptions	FDT_DTS_FILE=openrd-cl.dts
 +
 diff --git a/sys/boot/fdt/dts/openrd-cl.dts b/sys/boot/fdt/dts/openrd-cl.dts
 new file mode 100644
 index 0000000..6d11779
 --- /dev/null
 +++ b/sys/boot/fdt/dts/openrd-cl.dts
 @@ -0,0 +1,340 @@
 +/*
 + * Copyright (c) 2009-2010 The FreeBSD Foundation
 + * All rights reserved.
 + *
 + * This software was developed by Semihalf under sponsorship from
 + * the FreeBSD Foundation.
 + *
 + * Redistribution and use in source and binary forms, with or without
 + * modification, are permitted provided that the following conditions
 + * are met:
 + * 1. Redistributions of source code must retain the above copyright
 + *    notice, this list of conditions and the following disclaimer.
 + * 2. Redistributions in binary form must reproduce the above copyright
 + *    notice, this list of conditions and the following disclaimer in the
 + *    documentation and/or other materials provided with the distribution.
 + *
 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 + * SUCH DAMAGE.
 + *
 + * OpenRD-Client/Ultimate Device Tree Source.
 + *
 + * $FreeBSD$
 + */
 +
 +/dts-v1/;
 +
 +/ {
 +	model = "mrvl,OpenRD-CL";
 +	compatible = "OpenRD-CL";
 +	#address-cells = <1>;
 +	#size-cells = <1>;
 +
 +	aliases {
 +		ethernet0 = &enet0;
 +		ethernet1 = &enet1;
 +		mpp = &MPP;
 +		pci0 = &pci0;
 +		serial0 = &serial0;
 +		serial1 = &serial1;
 +		soc = &SOC;
 +		sram = &SRAM;
 +	};
 +
 +	cpus {
 +		#address-cells = <1>;
 +		#size-cells = <0>;
 +
 +		cpu@0 {
 +			device_type = "cpu";
 +			compatible = "ARM,88FR131";
 +			reg = <0x0>;
 +			d-cache-line-size = <32>;	// 32 bytes
 +			i-cache-line-size = <32>;	// 32 bytes
 +			d-cache-size = <0x4000>;	// L1, 16K
 +			i-cache-size = <0x4000>;	// L1, 16K
 +			timebase-frequency = <0>;
 +			bus-frequency = <0>;
 +			clock-frequency = <0>;
 +		};
 +	};
 +
 +	memory {
 +		device_type = "memory";
 +		reg = <0x0 0x20000000>;		// 512M at 0x0
 +	};
 +
 +	localbus@f1000000 {
 +		#address-cells = <2>;
 +		#size-cells = <1>;
 +		compatible = "mrvl,lbc";
 +
 +		/* This reflects CPU decode windows setup. */
 +		ranges = <0x0 0x0f 0xf9300000 0x00100000
 +			  0x1 0x1e 0xfa000000 0x00100000
 +			  0x2 0x1d 0xfa100000 0x02000000
 +			  0x3 0x1b 0xfc100000 0x00000400>;
 +
 +		nor@0,0 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			compatible = "cfi-flash";
 +			reg = <0x0 0x0 0x00100000>;
 +			bank-width = <2>;
 +			device-width = <1>;
 +		};
 +
 +		led@1,0 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			compatible = "led";
 +			reg = <0x1 0x0 0x00100000>;
 +		};
 +
 +		nor@2,0 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			compatible = "cfi-flash";
 +			reg = <0x2 0x0 0x02000000>;
 +			bank-width = <2>;
 +			device-width = <1>;
 +		};
 +
 +		nand@3,0 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			reg = <0x3 0x0 0x00100000>;
 +			bank-width = <2>;
 +			device-width = <1>;
 +		};
 +	};
 +
 +	SOC: soc88f6281@f1000000 {
 +		#address-cells = <1>;
 +		#size-cells = <1>;
 +		compatible = "simple-bus";
 +		ranges = <0x0 0xf1000000 0x00100000>;
 +		bus-frequency = <0>;
 +
 +		PIC: pic@20200 {
 +			interrupt-controller;
 +			#address-cells = <0>;
 +			#interrupt-cells = <1>;
 +			reg = <0x20200 0x3c>;
 +			compatible = "mrvl,pic";
 +		};
 +
 +		timer@20300 {
 +			compatible = "mrvl,timer";
 +			reg = <0x20300 0x30>;
 +			interrupts = <1>;
 +			interrupt-parent = <&PIC>;
 +			mrvl,has-wdt;
 +		};
 +
 +		MPP: mpp@10000 {
 +			#pin-cells = <2>;
 +			compatible = "mrvl,mpp";
 +			reg = <0x10000 0x34>;
 +			pin-count = <50>;
 +			pin-map = <
 +				0  1		/* MPP[0]:  NF_IO[2] */
 +				1  1		/* MPP[1]:  NF_IO[3] */
 +				2  1		/* MPP[2]:  NF_IO[4] */
 +				3  1		/* MPP[3]:  NF_IO[5] */
 +				4  1		/* MPP[4]:  NF_IO[6] */
 +				5  1		/* MPP[5]:  NF_IO[7] */
 +				6  1		/* MPP[6]:  SYSRST_OUTn */
 +				8  2		/* MPP[8]:  UA0_RTS */
 +				9  2		/* MPP[9]:  UA0_CTS */
 +				10 3		/* MPP[10]: UA0_TXD */
 +				11 3		/* MPP[11]: UA0_RXD */
 +				12 1		/* MPP[12]: SD_CLK */
 +				13 1		/* MPP[13]: SD_CMD */
 +				14 1		/* MPP[14]: SD_D[0] */
 +				15 1		/* MPP[15]: SD_D[1] */
 +				16 1		/* MPP[16]: SD_D[2] */
 +				17 1		/* MPP[17]: SD_D[3] */
 +				20 3            /* MPP[20]: GE1_CPU_RX0 */
 +				21 3            /* MPP[21]: GE1_CPU_RX1 */
 +				22 3            /* MPP[22]: GE1_CPU_RX2 */
 +				23 3            /* MPP[23]: GE1_CPU_RX3 */
 +				24 3            /* MPP[24]: GE1_CPU_TX0 */
 +				25 3            /* MPP[25]: GE1_CPU_TX1 */
 +				26 3            /* MPP[26]: GE1_CPU_TX2 */
 +				27 3            /* MPP[27]: GE1_CPU_RD3 */
 +				28 0            /* MPP[28]: GPIO */
 +				29 0            /* MPP[29]: GPIO */
 +				30 3            /* GE1_RXCTL */
 +				31 3            /* GE1_RXCLK */
 +				32 3            /* GE1_TXCLK */
 +				33 3            /* GE1_TXCTL */
 +				34 0 >;         /* MPP[34]: GPIO */
 +		};
 +
 +		GPIO: gpio@10100 {
 +			#gpio-cells = <3>;
 +			compatible = "mrvl,gpio";
 +			reg = <0x10100 0x20>;
 +			gpio-controller;
 +			interrupts = <35 36 37 38 39 40 41>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		rtc@10300 {
 +			compatible = "mrvl,rtc";
 +			reg = <0x10300 0x08>;
 +		};
 +
 +		twsi@11000 {
 +			#address-cells = <1>;
 +			#size-cells = <0>;
 +			compatible = "mrvl,twsi";
 +			reg = <0x11000 0x20>;
 +			interrupts = <43>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		enet0: ethernet@72000 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			model = "V2";
 +			compatible = "mrvl,ge";
 +			reg = <0x72000 0x2000>;
 +			ranges = <0x0 0x72000 0x2000>;
 +			local-mac-address = [ 00 00 00 00 00 00 ];
 +			interrupts = <12 13 14 11 46>;
 +			interrupt-parent = <&PIC>;
 +			phy-handle = <&phy0>;
 +
 +			mdio@0 {
 +				#address-cells = <1>;
 +				#size-cells = <0>;
 +				compatible = "mrvl,mdio";
 +
 +				phy0: ethernet-phy@0 {
 +					reg = <0x0>;
 +				};
 +				phy1: ethernet-phy@1 {
 +					reg = <0x1>;
 +				};
 +			};
 +		};
 +
 +		enet1: ethernet@76000 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			model = "V2";
 +			compatible = "mrvl,ge";
 +			reg = <0x76000 0x2000>;
 +			ranges = <0x0 0x76000 0x2000>;
 +			local-mac-address = [ 00 00 00 00 00 00 ];
 +			interrupts = <16 17 18 15 47>;
 +			interrupt-parent = <&PIC>;
 +			phy-handle = <&phy1>;
 +		};
 +
 +		serial0: serial@12000 {
 +			compatible = "ns16550";
 +			reg = <0x12000 0x20>;
 +			reg-shift = <2>;
 +			clock-frequency = <0>;
 +			interrupts = <33>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		serial1: serial@12100 {
 +			compatible = "ns16550";
 +			reg = <0x12100 0x20>;
 +			reg-shift = <2>;
 +			clock-frequency = <0>;
 +			interrupts = <34>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		crypto@30000 {
 +			compatible = "mrvl,cesa";
 +			reg = <0x30000 0x10000>;
 +			interrupts = <22>;
 +			interrupt-parent = <&PIC>;
 +			sram-handle = <&SRAM>;
 +		};
 +
 +		usb@50000 {
 +			compatible = "mrvl,usb-ehci", "usb-ehci";
 +			reg = <0x50000 0x1000>;
 +			interrupts = <48 19>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		xor@60000 {
 +			compatible = "mrvl,xor";
 +			reg = <0x60000 0x1000>;
 +			interrupts = <5 6 7 8>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		sata@80000 {
 +			compatible = "mrvl,sata";
 +			reg = <0x80000 0x6000>;
 +			interrupts = <21>;
 +			interrupt-parent = <&PIC>;
 +		};
 +	};
 +
 +	SRAM: sram@fd000000 {
 +		compatible = "mrvl,cesa-sram";
 +		reg = <0xfd000000 0x00100000>;
 +	};
 +
 +	chosen {
 +		stdin  = "serial0";
 +		stdout = "serial0";
 +	};
 +
 +	pci0: pcie@f1040000 {
 +		compatible = "mrvl,pcie";
 +		device_type = "pci";
 +		#interrupt-cells = <1>;
 +		#size-cells = <2>;
 +		#address-cells = <3>;
 +		reg = <0xf1040000 0x2000>;
 +		bus-range = <0 255>;
 +		ranges = <0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x04000000
 +			  0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
 +		clock-frequency = <33333333>;
 +		interrupt-parent = <&PIC>;
 +		interrupts = <44>;
 +		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 +		interrupt-map = <
 +			/* IDSEL 0x1 */
 +			0x0800 0x0 0x0 0x1 &PIC 0x9
 +			0x0800 0x0 0x0 0x2 &PIC 0x9
 +			0x0800 0x0 0x0 0x3 &PIC 0x9
 +			0x0800 0x0 0x0 0x4 &PIC 0x9
 +			>;
 +		pcie@0 {
 +			reg = <0x0 0x0 0x0 0x0 0x0>;
 +			#size-cells = <2>;
 +			#address-cells = <3>;
 +			device_type = "pci";
 +			ranges = <0x02000000 0x0 0xf4000000
 +				  0x02000000 0x0 0xf4000000
 +				  0x0 0x04040000
 +
 +				  0x01000000 0x0 0x0
 +				  0x01000000 0x0 0x0
 +				  0x0 0x00100000>;
 +		};
 +	};
 +};
 +
 
 --G4iJoqBmSsgzjUCe--



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