From owner-p4-projects@FreeBSD.ORG Mon May 28 14:32:52 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 2E7071065675; Mon, 28 May 2012 14:32:52 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id E4EA51065672 for ; Mon, 28 May 2012 14:32:51 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id B39D08FC1F for ; Mon, 28 May 2012 14:32:51 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q4SEWpZo052233 for ; Mon, 28 May 2012 14:32:51 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q4SEWp28052228 for perforce@freebsd.org; Mon, 28 May 2012 14:32:51 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Mon, 28 May 2012 14:32:51 GMT Message-Id: <201205281432.q4SEWp28052228@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 211874 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 May 2012 14:32:52 -0000 http://p4web.freebsd.org/@@211874?ac=10 Change 211874 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/05/28 14:32:48 When we fail to detect the right text frame buffer offset in the MTL register, rather than working around it by writing the correct offset, fail to attach the MTL driver. This causes the driver not to attach in BERI simulation as we don't have a PISM instantiation of the MTL device (as yet). Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/dev/terasic/mtl/terasic_mtl.h#5 edit .. //depot/projects/ctsrd/beribsd/src/sys/dev/terasic/mtl/terasic_mtl_text.c#5 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/dev/terasic/mtl/terasic_mtl.h#5 (text+ko) ==== @@ -141,6 +141,7 @@ /* * Constants to help interpret the text frame buffer. */ +#define TERASIC_MTL_TEXTFRAMEBUF_EXPECTED_ADDR 0x0177000 #define TERASIC_MTL_TEXTFRAMEBUF_CHAR_SHIFT 0 #define TERASIC_MTL_TEXTFRAMEBUF_ATTR_SHIFT 8 ==== //depot/projects/ctsrd/beribsd/src/sys/dev/terasic/mtl/terasic_mtl_text.c#5 (text+ko) ==== @@ -154,32 +154,17 @@ bus_write_2(sc->mtl_text_res, offset, v); } -/* - * XXXRW: Work around a feature in which the default address of the text frame - * buffer is not initialised at reset as expected. - */ -#define TERASIC_MTL_TEXT_EXPECTED_ADDR 0x0177000 -static void -terasic_mtl_text_workaround(struct terasic_mtl_softc *sc) +int +terasic_mtl_text_attach(struct terasic_mtl_softc *sc) { uint32_t v; terasic_mtl_reg_textframebufaddr_get(sc, &v); - if (v == TERASIC_MTL_TEXT_EXPECTED_ADDR) - return; - device_printf(sc->mtl_dev, - "%s: adjusting text frame buffer reg from 0x%x to 0x%x\n", - __func__, v, TERASIC_MTL_TEXT_EXPECTED_ADDR); - terasic_mtl_reg_textframebufaddr_set(sc, - TERASIC_MTL_TEXT_EXPECTED_ADDR); -} - -int -terasic_mtl_text_attach(struct terasic_mtl_softc *sc) -{ - - /* XXXRW: To go away. */ - terasic_mtl_text_workaround(sc); + if (v != TERASIC_MTL_TEXTFRAMEBUF_EXPECTED_ADDR) { + device_printf(sc->mtl_dev, "%s: unexpected text frame buffer " + "address (%08x); cannot attach\n", __func__, v); + return (ENXIO); + } sc->mtl_text_cdev = make_dev(&terasic_mtl_text_cdevsw, sc->mtl_unit, UID_ROOT, GID_WHEEL, 0400, "mtl_text%d", sc->mtl_unit); From owner-p4-projects@FreeBSD.ORG Tue May 29 18:58:01 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 64F8D1065672; Tue, 29 May 2012 18:58:01 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2799D106566C for ; Tue, 29 May 2012 18:58:01 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 101C08FC0A for ; Tue, 29 May 2012 18:58:01 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q4TIw00Z021563 for ; Tue, 29 May 2012 18:58:00 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q4TIw0HK021560 for perforce@freebsd.org; Tue, 29 May 2012 18:58:00 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Tue, 29 May 2012 18:58:00 GMT Message-Id: <201205291858.q4TIw0HK021560@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 211945 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 May 2012 18:58:01 -0000 http://p4web.freebsd.org/@@211945?ac=10 Change 211945 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/05/29 18:57:04 Modify MIPS page table entry (PTE) initialisation so that cachability bits are set only once, using is_cacheable_mem() to determine what caching properties are required, rather than also unconditionally setting PTE_C_CACHE in init_pte_prot(). As PTE_C_CACHE | PTE_C_UNCACHED == PTE_C_CACHE, this meant that all userspace memory mappings of device memory used caching TLB entries. This is arguably not quite what we want, even though it is consistent with the MIPS pmap design: PTE caching properties should be derived from machine-independent page table attributes, but this is a substantially more complex change as the MIPS pmap doesn't yet known about attributes. This may fix cacheability issues seen in memory mappings of MTL and DE4 device memory on CHERI MIPS. Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/pmap.c#2 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/pmap.c#2 (text+ko) ==== @@ -3144,16 +3144,16 @@ pt_entry_t rw; if (!(prot & VM_PROT_WRITE)) - rw = PTE_V | PTE_RO | PTE_C_CACHE; + rw = PTE_V | PTE_RO; else if ((m->oflags & VPO_UNMANAGED) == 0) { if ((m->md.pv_flags & PV_TABLE_MOD) != 0) - rw = PTE_V | PTE_D | PTE_C_CACHE; + rw = PTE_V | PTE_D; else - rw = PTE_V | PTE_C_CACHE; + rw = PTE_V; vm_page_aflag_set(m, PGA_WRITEABLE); } else /* Needn't emulate a modified bit for unmanaged pages. */ - rw = PTE_V | PTE_D | PTE_C_CACHE; + rw = PTE_V | PTE_D; return (rw); } From owner-p4-projects@FreeBSD.ORG Tue May 29 18:59:07 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 7E78E1065677; Tue, 29 May 2012 18:59:07 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 40CD51065673 for ; Tue, 29 May 2012 18:59:07 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 295DC8FC0A for ; Tue, 29 May 2012 18:59:07 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q4TIx7w1021593 for ; Tue, 29 May 2012 18:59:07 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q4TIx6DL021590 for perforce@freebsd.org; Tue, 29 May 2012 18:59:06 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Tue, 29 May 2012 18:59:06 GMT Message-Id: <201205291859.q4TIx6DL021590@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 211946 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 May 2012 18:59:07 -0000 http://p4web.freebsd.org/@@211946?ac=10 Change 211946 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/05/29 18:58:21 When printing page fault information for an unexpected exception type, explicitly print out "unknown" rather than an empty string, and include the exception type number for ease of debugging. Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/trap.c#3 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/trap.c#3 (text+ko) ==== @@ -1377,15 +1377,17 @@ read_or_write = "read"; break; default: - read_or_write = ""; + read_or_write = "unknown"; } pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0); - log(LOG_ERR, "%s: pid %d (%s), uid %d: pc %#jx got a %s fault at %#jx\n", + log(LOG_ERR, "%s: pid %d (%s), uid %d: pc %#jx got a %s fault " + "(type %#x) at %#jx\n", msg, p->p_pid, p->p_comm, p->p_ucred ? p->p_ucred->cr_uid : -1, (intmax_t)pc, read_or_write, + trap_type, (intmax_t)frame->badvaddr); /* log registers in trap frame */ From owner-p4-projects@FreeBSD.ORG Wed May 30 02:14:57 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id CC3AC1065679; Wed, 30 May 2012 02:14:56 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8EACF1065672 for ; Wed, 30 May 2012 02:14:56 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 74B7E8FC12 for ; Wed, 30 May 2012 02:14:56 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q4U2EurM094745 for ; Wed, 30 May 2012 02:14:56 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q4U2EuRa094742 for perforce@freebsd.org; Wed, 30 May 2012 02:14:56 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Wed, 30 May 2012 02:14:56 GMT Message-Id: <201205300214.q4U2EuRa094742@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 211963 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 May 2012 02:14:57 -0000 http://p4web.freebsd.org/@@211963?ac=10 Change 211963 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/05/30 02:14:54 Checkpoint work-in-progress kernel context switch support for the CHERI capability coprocessor: a template user capability is created during boot, and then used to populate user registers when a new user context is created during execve(). More explicitly manage the difference between user and kernel capability contexts, moving the existing CP2 frame to struct pcb, and adding a second one for the kernel. This is not yet believed to work, but best to submit before getting on a plane! Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#5 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.h#6 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/pcb.h#2 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/proc.h#3 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/pm_machdep.c#3 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#5 (text+ko) ==== @@ -29,6 +29,10 @@ */ #include +#include +#include + +#include #include @@ -48,6 +52,11 @@ */ /* + * Template capability delegating ambient authority to userspace processes. + */ +static struct capability cp2_user_template; + +/* * Given an existing more privileged capability (fromcrn), build a new * capability in tocrn with the contents of the passed flattened * representation. @@ -81,6 +90,18 @@ } void +cp2_capability_set_upriv(struct capability *cp) +{ + + /* + * XXXRW: Note assumption that MIPS_XUSEG_START == NULL. Perhaps + * should be a CTASSERT(). + */ + cp2_capability_set(cp, CHERI_PERM_ALL, NULL, NULL, + MIPS_XUSEG_END); +} + +void cp2_capability_set_null(struct capability *cp) { @@ -101,97 +122,42 @@ cp2_capability_copy(struct capability *cp_to, struct capability *cp_from) { - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, cp_from); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, cp_to); + cp2_capability_load(CHERI_CR_CT0, cp_from); + cp2_capability_store(CHERI_CR_CT0, cp_to); } void cp2_context_copy(struct cp2_frame *cf_destp, struct cp2_frame *cf_srcp) { - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c0); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c0); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c1); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c1); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c2); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c2); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c3); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c3); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c4); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c4); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c5); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c5); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c6); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c6); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c7); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c7); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c8); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c8); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c9); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c9); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c10); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c10); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c11); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c11); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c12); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c12); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c13); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c13); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c14); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c14); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c15); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c15); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c16); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c16); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c17); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c17); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c18); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c18); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c19); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c19); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c20); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c20); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c21); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c21); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c22); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c22); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c23); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c23); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c24); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c24); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_udc); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_udc); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_tsc); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_tsc); - - CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_pcc); - CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_pcc); + cp2_capability_copy(&cf_destp->cf_c0, &cf_srcp->cf_c0); + cp2_capability_copy(&cf_destp->cf_c1, &cf_srcp->cf_c1); + cp2_capability_copy(&cf_destp->cf_c2, &cf_srcp->cf_c2); + cp2_capability_copy(&cf_destp->cf_c3, &cf_srcp->cf_c3); + cp2_capability_copy(&cf_destp->cf_c4, &cf_srcp->cf_c4); + cp2_capability_copy(&cf_destp->cf_c5, &cf_srcp->cf_c5); + cp2_capability_copy(&cf_destp->cf_c6, &cf_srcp->cf_c6); + cp2_capability_copy(&cf_destp->cf_c7, &cf_srcp->cf_c7); + cp2_capability_copy(&cf_destp->cf_c8, &cf_srcp->cf_c8); + cp2_capability_copy(&cf_destp->cf_c9, &cf_srcp->cf_c9); + cp2_capability_copy(&cf_destp->cf_c10, &cf_srcp->cf_c10); + cp2_capability_copy(&cf_destp->cf_c11, &cf_srcp->cf_c11); + cp2_capability_copy(&cf_destp->cf_c12, &cf_srcp->cf_c12); + cp2_capability_copy(&cf_destp->cf_c13, &cf_srcp->cf_c13); + cp2_capability_copy(&cf_destp->cf_c14, &cf_srcp->cf_c14); + cp2_capability_copy(&cf_destp->cf_c15, &cf_srcp->cf_c15); + cp2_capability_copy(&cf_destp->cf_c16, &cf_srcp->cf_c16); + cp2_capability_copy(&cf_destp->cf_c17, &cf_srcp->cf_c17); + cp2_capability_copy(&cf_destp->cf_c18, &cf_srcp->cf_c18); + cp2_capability_copy(&cf_destp->cf_c19, &cf_srcp->cf_c19); + cp2_capability_copy(&cf_destp->cf_c20, &cf_srcp->cf_c20); + cp2_capability_copy(&cf_destp->cf_c21, &cf_srcp->cf_c21); + cp2_capability_copy(&cf_destp->cf_c22, &cf_srcp->cf_c22); + cp2_capability_copy(&cf_destp->cf_c23, &cf_srcp->cf_c23); + cp2_capability_copy(&cf_destp->cf_c24, &cf_srcp->cf_c24); + cp2_capability_copy(&cf_destp->cf_udc, &cf_srcp->cf_udc); + cp2_capability_copy(&cf_destp->cf_tsc, &cf_srcp->cf_tsc); + cp2_capability_copy(&cf_destp->cf_pcc, &cf_srcp->cf_pcc); } /* @@ -477,3 +443,56 @@ break; } } + +static void +cheri_init(void *arg) +{ + + /* + * Initialise a template capability that will be used when + * configuring new user processes. + * + * XXXRW: Currently, this delegates the full address space -- more + * ideally, we'd limit it to user portions of the address space, + * reinforcing the MIPS segment and ring model. + */ + cp2_capability_set_priv(&cp2_user_template); +} +SYSINIT(elf32, SI_SUB_CREATE_INIT, SI_ORDER_ANY, cheri_init, NULL); + +void +cheri_exec_setregs(struct thread *td) +{ + struct cp2_frame *cfp; + + cfp = &td->td_pcb->pcb_ucp2frame; + cp2_capability_load(CHERI_CR_CT0, &cp2_user_template); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c0); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c1); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c2); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c3); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c4); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c5); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c6); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c7); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c8); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c9); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c10); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c11); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c12); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c13); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c14); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c15); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c16); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c17); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c18); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c19); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c20); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c21); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c22); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c23); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_c24); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_udc); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_tsc); + cp2_capability_store(CHERI_CR_CT0, &cfp->cf_pcc); +} ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.h#6 (text+ko) ==== @@ -257,6 +257,20 @@ : "i" (crn_to), "i" (crn_base), "r" (offset)); \ } while (0) +static inline void +cp2_capability_load(u_int crn_to, struct capability *cp) +{ + + CP2_CR_LOAD(crn_to, CHERI_CR_KDC, cp); +} + +static inline void +cp2_capability_store(u_int crn_from, struct capability *cp) +{ + + CP2_CR_STORE(crn_from, CHERI_CR_KDC, cp); +} + /* * Extract a flattened but useful memory representation of a complete * capability register. @@ -349,15 +363,17 @@ * APIs that act on C language representations of capabilities -- but not * capabilities themselves. */ +void cp2_capability_copy(struct capability *cp_to, + struct capability *cp_from); void cp2_capability_set(struct capability *cp, uint32_t uperms, void *otypep /* eaddr */, void *basep, uint64_t length); - void cp2_capability_set_priv(struct capability *cp); +void cp2_capability_set_upriv(struct capability *cp); void cp2_capability_set_null(struct capability *cp); -void cp2_capability_copy(struct capability *cp_to, - struct capability *cp_from); void cp2_context_copy(struct cp2_frame *cf_destp, struct cp2_frame *cf_srcp); +void cheri_exec_setregs(struct thread *td); + #endif /* _MIPS_CHERI_CP2_H_ */ ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/pcb.h#2 (text+ko) ==== @@ -44,13 +44,23 @@ #include +#ifdef CPU_CHERI +#include +#endif + /* * MIPS process control block */ struct pcb { struct trapframe pcb_regs; /* saved CPU and registers */ +#ifdef CPU_CHERI + struct cp2_frame pcb_ucp2frame; +#endif __register_t pcb_context[14]; /* kernel context for resume */ +#ifdef CPU_CHERI + struct cp2_frame pcb_cp2frame; +#endif void *pcb_onfault; /* for copyin/copyout faults */ register_t pcb_tpc; }; ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/proc.h#3 (text+ko) ==== @@ -65,9 +65,6 @@ int md_pc_count; /* performance counter */ int md_pc_spill; /* performance counter spill */ void *md_tls; -#if defined(CPU_CHERI) - struct cp2_frame md_cp2frame; -#endif #ifdef CPU_CNMIPS struct octeon_cop2_state *md_cop2; /* kernel context */ struct octeon_cop2_state *md_ucop2; /* userland context */ ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/pm_machdep.c#3 (text+ko) ==== @@ -69,6 +69,10 @@ #include #include +#ifdef CPU_CHERI +#include +#endif + #define UCONTEXT_MAGIC 0xACEDBADE /* @@ -525,6 +529,7 @@ #endif #if defined(CPU_CHERI) td->td_frame->sr |= MIPS_SR_COP_2_BIT; + cheri_exec_setregs(td); #endif /* * FREEBSD_DEVELOPERS_FIXME: From owner-p4-projects@FreeBSD.ORG Thu May 31 23:36:15 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id C52B81065674; Thu, 31 May 2012 23:36:15 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 87B76106564A for ; Thu, 31 May 2012 23:36:15 +0000 (UTC) (envelope-from brooks@freebsd.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 6F9988FC16 for ; Thu, 31 May 2012 23:36:15 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q4VNaF22097044 for ; Thu, 31 May 2012 23:36:15 GMT (envelope-from brooks@freebsd.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q4VNaFSj097041 for perforce@freebsd.org; Thu, 31 May 2012 23:36:15 GMT (envelope-from brooks@freebsd.org) Date: Thu, 31 May 2012 23:36:15 GMT Message-Id: <201205312336.q4VNaFSj097041@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to brooks@freebsd.org using -f From: Brooks Davis To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 212065 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 May 2012 23:36:16 -0000 http://p4web.freebsd.org/@@212065?ac=10 Change 212065 by brooks@brooks_ecr_current on 2012/05/31 23:35:16 Checkpoint a version of the isf(4) driver with the ability to read. It appears that both devices are talking to the same 32MB chip which clearly isn't right, but the result should still be partially useful. Keep the hints commented out as it conflicts with the device required for Simon's useful flashprog tool. Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.c#3 edit .. //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.h#3 edit .. //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf_nexus.c#3 edit .. //depot/projects/ctsrd/beribsd/src/sys/mips/beri/files.beri#14 edit .. //depot/projects/ctsrd/beribsd/src/sys/mips/conf/BERI_DE4.hints#2 edit .. //depot/projects/ctsrd/beribsd/src/sys/mips/conf/BERI_DE4_SDROOT#2 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.c#3 (text+ko) ==== @@ -1,5 +1,6 @@ /*- * Copyright (c) 2012 Robert N. M. Watson + # Copyright (c) 2012 SRI International * All rights reserved. * * This software was developed by SRI International and the University of @@ -32,17 +33,19 @@ __FBSDID("$FreeBSD$"); #include +#include +#include +#include + #include -#include #include +#include #include -#include +#include #include #include -#include #include #include -#include #include #include @@ -52,7 +55,63 @@ #include +/* Read Mode */ +#define ISF_CMD_RA 0xFF /* Read Array mode */ +#define ISF_CMD_RSR 0x70 /* Read Status Register mode */ +#define ISF_CMD_RDI 0x90 /* Read Device ID/Config Reg mode */ +#define ISF_CMD_RQ 0x98 /* Read Query mode */ +#define ISF_CMD_CSR 0x50 /* Clear Status Register */ + +/* Write Mode */ +#define ISF_CMD_WPS 0x40 /* Word Program Setup */ +#define ISF_CMD_BPC 0xD0 /* Buffered Program Confirm */ + +/* Erase Mode */ +#define ISF_CMD_BES 0x20 /* Block Erase Setup */ +#define IFS_CMD_BEC 0xD0 /* Block Erase Confirm */ + +/* Block Locking/Unlocking */ +#define ISF_CMD_LBS 0x60 /* Lock Block Setup */ +#define IFS_CMD_LB 0x01 /* Lock Block */ +#define IFS_CMD_UB 0xD0 /* Unlock Block */ + +/* + * Read Device Identifier registers. + * + * NOTE: ISF_RDIR_BLC is relative to the block base address. + */ +#define ISF_REG_MC 0x00 /* Manufacture Code */ +#define ISF_REG_ID 0x01 /* Device ID Code */ +#define ISF_REG_BLC 0x02 /* Block Lock Configuration */ +#define ISF_REG_RCR 0x05 /* Read Configuration Register */ + /* + * Protection Registers + */ +#define ISF_REG_L0 0x80 /* Lock Register 0 */ +#define ISF_REG_FPP 0x81 /* 64-bit Factory Protection Register */ +#define ISF_REG_UPP 0x85 /* 64-bit User Protection Register */ +#define ISF_REG_L1 0x89 /* Lock Register 1 */ +#define ISF_REG_PP1 0x8A /* 128-bit Protection Register 1 */ +#define ISF_REG_PP2 0x92 /* 128-bit Protection Register 2 */ +#define ISF_REG_PP3 0x9A /* 128-bit Protection Register 3 */ +#define ISF_REG_PP4 0xA2 /* 128-bit Protection Register 4 */ +#define ISF_REG_PP5 0xAA /* 128-bit Protection Register 5 */ +#define ISF_REG_PP6 0xB2 /* 128-bit Protection Register 6 */ +#define ISF_REG_PP7 0xBA /* 128-bit Protection Register 7 */ +#define ISF_REG_PP8 0xC2 /* 128-bit Protection Register 8 */ +#define ISF_REG_PP9 0xCA /* 128-bit Protection Register 9 */ +#define ISF_REG_PP10 0xD2 /* 128-bit Protection Register 10 */ +#define ISF_REG_PP11 0xDA /* 128-bit Protection Register 11 */ +#define ISF_REG_PP12 0xE2 /* 128-bit Protection Register 12 */ +#define ISF_REG_PP13 0xEA /* 128-bit Protection Register 13 */ +#define ISF_REG_PP14 0xF2 /* 128-bit Protection Register 14 */ +#define ISF_REG_PP15 0xFA /* 128-bit Protection Register 15 */ +#define ISF_REG_PP16 0x102 /* 128-bit Protection Register 16 */ + +static void isf_task(void *arg); + +/* * Device driver for the Intel StrataFlash NOR flash device. This * implementation is known to work with 256Mb instances of the device, but may * also work with other 64/128/512Mb parts without much work. Multiple @@ -61,25 +120,37 @@ * part. */ -#if 0 -/* - * XXXRW: Sample bus_space I/O routines which we would like to model isf - * register and command routines on. - */ static uint16_t -isf_read_rr1(struct isf_softc *sc) +isf_read_reg(struct isf_softc *sc, uint32_t reg) +{ + + device_printf(sc->isf_dev, "isf_read_reg(0x%02x)\n", reg); + return (le16toh(bus_read_2(sc->isf_res, reg * 2))); +} + +static uint64_t +isf_read_reg64(struct isf_softc *sc, uint32_t reg) { + uint64_t val; + uint16_t *val16 = (uint16_t *)&val; - return (le16toh(bus_read_2(sc->isf_res, ISF_OFF_RR1))); + device_printf(sc->isf_dev, "isf_read_reg64(0x%02x)\n", reg); + val16[0] = bus_read_2(sc->isf_res, reg * 2); + val16[1] = bus_read_2(sc->isf_res, (reg+1) * 2); + val16[2] = bus_read_2(sc->isf_res, (reg+2) * 2); + val16[3] = bus_read_2(sc->isf_res, (reg+3) * 2); + + return(le64toh(val)); } static void -isf_write_cmd_arg(struct isf_softc *sc, uint32_t cmd_arg) +isf_write_cmd(struct isf_softc *sc, off_t off, uint16_t cmd) { - - bus_write_4(sc->isf_res, ISF_OFF_CMD_ARG, htole32(cmd_arg)); + + device_printf(sc->isf_dev, "isf_write_cmd(0x%08jx, 0x%02x)\n", + off, cmd); + bus_write_2(sc->isf_res, off, htole16(cmd)); } -#endif static void isf_read(struct isf_softc *sc, off_t off, void *data, size_t len) @@ -115,14 +186,6 @@ * disk(9) methods. */ static int -isf_disk_dump(void *arg, void *virtual, vm_offset_t physical, - off_t offset, size_t length) -{ - - panic("%s: not yet", __func__); -} - -static int isf_disk_ioctl(struct disk *disk, u_long cmd, void *data, int fflag, struct thread *td) { @@ -134,8 +197,7 @@ static void isf_disk_strategy(struct bio *bp) { - struct isf_softc *sc; - int error; + struct isf_softc *sc = bp->bio_disk->d_drv1;; /* * We advertise a block size and maximum I/O size up the stack; catch @@ -144,39 +206,89 @@ KASSERT(bp->bio_bcount == ISF_SECTORSIZE, ("%s: I/O size not %d", __func__, ISF_SECTORSIZE)); - /* - * Although the flash doesn't need sorting, we don't want to introduce - * barriers, so use bioq_disksort(). - */ - sc = bp->bio_disk->d_drv1; ISF_LOCK(sc); - error = 0; - switch (bp->bio_cmd) { - case BIO_READ: - isf_read(sc, bp->bio_pblkno * ISF_SECTORSIZE, bp->bio_data, - bp->bio_bcount); - break; + bioq_disksort(&sc->isf_bioq, bp); + ISF_WAKEUP(sc); + ISF_UNLOCK(sc); +} + +static void +isf_task(void *arg) +{ + struct isf_softc *sc = arg; + struct bio *bp; + int ss = sc->isf_disk->d_sectorsize; + + for (;;) { + ISF_LOCK(sc); + do { + bp = bioq_first(&sc->isf_bioq); + if (bp == NULL) + ISF_SLEEP(sc); + } while (bp == NULL); + bioq_remove(&sc->isf_bioq, bp); + + switch (bp->bio_cmd) { + case BIO_READ: + isf_read(sc, bp->bio_pblkno * ss, bp->bio_data, + bp->bio_bcount); + biodone(bp); + break; - case BIO_WRITE: - error = ENXIO; + case BIO_WRITE: #ifdef NOTYET - /* - * XXXRW: copied and pasted from altera_sdcard -- obviously - * won't work. - */ - isf_write(sc, bp->bio_pbklno * ISF_SECTORSIZE, bp->bio_data, - bp->bio_bcount); + /* + * XXXRW: copied and pasted from altera_sdcard -- + * obviously won't work. + */ + isf_write(sc, bp->bio_pbklno * ss, bp->bio_data, + bp->bio_bcount); #endif - break; + biofinish(bp, NULL, ENXIO); + break; + + default: + panic("%s: unsupported I/O operation %d", __func__, + bp->bio_cmd); + } + ISF_UNLOCK(sc); + } +} + +static void +isf_dump_info(struct isf_softc *sc) +{ + int i; + int32_t reg; + + isf_write_cmd(sc, 0, ISF_CMD_RDI); + device_printf(sc->isf_dev, "manufacturer code: 0x%04x\n", + isf_read_reg(sc, ISF_REG_MC)); + device_printf(sc->isf_dev, "device id code: 0x%04x\n", + isf_read_reg(sc, ISF_REG_ID)); + device_printf(sc->isf_dev, "read config register: 0x%04x\n", + isf_read_reg(sc, ISF_REG_RCR)); + + device_printf(sc->isf_dev, "lock register 0: 0x%04x\n", + isf_read_reg(sc, ISF_REG_L0)); + device_printf(sc->isf_dev, "lock register 1: 0x%04x\n", + isf_read_reg(sc, ISF_REG_L1)); + + device_printf(sc->isf_dev, "factory PPR: 0x%016jx\n", + (uintmax_t)isf_read_reg64(sc, ISF_REG_FPP)); + device_printf(sc->isf_dev, "user PPR (64-bit): 0x%016jx\n", + (uintmax_t)isf_read_reg64(sc, ISF_REG_UPP)); - default: - panic("%s: unsupported I/O operation %d", __func__, - bp->bio_cmd); + for (reg = ISF_REG_PP1, i = 1; reg <= ISF_REG_PP16; reg += 8, i++) { + /* XXX: big-endian ordering of uint64_t's */ + device_printf(sc->isf_dev, + "user PPR [%02d]: 0x%016jx%016jx\n", i, + (uintmax_t)isf_read_reg64(sc, reg+4), + (uintmax_t)isf_read_reg64(sc, reg)); } - if (error == 0) - bp->bio_resid = 0; - biofinish(bp, NULL, error); - ISF_UNLOCK(sc); + + + isf_write_cmd(sc, 0, ISF_CMD_RA); } static void @@ -184,20 +296,26 @@ { struct disk *disk; + kproc_create(&isf_task, sc, &sc->isf_proc, 0, 0, "isf"); + disk = disk_alloc(); disk->d_drv1 = sc; disk->d_name = "isf"; disk->d_unit = sc->isf_unit; disk->d_strategy = isf_disk_strategy; - disk->d_dump = isf_disk_dump; disk->d_ioctl = isf_disk_ioctl; disk->d_sectorsize = ISF_SECTORSIZE; disk->d_mediasize = ISF_MEDIASIZE; disk->d_maxsize = ISF_SECTORSIZE; sc->isf_disk = disk; + + /* XXXBED: put under bootverbose */ + isf_dump_info(sc); + disk_create(disk, DISK_VERSION); device_printf(sc->isf_dev, "%juM flash device\n", - (uintmax_t)disk->d_maxsize / (1024 * 1024)); + (uintmax_t)disk->d_mediasize / (1024 * 1024)); + } static void @@ -237,6 +355,7 @@ "Unsupported flash size %lu\n", size); return (ENXIO); } + bioq_init(&sc->isf_bioq); ISF_LOCK_INIT(sc); sc->isf_disk = NULL; isf_disk_insert(sc); ==== //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.h#3 (text+ko) ==== @@ -1,5 +1,6 @@ /*- * Copyright (c) 2012 Robert N. M. Watson + * Copyright (c) 2012 SRI International * All rights reserved. * * This software was developed by SRI International and the University of @@ -49,6 +50,7 @@ int isf_rid; struct mtx isf_lock; struct disk *isf_disk; + struct proc *isf_proc; /* * Fields relating to in-progress and pending I/O, if any. @@ -61,7 +63,10 @@ #define ISF_LOCK_DESTROY(sc) mtx_destroy(&(sc)->isf_lock) #define ISF_LOCK_INIT(sc) mtx_init(&(sc)->isf_lock, "isf", NULL, \ MTX_DEF) +#define ISF_SLEEP(sc) mtx_sleep((sc), &(sc)->isf_lock, PRIBIO, \ + "isf", 0) #define ISF_UNLOCK(sc) mtx_unlock(&(sc)->isf_lock) +#define ISF_WAKEUP(sc) wakeup((sc)) int isf_attach(struct isf_softc *sc); void isf_detach(struct isf_softc *sc); ==== //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf_nexus.c#3 (text+ko) ==== @@ -1,5 +1,6 @@ /*- * Copyright (c) 2012 Robert N. M. Watson + * Copyright (c) 2012 SRI International * All rights reserved. * * This software was developed by SRI International and the University of ==== //depot/projects/ctsrd/beribsd/src/sys/mips/beri/files.beri#14 (text+ko) ==== @@ -13,6 +13,8 @@ dev/terasic/mtl/terasic_mtl_reg.c optional terasic_mtl dev/terasic/mtl/terasic_mtl_syscons.c optional terasic_mtl dev/terasic/mtl/terasic_mtl_text.c optional terasic_mtl +dev/isf/isf.c optional isf +dev/isf/isf_nexus.c optional isf mips/beri/beri_machdep.c standard mips/mips/intr_machdep.c standard mips/mips/tick.c standard ==== //depot/projects/ctsrd/beribsd/src/sys/mips/conf/BERI_DE4.hints#2 (text+ko) ==== @@ -42,3 +42,15 @@ hint.altera_avgen.0.fileio="rw" hint.altera_avgen.0.mmapio="rwx" hint.altera_avgen.0.devname="de4flash" + +# +# General Intel StrataFlash driver +# +# To enable this you must disable the altera_avgen de4flash mapping. +# +#hint.isf.0.at="nexus0" +#hint.isf.0.maddr=0x74000000 +#hint.isf.0.msize=0x2000000 +#hint.isf.1.at="nexus0" +#hint.isf.1.maddr=0x76000000 +#hint.isf.1.msize=0x2000000 ==== //depot/projects/ctsrd/beribsd/src/sys/mips/conf/BERI_DE4_SDROOT#2 (text+ko) ==== @@ -51,6 +51,7 @@ device altera_sdcard device terasic_de4led device terasic_mtl +device isf device md device ether From owner-p4-projects@FreeBSD.ORG Fri Jun 1 21:29:58 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id A33821065672; Fri, 1 Jun 2012 21:29:58 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 656A8106566B for ; Fri, 1 Jun 2012 21:29:58 +0000 (UTC) (envelope-from brooks@freebsd.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 4F26A8FC17 for ; Fri, 1 Jun 2012 21:29:58 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q51LTwNd093571 for ; Fri, 1 Jun 2012 21:29:58 GMT (envelope-from brooks@freebsd.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q51LTwYx093568 for perforce@freebsd.org; Fri, 1 Jun 2012 21:29:58 GMT (envelope-from brooks@freebsd.org) Date: Fri, 1 Jun 2012 21:29:58 GMT Message-Id: <201206012129.q51LTwYx093568@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to brooks@freebsd.org using -f From: Brooks Davis To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 212124 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Jun 2012 21:29:59 -0000 http://p4web.freebsd.org/@@212124?ac=10 Change 212124 by brooks@brooks_ecr_current on 2012/06/01 21:29:32 Checkpoint a working write implementation in word mode, an ifdef'd non-working buffer mode write implementation, and an untested erase ioctl based on Simon's suggestion to alwasy erase 128K blocks. Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.c#4 edit .. //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.h#4 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.c#4 (text+ko) ==== @@ -1,6 +1,6 @@ /*- * Copyright (c) 2012 Robert N. M. Watson - # Copyright (c) 2012 SRI International + * Copyright (c) 2012 SRI International * All rights reserved. * * This software was developed by SRI International and the University of @@ -64,16 +64,17 @@ /* Write Mode */ #define ISF_CMD_WPS 0x40 /* Word Program Setup */ +#define ISF_CMD_BPS 0xE8 /* Buffered Program Setup */ #define ISF_CMD_BPC 0xD0 /* Buffered Program Confirm */ /* Erase Mode */ #define ISF_CMD_BES 0x20 /* Block Erase Setup */ -#define IFS_CMD_BEC 0xD0 /* Block Erase Confirm */ +#define ISF_CMD_BEC 0xD0 /* Block Erase Confirm */ /* Block Locking/Unlocking */ #define ISF_CMD_LBS 0x60 /* Lock Block Setup */ -#define IFS_CMD_LB 0x01 /* Lock Block */ -#define IFS_CMD_UB 0xD0 /* Unlock Block */ +#define ISF_CMD_LB 0x01 /* Lock Block */ +#define ISF_CMD_UB 0xD0 /* Unlock Block */ /* * Read Device Identifier registers. @@ -109,6 +110,16 @@ #define ISF_REG_PP15 0xFA /* 128-bit Protection Register 15 */ #define ISF_REG_PP16 0x102 /* 128-bit Protection Register 16 */ +#define ISF_SR_BWS (1 << 0) /* BEFP Status */ +#define ISF_SR_BLS (1 << 1) /* Block-Locked Status */ +#define ISF_SR_PSS (1 << 2) /* Program Suspend Status */ +#define ISF_SR_VPPS (1 << 3) /* Vpp Status */ +#define ISF_SR_PS (1 << 4) /* Program Status */ +#define ISF_SR_ES (1 << 5) /* Erase Status */ +#define ISF_SR_ESS (1 << 6) /* Erase Suspend Status */ +#define ISF_SR_DWS (1 << 7) /* Device Write Status */ +#define ISF_SR_FSC_MASK (ISF_SR_VPPS | ISF_SR_PS | ISF_SR_BLS) + static void isf_task(void *arg); /* @@ -152,7 +163,62 @@ bus_write_2(sc->isf_res, off, htole16(cmd)); } +static uint16_t +isf_read_status(struct isf_softc *sc, off_t off) +{ + + isf_write_cmd(sc, off, ISF_CMD_RSR); + return isf_read_reg(sc, off); +} + static void +isf_clear_status(struct isf_softc *sc) +{ + + isf_write_cmd(sc, 0, ISF_CMD_CSR); +} + +static int +isf_full_status_check(struct isf_softc *sc) +{ + int error = 0; + uint16_t status; + + status = isf_read_status(sc, 0); + if (status & ISF_SR_VPPS) { + device_printf(sc->isf_dev, "Vpp Range Error\n"); + error = EIO; + } else if (status & ISF_SR_PS) { + device_printf(sc->isf_dev, "Program Error\n"); + error = EIO; + } else if (status & ISF_SR_BLS) { + device_printf(sc->isf_dev, "Device Protect Error\n"); + error = EIO; + } + isf_clear_status(sc); + + return(error); +} + +static void +isf_unlock_block(struct isf_softc *sc, off_t off) +{ + + isf_write_cmd(sc, off, ISF_CMD_LBS); + isf_write_cmd(sc, off, ISF_CMD_UB); + isf_write_cmd(sc, off, ISF_CMD_RA); +} + +static void +isf_lock_block(struct isf_softc *sc, off_t off) +{ + + isf_write_cmd(sc, off, ISF_CMD_LBS); + isf_write_cmd(sc, off, ISF_CMD_LB); + isf_write_cmd(sc, off, ISF_CMD_RA); +} + +static void isf_read(struct isf_softc *sc, off_t off, void *data, size_t len) { @@ -166,10 +232,13 @@ bus_read_region_2(sc->isf_res, off, (uint16_t *)data, len / 2); } -#ifdef NOTYET -static void +static int isf_write(struct isf_softc *sc, off_t off, void *data, size_t len) { + int error = 0; + uint16_t *dp; + uint16_t status; + off_t coff; KASSERT((uintptr_t)data % 2 == 0, ("%s: unaligned data %p", __func__, data)); @@ -178,9 +247,81 @@ KASSERT(off % ISF_SECTORSIZE == 0, ("%s: invalid offset %ju\n", __func__, off)); - bus_write_region_2(sc->isf_res, off, (uint16_t *)data, len / 2); + isf_unlock_block(sc, off); + +#ifdef ISF_BUFFER_PROGRAM + for (dp = data, coff = off; dp - (uint16_t *)data < len / 2; + dp += 32, coff += 64) { + isf_clear_status(sc); + isf_write_cmd(sc, coff, ISF_CMD_BPS); + while ( !(isf_read_reg(sc, coff) & ISF_SR_DWS) ) + /* XXX: should have a timeout */ + isf_write_cmd(sc, coff, ISF_CMD_BPS); + + isf_write_cmd(sc, coff, 32); + //bus_write_region_2(sc->isf_res, coff, dp, 32); + for (int i = 0; i < 32; i++) + isf_write_cmd(sc, coff + i * 2, *(dp + 1)); + + isf_write_cmd(sc, coff, ISF_CMD_BPC); + + status = isf_read_reg(sc, coff); + while ( !(status & ISF_SR_DWS) ) { + if (status & ISF_SR_PSS) + panic("%s: suspend not supported", __func__); + status = isf_read_reg(sc, coff); + } + isf_full_status_check(sc); + + isf_write_cmd(sc, coff, ISF_CMD_RA); + } +#else + for (dp = data, coff = off; dp - (uint16_t *)data < len / 2; + dp++, coff += 2) { + isf_write_cmd(sc, coff, ISF_CMD_WPS); + bus_write_2(sc->isf_res, coff, *dp); + status = isf_read_reg(sc, coff); + while ( !(status & ISF_SR_DWS) ) { + if (status & ISF_SR_PSS) + panic("%s: suspend not supported", __func__); + status = isf_read_reg(sc, coff); + } + } + isf_full_status_check(sc); + isf_write_cmd(sc, coff, ISF_CMD_RA); +#endif + + isf_lock_block(sc, off); + + return error; +} + +static void +isf_erase_range(struct isf_softc *sc, off_t blk_off, size_t size) +{ + uint16_t w, status; + off_t off; + + for (off = blk_off; off < blk_off + size; off += 2) { + w = bus_read_2(sc->isf_res, off); + if (w == 0xFFFF) + continue; + + isf_clear_status(sc); + isf_unlock_block(sc, off); + isf_write_cmd(sc, off, ISF_CMD_BES); + isf_write_cmd(sc, off, ISF_CMD_BEC); + + status = isf_read_status(sc, off); + while ( !(status & ISF_SR_DWS) ) { + if (status & ISF_SR_PSS) + panic("%s: suspend not supported", __func__); + status = isf_read_status(sc, off); + } + + isf_write_cmd(sc, off, ISF_CMD_RA); + } } -#endif /* * disk(9) methods. @@ -189,9 +330,28 @@ isf_disk_ioctl(struct disk *disk, u_long cmd, void *data, int fflag, struct thread *td) { + int error = 0; + struct isf_softc *sc = disk->d_drv1; + struct isf_range *ir; - /* XXXRW: more here? */ - return (EINVAL); + switch (cmd) { + case ISF_ERASE: + ir = data; + if (ir->ir_off % ISF_ERASE_BLOCK != 0 || + ir->ir_off >= disk->d_mediasize || + ir->ir_size == 0 || + ir->ir_size % ISF_ERASE_BLOCK != 0 || + ir->ir_off + ir->ir_size > disk->d_mediasize) { + error = EINVAL; + break; + } + isf_erase_range(sc, ir->ir_off, ir->ir_size); + break; + default: + error = EINVAL; + } + + return (error); } static void @@ -218,6 +378,7 @@ struct isf_softc *sc = arg; struct bio *bp; int ss = sc->isf_disk->d_sectorsize; + int error; for (;;) { ISF_LOCK(sc); @@ -236,15 +397,30 @@ break; case BIO_WRITE: + error = 0; #ifdef NOTYET /* - * XXXRW: copied and pasted from altera_sdcard -- - * obviously won't work. + * Read in the block we want to write and check that + * we're only setting bits to 0. */ - isf_write(sc, bp->bio_pbklno * ss, bp->bio_data, + isf_read(sc, bp->bio_pblkno * ss, sc->isf_rbuf, bp->bio_bcount); + for (i = 0; i < bp->bio_bcount / 2; i++) + if (sc->isf_rbuf[i] & + (unit16_t *)bp->bio_data[i] != + (unit16_t *)bp->bio_data[i]) { + error = EIO; + break; + } #endif - biofinish(bp, NULL, ENXIO); + + if (error == 0) + error = isf_write(sc, bp->bio_pblkno * ss, + bp->bio_data, bp->bio_bcount); + if (error == 0) + biodone(bp); + else + biofinish(bp, NULL, error); break; default: @@ -355,6 +531,15 @@ "Unsupported flash size %lu\n", size); return (ENXIO); } + + isf_write_cmd(sc, 0, ISF_CMD_RDI); + if (isf_read_reg(sc, ISF_REG_ID) != 0x8961) { + device_printf(sc->isf_dev, + "Unsupported device ID 0x%04x\n", + isf_read_reg(sc, ISF_REG_ID)); + return (ENXIO); + } + bioq_init(&sc->isf_bioq); ISF_LOCK_INIT(sc); sc->isf_disk = NULL; ==== //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.h#4 (text+ko) ==== @@ -32,6 +32,13 @@ #ifndef _DEV_ISF_H_ #define _DEV_ISF_H_ +struct isf_range { + off_t ir_off; /* Offset of range to delete (set to 0xFF) */ + size_t ir_size; /* Size of range */ +}; + +#define ISF_ERASE _IOW('I', 1, struct isf_range) + /* * XXXRW: For now, support only 256Mb parts, but we may want to support others * in the future. @@ -42,7 +49,9 @@ */ #define ISF_SECTORSIZE (512) #define ISF_MEDIASIZE (256 * 1024 * 1024 / 8) +#define ISF_ERASE_BLOCK (128 * 1024) +#ifdef _KERNEL struct isf_softc { device_t isf_dev; int isf_unit; @@ -56,6 +65,7 @@ * Fields relating to in-progress and pending I/O, if any. */ struct bio_queue_head isf_bioq; + uint16_t isf_rbuf[ISF_SECTORSIZE / 2]; }; #define ISF_LOCK(sc) mtx_lock(&(sc)->isf_lock) @@ -70,5 +80,6 @@ int isf_attach(struct isf_softc *sc); void isf_detach(struct isf_softc *sc); +#endif /* _KERNEL */ #endif /* _DEV_ISF_H_ */ From owner-p4-projects@FreeBSD.ORG Fri Jun 1 22:11:36 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id ED14E1065673; Fri, 1 Jun 2012 22:11:35 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B311B106566C for ; Fri, 1 Jun 2012 22:11:35 +0000 (UTC) (envelope-from brooks@freebsd.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 7ACE78FC08 for ; Fri, 1 Jun 2012 22:11:35 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q51MBZMZ011414 for ; Fri, 1 Jun 2012 22:11:35 GMT (envelope-from brooks@freebsd.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q51MBZDB011407 for perforce@freebsd.org; Fri, 1 Jun 2012 22:11:35 GMT (envelope-from brooks@freebsd.org) Date: Fri, 1 Jun 2012 22:11:35 GMT Message-Id: <201206012211.q51MBZDB011407@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to brooks@freebsd.org using -f From: Brooks Davis To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 212127 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Jun 2012 22:11:36 -0000 http://p4web.freebsd.org/@@212127?ac=10 Change 212127 by brooks@brooks_ecr_current on 2012/06/01 22:10:33 Push the attach routine in the right direction. I think it is at least no longer a panic(9) implemenation. Lock around the ERASE ioctl. Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.c#5 edit .. //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.h#5 edit .. //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf_nexus.c#4 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.c#5 (text+ko) ==== @@ -302,6 +302,7 @@ uint16_t w, status; off_t off; + ISF_LOCK(sc); for (off = blk_off; off < blk_off + size; off += 2) { w = bus_read_2(sc->isf_res, off); if (w == 0xFFFF) @@ -321,6 +322,7 @@ isf_write_cmd(sc, off, ISF_CMD_RA); } + ISF_UNLOCK(sc); } /* @@ -384,8 +386,12 @@ ISF_LOCK(sc); do { bp = bioq_first(&sc->isf_bioq); - if (bp == NULL) - ISF_SLEEP(sc); + if (bp == NULL) { + if (sc->isf_doomed) + kproc_exit(0); + else + ISF_SLEEP(sc, sc); + } } while (bp == NULL); bioq_remove(&sc->isf_bioq, bp); @@ -472,6 +478,7 @@ { struct disk *disk; + sc->isf_doomed = 0; kproc_create(&isf_task, sc, &sc->isf_proc, 0, 0, "isf"); disk = disk_alloc(); @@ -502,6 +509,10 @@ ISF_LOCK_ASSERT(sc); KASSERT(sc->isf_disk != NULL, ("%s: isf_disk NULL", __func__)); + sc->isf_doomed = 0; + ISF_WAKEUP(sc); + ISF_SLEEP(sc, sc->isf_proc); + /* * XXXRW: Is it OK to call disk_destroy() under the mutex, or should * we be deferring that to the calling context once it is released? @@ -539,6 +550,7 @@ isf_read_reg(sc, ISF_REG_ID)); return (ENXIO); } + isf_write_cmd(sc, 0, ISF_CMD_RA); bioq_init(&sc->isf_bioq); ISF_LOCK_INIT(sc); @@ -558,10 +570,11 @@ * * XXXRW: Is the locking here right? */ + ISF_LOCK(sc); isf_disk_remove(sc); - ISF_UNLOCK(sc); bioq_flush(&sc->isf_bioq, NULL, ENXIO); KASSERT(bioq_first(&sc->isf_bioq) == NULL, ("%s: non-empty bioq", __func__)); + ISF_UNLOCK(sc); ISF_LOCK_DESTROY(sc); } ==== //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf.h#5 (text+ko) ==== @@ -60,6 +60,7 @@ struct mtx isf_lock; struct disk *isf_disk; struct proc *isf_proc; + int isf_doomed; /* * Fields relating to in-progress and pending I/O, if any. @@ -73,7 +74,7 @@ #define ISF_LOCK_DESTROY(sc) mtx_destroy(&(sc)->isf_lock) #define ISF_LOCK_INIT(sc) mtx_init(&(sc)->isf_lock, "isf", NULL, \ MTX_DEF) -#define ISF_SLEEP(sc) mtx_sleep((sc), &(sc)->isf_lock, PRIBIO, \ +#define ISF_SLEEP(sc, wait) mtx_sleep((wait), &(sc)->isf_lock, PRIBIO, \ "isf", 0) #define ISF_UNLOCK(sc) mtx_unlock(&(sc)->isf_lock) #define ISF_WAKEUP(sc) wakeup((sc)) ==== //depot/projects/ctsrd/beribsd/src/sys/dev/isf/isf_nexus.c#4 (text+ko) ====