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Date:      Sun, 22 Jul 2012 12:31:05 +0000
From:      aleek@FreeBSD.org
To:        svn-soc-all@FreeBSD.org
Subject:   socsvn commit: r239660 - in soc2012/aleek/beaglexm-armv6/sys: arm/ti/am37x arm/ti/usb boot/fdt/dts
Message-ID:  <20120722123105.5589B106564A@hub.freebsd.org>

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Author: aleek
Date: Sun Jul 22 12:31:03 2012
New Revision: 239660
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=239660

Log:
  uncommented PRCM clocks for USB

Modified:
  soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_prcm.c
  soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c
  soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts

Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_prcm.c
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_prcm.c	Sun Jul 22 11:22:04 2012	(r239659)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_prcm.c	Sun Jul 22 12:31:03 2012	(r239660)
@@ -184,8 +184,17 @@
 omap3_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
 
 static int
+omap3_clk_hsusbhost_activate(struct ti_clock_dev *clkdev);
+
+static int
+omap3_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev );
+
+static int
 omap3_clk_alwayson_null_func(struct ti_clock_dev *clkdev);
 
+static int
+omap3_clk_setup_dpll5(uint32_t mul, uint32_t div);
+
 static const struct ti_clk_details*
 omap3_clk_details(clk_ident_t id);
 
@@ -291,11 +300,11 @@
 #if 0	
 	OMAP3_GENERIC_CLOCK_DEV(MMC2_CLK),
 	OMAP3_GENERIC_CLOCK_DEV(MMC3_CLK),
+#endif
 
 	/* USB HS (high speed TLL, EHCI and OHCI) */
 	OMAP3_GENERIC_CLOCK_DEV(USBTLL_CLK),
 	OMAP3_HSUSBHOST_CLOCK_DEV(USBHSHOST_CLK),
-#endif
 	/* GPIO */
 	OMAP3_GENERIC_CLOCK_DEV(GPIO1_CLK),
 	OMAP3_GENERIC_CLOCK_DEV(GPIO2_CLK),
@@ -392,6 +401,7 @@
 		0x00, 0x10, 0x20, 25),
 	OMAP3_GENERIC_CLOCK_DETAILS(MMC3_CLK, FREQ_96MHZ, CORE_CM_OFFSET,
 		0x00, 0x10, 0x20, 30),
+#endif
 	
 	/* USB HS (high speed TLL, EHCI and OHCI) */
 	OMAP3_GENERIC_CLOCK_DETAILS(USBTLL_CLK, -1, CORE_CM_OFFSET,
@@ -399,6 +409,7 @@
 	OMAP3_GENERIC_CLOCK_DETAILS(USBHSHOST_CLK, -1, USBHOST_CM_OFFSET,
 		0x00, 0x10, 0x20, 1),
 
+#if 0
 	/* GPIO modules */
 	OMAP3_GENERIC_CLOCK_DETAILS(GPIO1_CLK, -1, WKUP_CM_OFFSET,
 		0x00, 0x10, 0x20, 3),
@@ -595,6 +606,7 @@
 			return (0);
 		}
 	}
+	printf("Error: failed to enable module with USB clock %d\n", clkdev->id);
 	return (ETIMEDOUT);
 }
 
@@ -755,6 +767,188 @@
 }
 
 /**
+ *	omap3_clk_usbhost_activate - activates a modules iinterface and func clock
+ *	@clkdev: pointer to the clock device structure.
+ *	@mem_res: array of memory resources mapped when PRCM driver attached
+ *	
+ *	
+ *
+ *	LOCKING:
+ *	Inherits the locks from the omap_prcm driver, no internal locking.
+ *
+ *	RETURNS:
+ *	Returns 0 on success or a positive error code on failure.
+ */
+static int
+omap3_clk_hsusbhost_activate(struct ti_clock_dev *clkdev)
+{
+	const struct ti_clk_details* clk_details = omap3_clk_details(clkdev->id);
+	//struct resource* clk_mem_res = mem_res[CM_INSTANCE_MEM_REGION];
+	uint32_t fclken, iclken;
+	unsigned int sysclk;
+
+	if (clk_details == NULL)
+		return (ENXIO);
+	if (clkdev->id != USBHSHOST_CLK)
+		return (EINVAL);
+	
+	/* First ensure DPLL5 is setup and running, this provides the 120M clock */
+
+	/* SYS_CLK feeds the DPLL so need that to calculate the mul & div */
+	omap3_clk_get_sysclk_freq(NULL, &sysclk);
+
+	/* Activate DPLL5 and therefore the 120M clock */
+	if (omap3_clk_setup_dpll5(120, 13) != 0)
+		return (ETIMEDOUT);
+
+	
+	/* All the 'generic' clocks have a FCLKEN, ICLKEN and IDLEST register which
+	 * is for the functional, interface and clock status regsters respectively.
+	 */
+	 
+	/* Enable the interface clock */
+	iclken = cm_read_4( clk_details->iclken_offset);
+	iclken |= 0x1;
+	cm_write_4(clk_details->iclken_offset, iclken);
+
+	/* Read back the value to ensure the write has taken place ... needed ? */
+	iclken = cm_read_4(clk_details->iclken_offset);
+
+
+	/* Enable the functional clock */
+	fclken = cm_read_4(clk_details->fclken_offset);
+	fclken |= 0x03;
+	cm_write_4(clk_details->fclken_offset, fclken);
+
+	/* Read back the value to ensure the write has taken place ... needed ? */
+	fclken = cm_read_4(clk_details->fclken_offset);
+
+
+	/* Now poll on the IDLEST register to tell us if the module has come up.
+	 * TODO: We need to take into account the parent clocks.
+	 */
+#if 0	
+	if (omap3_clk_wait_on_reg(clk_mem_res, clk_details->idlest_offset, 0x02,
+	    0x00) != 0) {
+		printf("Error: failed to enable module with USB clock %d\n", clkdev->id);
+		return (ETIMEDOUT);
+	}
+#endif
+	for( int i=0; i< MAX_MODULE_ENABLE_WAIT; ++i )
+	{
+		if( ( cm_read_4( clk_details->idlest_offset ) & 0x02 ) == 0x00 )
+		{
+			return (0);
+		}
+	}
+	printf("Error: failed to enable module with USB clock %d\n", clkdev->id);
+	return (ETIMEDOUT);
+}
+
+/**
+ *	omap3_clk_hsusbhost_deactivate - deactivates a modules clock
+ *	@clkdev: pointer to the clock device structure.
+ *	@mem_res: array of memory resources mapped when PRCM driver attached
+ *	
+ *	
+ *
+ *	LOCKING:
+ *	Inherits the locks from the omap_prcm driver, no internal locking.
+ *
+ *	RETURNS:
+ *	Returns 0 on success or a positive error code on failure.
+ */
+static int
+omap3_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev )
+{
+	const struct ti_clk_details* clk_details = omap3_clk_details(clkdev->id);
+	//struct resource* clk_mem_res = mem_res[CM_INSTANCE_MEM_REGION]; //@todo remove
+	uint32_t fclken, iclken;
+
+	if (clk_details == NULL)
+		return (ENXIO);
+	
+	
+	/* All the 'generic' clocks have a FCLKEN, ICLKEN and IDLEST register which
+	 * is for the functional, interface and clock status regsters respectively.
+	 */
+	 
+	/* Disable the interface clock */
+	iclken = cm_read_4(clk_details->iclken_offset);
+	iclken &= ~(1UL << clk_details->bit_offset);
+	cm_write_4(clk_details->iclken_offset, iclken);
+
+	/* Disable the functional clock */
+	fclken = cm_read_4(clk_details->fclken_offset);
+	fclken &= ~(1UL << clk_details->bit_offset);
+	cm_write_4(clk_details->fclken_offset, fclken);
+
+	
+	return (0);
+}
+
+/**
+ *	omap3_clk_setup_dpll5 - setup DPLL5 which is needed for the 120M_FCLK
+ *	@dev: prcm device handle
+ *
+ *	Sets up the DPLL5 at the frequency specified by the mul and div arguments
+ *	(the source clock is SYS_CLK).
+ *
+ *	LOCKING:
+ *	None
+ *
+ *	RETURNS:
+ *	Returns 0 on success otherwise ETIMEDOUT if DPLL failed to lock.
+ */
+static int
+omap3_clk_setup_dpll5(uint32_t mul, uint32_t div)
+{
+	uint32_t val;
+	
+	/* DPPL5 uses DPLL5_ALWON_FCLK as it's reference clock, this is just SYS_CLK
+	 * which on the beagleboard is 13MHz.
+	 */
+	
+	/* Set the multipler and divider values for the PLL.  We want 120Mhz so take
+	 * the system clock (13Mhz) divide by that then multiple by 120.
+	 */
+	val = ((mul & 0x7ff) << 8) | ((div - 1) & 0x7f);
+	cm_write_4(CLOCK_CTRL_CM_OFFSET + 0x4C, val);
+	
+	/* This is the clock divider from the PLL into the 120Mhz clock supplied to
+	 * the USB module. */
+	val = 0x01;
+	cm_write_4(CLOCK_CTRL_CM_OFFSET + 0x50, val);
+
+	/* PERIPH2_DPLL_FREQSEL = 0x7   (1.75 MHz—2.1 MHz)
+	 * EN_PERIPH2_DPLL = 0x7        (Enables the DPLL5 in lock mode)
+	 */
+	val = (7 << 4) | (7 << 0);
+	cm_write_4(CLOCK_CTRL_CM_OFFSET + 0x04, val);
+
+
+	/* Disable auto-idle */
+	cm_write_4(CLOCK_CTRL_CM_OFFSET + 0x34, 0x00);
+
+
+	/* Wait until the DPLL5 is locked and there is clock activity */
+#if 0
+	return (omap3_clk_wait_on_reg(cm_mem_res, (CLOCK_CTRL_CM_OFFSET + 0x24),
+	                              0x01, 0x01));
+#endif
+	for( int i=0; i< MAX_MODULE_ENABLE_WAIT; ++i )
+	{
+		if( (cm_read_4( (CLOCK_CTRL_CM_OFFSET + 0x24) ) & 0x01 ) == 0x01 )
+		{
+			return (0);
+		}
+	}
+	return (ETIMEDOUT);
+}
+
+
+
+/**
  *	omap3_clk_details - returns a pointer to the generic clock details
  *	@id: The ID of the clock to get the details for
  *

Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c	Sun Jul 22 11:22:04 2012	(r239659)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c	Sun Jul 22 12:31:03 2012	(r239660)
@@ -742,11 +742,9 @@
 static int
 omap_ehci_probe(device_t dev)
 {
-	device_printf( dev, "probing!\n\n" );
 	if (!ofw_bus_is_compatible(dev, "ti,ehci"))
 		return (ENXIO);
 
-	device_printf( dev, "probed!!!\n\n" );
 	device_set_desc(dev, OMAP_EHCI_HC_DEVSTR);
 	
 	return (BUS_PROBE_DEFAULT);

Modified: soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts	Sun Jul 22 11:22:04 2012	(r239659)
+++ soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts	Sun Jul 22 12:31:03 2012	(r239660)
@@ -168,7 +168,7 @@
 		};
 
 		ehci@48064800 {
-			compatible = "ti, ehci";
+			compatible = "ti,ehci";
 			reg = < 0x48064800 0x400 /* EHCI */
 					0x48064000 0x400 /* UHH */
 					0x48062000 0x1000 /* TLL */ >;



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