From owner-freebsd-drivers@FreeBSD.ORG Mon Apr 6 21:21:18 2015 Return-Path: Delivered-To: freebsd-drivers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 5821ABD9 for ; Mon, 6 Apr 2015 21:21:18 +0000 (UTC) Received: from bigwig.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2F3A581F for ; Mon, 6 Apr 2015 21:21:18 +0000 (UTC) Received: from ralph.baldwin.cx (pool-173-54-116-245.nwrknj.fios.verizon.net [173.54.116.245]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id A1EE6B945; Mon, 6 Apr 2015 17:21:16 -0400 (EDT) From: John Baldwin To: freebsd-drivers@freebsd.org Subject: Re: general question on interrupts handling Date: Mon, 06 Apr 2015 17:07:14 -0400 Message-ID: <1512772.cb4krpaZ39@ralph.baldwin.cx> User-Agent: KMail/4.14.2 (FreeBSD/10.1-STABLE; KDE/4.14.2; amd64; ; ) In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Mon, 06 Apr 2015 17:21:16 -0400 (EDT) Cc: =?ISO-8859-1?Q?Mat=EDas?= Perret Cantoni X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Apr 2015 21:21:18 -0000 On Thursday, March 12, 2015 06:52:25 PM Mat=EDas Perret Cantoni wrote: > Hi! >=20 > I'm writing my first interrupt handling routine of a newbus driver an= d I'm > not sure what things should I take care of in my ISR and what things = the > system will take care. >=20 > I'm working on a Xilinx Zynq-7000 platform. I'm generating a Shared > Peripheral Interrupt from the FPGA. >=20 > For example... > ... do I have to disable interrupts upon entering my ISR and enable t= hem > again before returning, o FreeBSD does it for me? > ... do I have to clear the GIC interrupt status of my interrupt or th= e > systems does it automatically when my routine returns? >=20 > Please excuse me if this is too general or silly. If you can point m= e any > documentation or sources to read, It'd be great. For a regular interrupt handler that runs in an thread context, the sys= tem will generally mask your device's interrupt until the interrupt thread = is scheduled and runs your handler. After your handler returns the interr= upt will be unmasked. For a filter interrupt handler that does not run in an interrupt thread= context, no masking is done and you generally need to mask the interrup= t yourself using a device-specific register if you cannot fully handle th= e interrupt in the filter routine. --=20 John Baldwin