From owner-p4-projects@FreeBSD.ORG Tue Feb 10 01:44:50 2015 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 259555CB; Tue, 10 Feb 2015 01:44:50 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id C05365C9 for ; Tue, 10 Feb 2015 01:44:49 +0000 (UTC) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:1900:2254:2068::682:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A938EAAB for ; Tue, 10 Feb 2015 01:44:49 +0000 (UTC) Received: from skunkworks.freebsd.org ([127.0.1.74]) by skunkworks.freebsd.org (8.14.9/8.14.9) with ESMTP id t1A1inbv095298 for ; Tue, 10 Feb 2015 01:44:49 GMT (envelope-from jmg@freebsd.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.9/8.14.9/Submit) id t1A1inM6095295 for perforce@freebsd.org; Tue, 10 Feb 2015 01:44:49 GMT (envelope-from jmg@freebsd.org) Date: Tue, 10 Feb 2015 01:44:49 GMT Message-Id: <201502100144.t1A1inM6095295@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to jmg@freebsd.org using -f From: John-Mark Gurney Subject: PERFORCE change 1205949 for review To: Perforce Change Reviews Precedence: bulk X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.18-1 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Feb 2015 01:44:50 -0000 http://p4web.freebsd.org/@@1205949?ac=10 Change 1205949 by jmg@jmg_pciehp on 2015/02/10 01:44:02 IFC @ 1205948 Affected files ... .. //depot/projects/pciehotplug/sys/amd64/amd64/apic_vector.S#2 integrate .. //depot/projects/pciehotplug/sys/amd64/amd64/genassym.c#2 integrate .. //depot/projects/pciehotplug/sys/amd64/amd64/mp_machdep.c#2 integrate .. //depot/projects/pciehotplug/sys/amd64/include/cpufunc.h#2 integrate .. //depot/projects/pciehotplug/sys/amd64/include/pvclock.h#1 branch .. //depot/projects/pciehotplug/sys/amd64/vmm/vmm_support.S#2 integrate .. //depot/projects/pciehotplug/sys/arm/broadcom/bcm2835/bcm2835_audio.c#1 branch .. //depot/projects/pciehotplug/sys/arm/broadcom/bcm2835/bcm2835_gpio.c#3 integrate .. //depot/projects/pciehotplug/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c#2 integrate .. //depot/projects/pciehotplug/sys/arm/broadcom/bcm2835/files.bcm2835#2 integrate .. //depot/projects/pciehotplug/sys/arm/broadcom/bcm2835/vc_vchi_audioserv_defs.h#1 branch .. //depot/projects/pciehotplug/sys/arm/conf/RPI-B#2 integrate .. //depot/projects/pciehotplug/sys/arm/ti/ti_gpio.c#3 integrate .. //depot/projects/pciehotplug/sys/boot/amd64/boot1.efi/fat.tmpl.bz2.uu#2 integrate .. //depot/projects/pciehotplug/sys/boot/amd64/boot1.efi/generate-fat.sh#2 integrate .. //depot/projects/pciehotplug/sys/boot/amd64/efi/main.c#2 integrate .. //depot/projects/pciehotplug/sys/boot/efi/include/efiapi.h#2 integrate .. //depot/projects/pciehotplug/sys/boot/forth/beastie.4th#2 integrate .. //depot/projects/pciehotplug/sys/boot/forth/brand.4th#2 integrate .. //depot/projects/pciehotplug/sys/cam/cam_ccb.h#2 integrate .. //depot/projects/pciehotplug/sys/cam/cam_xpt.c#2 integrate .. //depot/projects/pciehotplug/sys/cam/cam_xpt_internal.h#2 integrate .. //depot/projects/pciehotplug/sys/cam/ctl/ctl_frontend_iscsi.c#3 integrate .. //depot/projects/pciehotplug/sys/cam/ctl/ctl_frontend_iscsi.h#3 integrate .. //depot/projects/pciehotplug/sys/cam/ctl/ctl_ioctl.h#3 integrate .. //depot/projects/pciehotplug/sys/cam/scsi/scsi_xpt.c#2 integrate .. //depot/projects/pciehotplug/sys/cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c#2 integrate .. //depot/projects/pciehotplug/sys/cddl/dev/dtrace/dtrace_load.c#2 integrate .. //depot/projects/pciehotplug/sys/cddl/dev/dtrace/dtrace_unload.c#2 integrate .. //depot/projects/pciehotplug/sys/conf/dtb.mk#2 integrate .. //depot/projects/pciehotplug/sys/conf/files#4 integrate .. //depot/projects/pciehotplug/sys/conf/files.amd64#3 integrate .. //depot/projects/pciehotplug/sys/conf/files.i386#2 integrate .. //depot/projects/pciehotplug/sys/conf/kern.mk#3 integrate .. //depot/projects/pciehotplug/sys/conf/kern.opts.mk#2 integrate .. //depot/projects/pciehotplug/sys/conf/kern.pre.mk#2 integrate .. //depot/projects/pciehotplug/sys/conf/options#3 integrate .. //depot/projects/pciehotplug/sys/contrib/dev/acpica/include/actbl2.h#2 integrate .. //depot/projects/pciehotplug/sys/contrib/dev/ath/ath_hal/ar9300/ar9300.h#2 integrate .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/compat/list.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/compat/vchi_bsd.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/compat/vchi_bsd.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchi/connections/connection.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchi/message_drivers/message.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchi/vchi.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchi/vchi_cfg.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchi/vchi_cfg_internal.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchi/vchi_common.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchi/vchi_mh.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_2835.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_arm.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_arm.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_build_info.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_cfg.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_connected.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_connected.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_core.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_core.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_if.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_ioctl.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_memdrv.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_pagelist.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_proc.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_shim.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_util.c#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_util.h#1 branch .. //depot/projects/pciehotplug/sys/contrib/vchiq/interface/vchiq_arm/vchiq_version.c#1 branch .. //depot/projects/pciehotplug/sys/dev/acpica/acpi.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/cxgb/cxgb_osdep.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/cxgbe/adapter.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/cxgbe/common/t4_hw.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/cxgbe/if_cxl.c#1 branch .. //depot/projects/pciehotplug/sys/dev/cxgbe/iw_cxgbe/device.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/cxgbe/offload.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/cxgbe/t4_main.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/cxgbe/tom/t4_listen.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/cxgbe/tom/t4_tom.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/drm2/i915/i915_drv.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/drm2/i915/i915_drv.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/drm2/i915/intel_dp.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/drm2/i915/intel_iic.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/drm2/radeon/ni.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/drm2/radeon/si.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/drm2/ttm/ttm_bo.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/drm2/ttm/ttm_page_alloc.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/ed/if_ed.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/fe/if_fe_isa.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/ipmi/ipmi.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/ipmi/ipmi_kcs.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/ipmi/ipmi_smic.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/ipmi/ipmi_ssif.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/ipmi/ipmivars.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/iscsi/icl.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/iscsi/icl.h#3 integrate .. //depot/projects/pciehotplug/sys/dev/iscsi/icl_conn_if.m#2 integrate .. //depot/projects/pciehotplug/sys/dev/iscsi/icl_soft.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/iscsi/icl_wrappers.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/iscsi/iscsi.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/iscsi/iscsi.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/iscsi/iscsi_ioctl.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/pci/pci.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/sfxge/common/efsys.h#3 integrate .. //depot/projects/pciehotplug/sys/dev/sfxge/sfxge.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/sfxge/sfxge.h#3 integrate .. //depot/projects/pciehotplug/sys/dev/sfxge/sfxge_ev.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/sfxge/sfxge_mcdi.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/sfxge/sfxge_port.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/sfxge/sfxge_rx.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/sfxge/sfxge_tx.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/sfxge/sfxge_tx.h#3 integrate .. //depot/projects/pciehotplug/sys/dev/uart/uart_bus_pci.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/usb/controller/xhci.c#3 integrate .. //depot/projects/pciehotplug/sys/dev/usb/serial/u3g.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/usb/usbdevs#2 integrate .. //depot/projects/pciehotplug/sys/dev/vt/hw/vga/vt_vga.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/wpi/if_wpi.c#2 integrate .. //depot/projects/pciehotplug/sys/dev/wpi/if_wpi_debug.h#1 branch .. //depot/projects/pciehotplug/sys/dev/wpi/if_wpireg.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/wpi/if_wpivar.h#2 integrate .. //depot/projects/pciehotplug/sys/dev/xen/timer/timer.c#2 integrate .. //depot/projects/pciehotplug/sys/fs/tmpfs/tmpfs_subr.c#3 integrate .. //depot/projects/pciehotplug/sys/i386/i386/apic_vector.s#2 integrate .. //depot/projects/pciehotplug/sys/i386/i386/genassym.c#2 integrate .. //depot/projects/pciehotplug/sys/i386/i386/mp_machdep.c#2 integrate .. //depot/projects/pciehotplug/sys/i386/include/cpufunc.h#2 integrate .. //depot/projects/pciehotplug/sys/i386/include/pvclock.h#1 branch .. //depot/projects/pciehotplug/sys/i386/xen/clock.c#2 integrate .. //depot/projects/pciehotplug/sys/kern/init_main.c#2 integrate .. //depot/projects/pciehotplug/sys/kern/kern_clock.c#2 integrate .. //depot/projects/pciehotplug/sys/kern/kern_clocksource.c#2 integrate .. //depot/projects/pciehotplug/sys/kern/kern_sig.c#2 integrate .. //depot/projects/pciehotplug/sys/kern/kern_timeout.c#2 integrate .. //depot/projects/pciehotplug/sys/kern/subr_bus.c#2 integrate .. //depot/projects/pciehotplug/sys/kern/subr_hints.c#2 integrate .. //depot/projects/pciehotplug/sys/kern/sys_pipe.c#2 integrate .. //depot/projects/pciehotplug/sys/kern/uipc_shm.c#2 integrate .. //depot/projects/pciehotplug/sys/modules/Makefile#2 integrate .. //depot/projects/pciehotplug/sys/modules/cxgbe/Makefile#2 integrate .. //depot/projects/pciehotplug/sys/modules/cxgbe/if_cxl/Makefile#1 branch .. //depot/projects/pciehotplug/sys/modules/dtb/rpi/Makefile#1 branch .. //depot/projects/pciehotplug/sys/modules/wpi/Makefile#2 integrate .. //depot/projects/pciehotplug/sys/netinet/if_ether.c#2 integrate .. //depot/projects/pciehotplug/sys/netinet/in.c#2 integrate .. //depot/projects/pciehotplug/sys/netinet6/in6.c#2 integrate .. //depot/projects/pciehotplug/sys/netinet6/nd6.c#2 integrate .. //depot/projects/pciehotplug/sys/netpfil/ipfw/ip_fw_iface.c#2 integrate .. //depot/projects/pciehotplug/sys/netpfil/ipfw/ip_fw_nat.c#2 integrate .. //depot/projects/pciehotplug/sys/netpfil/ipfw/ip_fw_private.h#2 integrate .. //depot/projects/pciehotplug/sys/netpfil/ipfw/ip_fw_table.c#2 integrate .. //depot/projects/pciehotplug/sys/netpfil/ipfw/ip_fw_table_algo.c#2 integrate .. //depot/projects/pciehotplug/sys/powerpc/aim/machdep.c#2 integrate .. //depot/projects/pciehotplug/sys/powerpc/include/cpu.h#2 integrate .. //depot/projects/pciehotplug/sys/powerpc/powerpc/swtch64.S#2 integrate .. //depot/projects/pciehotplug/sys/powerpc/pseries/mmu_phyp.c#2 integrate .. //depot/projects/pciehotplug/sys/powerpc/pseries/platform_chrp.c#2 integrate .. //depot/projects/pciehotplug/sys/powerpc/pseries/xics.c#2 integrate .. //depot/projects/pciehotplug/sys/sys/bitset.h#2 integrate .. //depot/projects/pciehotplug/sys/sys/bus.h#2 integrate .. //depot/projects/pciehotplug/sys/sys/callout.h#2 integrate .. //depot/projects/pciehotplug/sys/sys/cdefs.h#3 integrate .. //depot/projects/pciehotplug/sys/sys/copyright.h#2 integrate .. //depot/projects/pciehotplug/sys/sys/cpuset.h#2 integrate .. //depot/projects/pciehotplug/sys/sys/param.h#3 integrate .. //depot/projects/pciehotplug/sys/sys/systm.h#2 integrate .. //depot/projects/pciehotplug/sys/ufs/ffs/ffs_softdep.c#3 integrate .. //depot/projects/pciehotplug/sys/x86/acpica/madt.c#2 integrate .. //depot/projects/pciehotplug/sys/x86/include/apicreg.h#2 integrate .. //depot/projects/pciehotplug/sys/x86/include/apicvar.h#2 integrate .. //depot/projects/pciehotplug/sys/x86/include/pvclock.h#1 branch .. //depot/projects/pciehotplug/sys/x86/include/specialreg.h#2 integrate .. //depot/projects/pciehotplug/sys/x86/x86/io_apic.c#2 integrate .. //depot/projects/pciehotplug/sys/x86/x86/local_apic.c#2 integrate .. //depot/projects/pciehotplug/sys/x86/x86/pvclock.c#1 branch .. //depot/projects/pciehotplug/sys/x86/xen/xen_apic.c#2 integrate Differences ... ==== //depot/projects/pciehotplug/sys/amd64/amd64/apic_vector.S#2 (text+ko) ==== @@ -28,7 +28,7 @@ * SUCH DAMAGE. * * from: vector.s, 386BSD 0.1 unknown origin - * $FreeBSD: head/sys/amd64/amd64/apic_vector.S 263001 2014-03-11 10:03:29Z royger $ + * $FreeBSD: head/sys/amd64/amd64/apic_vector.S 278473 2015-02-09 21:00:56Z kib $ */ /* @@ -39,6 +39,7 @@ #include "opt_smp.h" #include +#include #include #include "assym.s" @@ -49,6 +50,22 @@ #define LK #endif + .text + SUPERALIGN_TEXT + /* End Of Interrupt to APIC */ +as_lapic_eoi: + cmpl $0,x2apic_mode + jne 1f + movq lapic_map,%rax + movl $0,LA_EOI(%rax) + ret +1: + movl $MSR_APIC_EOI,%ecx + xorl %eax,%eax + xorl %edx,%edx + wrmsr + ret + /* * I/O Interrupt Entry Point. Rather than having one entry point for * each interrupt source, we use one entry point for each 32-bit word @@ -62,15 +79,22 @@ IDTVEC(vec_name) ; \ PUSH_FRAME ; \ FAKE_MCOUNT(TF_RIP(%rsp)) ; \ - movq lapic, %rdx ; /* pointer to local APIC */ \ + cmpl $0,x2apic_mode ; \ + je 1f ; \ + movl $(MSR_APIC_ISR0 + index),%ecx ; \ + rdmsr ; \ + jmp 2f ; \ +1: ; \ + movq lapic_map, %rdx ; /* pointer to local APIC */ \ movl LA_ISR + 16 * (index)(%rdx), %eax ; /* load ISR */ \ +2: ; \ bsrl %eax, %eax ; /* index of highest set bit in ISR */ \ - jz 1f ; \ + jz 3f ; \ addl $(32 * index),%eax ; \ movq %rsp, %rsi ; \ movl %eax, %edi ; /* pass the IRQ */ \ call lapic_handle_intr ; \ -1: ; \ +3: ; \ MEXITCOUNT ; \ jmp doreti @@ -160,8 +184,7 @@ SUPERALIGN_TEXT invltlb_ret: - movq lapic, %rax - movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ + call as_lapic_eoi POP_FRAME jmp doreti_iret @@ -228,8 +251,7 @@ IDTVEC(ipi_intr_bitmap_handler) PUSH_FRAME - movq lapic, %rdx - movl $0, LA_EOI(%rdx) /* End Of Interrupt to APIC */ + call as_lapic_eoi FAKE_MCOUNT(TF_RIP(%rsp)) @@ -245,8 +267,7 @@ IDTVEC(cpustop) PUSH_FRAME - movq lapic, %rax - movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ + call as_lapic_eoi call cpustop_handler jmp doreti @@ -260,8 +281,7 @@ PUSH_FRAME call cpususpend_handler - movq lapic, %rax - movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ + call as_lapic_eoi jmp doreti /* @@ -279,7 +299,6 @@ incq (%rax) #endif call smp_rendezvous_action - movq lapic, %rax - movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ + call as_lapic_eoi jmp doreti #endif /* SMP */ ==== //depot/projects/pciehotplug/sys/amd64/amd64/genassym.c#2 (text+ko) ==== @@ -33,7 +33,7 @@ */ #include -__FBSDID("$FreeBSD: head/sys/amd64/amd64/genassym.c 274324 2014-11-09 19:58:30Z glebius $"); +__FBSDID("$FreeBSD: head/sys/amd64/amd64/genassym.c 278473 2015-02-09 21:00:56Z kib $"); #include "opt_compat.h" #include "opt_hwpmc_hooks.h" @@ -220,13 +220,8 @@ ASSYM(PC_TSS, offsetof(struct pcpu, pc_tss)); ASSYM(PC_PM_SAVE_CNT, offsetof(struct pcpu, pc_pm_save_cnt)); -ASSYM(LA_VER, offsetof(struct LAPIC, version)); -ASSYM(LA_TPR, offsetof(struct LAPIC, tpr)); -ASSYM(LA_EOI, offsetof(struct LAPIC, eoi)); -ASSYM(LA_SVR, offsetof(struct LAPIC, svr)); -ASSYM(LA_ICR_LO, offsetof(struct LAPIC, icr_lo)); -ASSYM(LA_ICR_HI, offsetof(struct LAPIC, icr_hi)); -ASSYM(LA_ISR, offsetof(struct LAPIC, isr0)); +ASSYM(LA_EOI, LAPIC_EOI * LAPIC_MEM_MUL); +ASSYM(LA_ISR, LAPIC_ISR0 * LAPIC_MEM_MUL); ASSYM(KCSEL, GSEL(GCODE_SEL, SEL_KPL)); ASSYM(KDSEL, GSEL(GDATA_SEL, SEL_KPL)); ==== //depot/projects/pciehotplug/sys/amd64/amd64/mp_machdep.c#2 (text+ko) ==== @@ -25,7 +25,7 @@ */ #include -__FBSDID("$FreeBSD: head/sys/amd64/amd64/mp_machdep.c 271409 2014-09-10 21:37:47Z jhb $"); +__FBSDID("$FreeBSD: head/sys/amd64/amd64/mp_machdep.c 278473 2015-02-09 21:00:56Z kib $"); #include "opt_cpu.h" #include "opt_ddb.h" @@ -705,8 +705,11 @@ wrmsr(MSR_STAR, msr); wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); - /* Disable local APIC just to be sure. */ - lapic_disable(); + /* + * On real hardware, switch to x2apic mode if possible. + * Disable local APIC until BSP directed APs to run. + */ + lapic_xapic_mode(); /* signal our startup to the BSP. */ mp_naps++; @@ -1065,14 +1068,27 @@ { /* + * This attempts to follow the algorithm described in the + * Intel Multiprocessor Specification v1.4 in section B.4. + * For each IPI, we allow the local APIC ~20us to deliver the + * IPI. If that times out, we panic. + */ + + /* * first we do an INIT IPI: this INIT IPI might be run, resetting * and running the target CPU. OR this INIT IPI might be latched (P5 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be * ignored. */ - lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | + lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL | APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); - lapic_ipi_wait(-1); + lapic_ipi_wait(20); + + /* Explicitly deassert the INIT IPI. */ + lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL | + APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, + apic_id); + DELAY(10000); /* wait ~10mS */ /* @@ -1084,9 +1100,11 @@ * will run. */ lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | - APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | + APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | vector, apic_id); - lapic_ipi_wait(-1); + if (!lapic_ipi_wait(20)) + panic("Failed to deliver first STARTUP IPI to APIC %d", + apic_id); DELAY(200); /* wait ~200uS */ /* @@ -1096,9 +1114,12 @@ * recognized after hardware RESET or INIT IPI. */ lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | - APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | + APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | vector, apic_id); - lapic_ipi_wait(-1); + if (!lapic_ipi_wait(20)) + panic("Failed to deliver second STARTUP IPI to APIC %d", + apic_id); + DELAY(200); /* wait ~200uS */ } ==== //depot/projects/pciehotplug/sys/amd64/include/cpufunc.h#2 (text+ko) ==== @@ -27,7 +27,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD: head/sys/amd64/include/cpufunc.h 261891 2014-02-14 15:18:37Z avg $ + * $FreeBSD: head/sys/amd64/include/cpufunc.h 278473 2015-02-09 21:00:56Z kib $ */ /* @@ -343,6 +343,15 @@ return (low | ((uint64_t)high << 32)); } +static __inline uint32_t +rdmsr32(u_int msr) +{ + uint32_t low; + + __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx"); + return (low); +} + static __inline uint64_t rdpmc(u_int pmc) { @@ -826,6 +835,7 @@ u_long rcr3(void); u_long rcr4(void); uint64_t rdmsr(u_int msr); +uint32_t rdmsr32(u_int msr); uint64_t rdpmc(u_int pmc); uint64_t rdr0(void); uint64_t rdr1(void); ==== //depot/projects/pciehotplug/sys/amd64/vmm/vmm_support.S#2 (text+ko) ==== @@ -23,20 +23,21 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD: head/sys/amd64/vmm/vmm_support.S 245678 2013-01-20 03:42:49Z neel $ + * $FreeBSD: head/sys/amd64/vmm/vmm_support.S 278473 2015-02-09 21:00:56Z kib $ */ #define LOCORE #include -#define LA_EOI 0xB0 - .text SUPERALIGN_TEXT IDTVEC(justreturn) + pushq %rdx pushq %rax - movq lapic, %rax - movl $0, LA_EOI(%rax) + pushq %rcx + call as_lapic_eoi + popq %rcx popq %rax - iretq + popq %rdx + jmp doreti_iret ==== //depot/projects/pciehotplug/sys/arm/broadcom/bcm2835/bcm2835_gpio.c#3 (text+ko) ==== @@ -26,31 +26,24 @@ * */ #include -__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_gpio.c 277996 2015-01-31 19:32:14Z loos $"); +__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_gpio.c 278215 2015-02-04 18:15:28Z loos $"); #include #include #include - +#include +#include #include +#include #include +#include #include -#include -#include -#include #include #include -#include -#include -#include -#include -#include -#include #include #include -#include #include @@ -65,6 +58,7 @@ #define BCM_GPIO_IRQS 4 #define BCM_GPIO_PINS 54 +#define BCM_GPIO_PINS_PER_BANK 32 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) @@ -89,12 +83,15 @@ struct resource * sc_res[BCM_GPIO_IRQS + 1]; bus_space_tag_t sc_bst; bus_space_handle_t sc_bsh; - void * sc_intrhand; + void * sc_intrhand[BCM_GPIO_IRQS]; int sc_gpio_npins; int sc_ro_npins; int sc_ro_pins[BCM_GPIO_PINS]; struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS]; + struct intr_event * sc_events[BCM_GPIO_PINS]; struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS]; + enum intr_trigger sc_irq_trigger[BCM_GPIO_PINS]; + enum intr_polarity sc_irq_polarity[BCM_GPIO_PINS]; }; enum bcm_gpio_pud { @@ -103,21 +100,35 @@ BCM_GPIO_PULLUP, }; -#define BCM_GPIO_LOCK(_sc) mtx_lock(&_sc->sc_mtx) -#define BCM_GPIO_UNLOCK(_sc) mtx_unlock(&_sc->sc_mtx) -#define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) +#define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) +#define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) +#define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) +#define BCM_GPIO_WRITE(_sc, _off, _val) \ + bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val) +#define BCM_GPIO_READ(_sc, _off) \ + bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off) +#define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \ + BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits)) +#define BCM_GPIO_SET_BITS(_sc, _off, _bits) \ + BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits) +#define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK) +#define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK)) -#define BCM_GPIO_GPFSEL(_bank) 0x00 + _bank * 4 -#define BCM_GPIO_GPSET(_bank) 0x1c + _bank * 4 -#define BCM_GPIO_GPCLR(_bank) 0x28 + _bank * 4 -#define BCM_GPIO_GPLEV(_bank) 0x34 + _bank * 4 -#define BCM_GPIO_GPPUD(_bank) 0x94 -#define BCM_GPIO_GPPUDCLK(_bank) 0x98 + _bank * 4 +#define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */ +#define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */ +#define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */ +#define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */ +#define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */ +#define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */ +#define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */ +#define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */ +#define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */ +#define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */ +#define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */ +#define BCM_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */ +#define BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */ -#define BCM_GPIO_WRITE(_sc, _off, _val) \ - bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) -#define BCM_GPIO_READ(_sc, _off) \ - bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) +static struct bcm_gpio_softc *bcm_gpio_sc = NULL; static int bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin) @@ -665,6 +676,40 @@ } static int +bcm_gpio_intr(void *arg) +{ + int bank_last, irq; + struct bcm_gpio_softc *sc; + struct intr_event *event; + uint32_t bank, mask, reg; + + sc = (struct bcm_gpio_softc *)arg; + reg = 0; + bank_last = -1; + for (irq = 0; irq < BCM_GPIO_PINS; irq++) { + bank = BCM_GPIO_BANK(irq); + mask = BCM_GPIO_MASK(irq); + if (bank != bank_last) { + reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); + bank_last = bank; + } + if (reg & mask) { + event = sc->sc_events[irq]; + if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers)) + intr_event_handle(event, NULL); + else { + device_printf(sc->sc_dev, "Stray IRQ %d\n", + irq); + } + /* Clear the Status bit by writing '1' to it. */ + BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), mask); + } + } + + return (FILTER_HANDLED); +} + +static int bcm_gpio_probe(device_t dev) { @@ -679,6 +724,39 @@ } static int +bcm_gpio_intr_attach(device_t dev) +{ + struct bcm_gpio_softc *sc; + int i; + + sc = device_get_softc(dev); + for (i = 0; i < BCM_GPIO_IRQS; i++) { + if (bus_setup_intr(dev, sc->sc_res[i + 1], + INTR_TYPE_MISC | INTR_MPSAFE, bcm_gpio_intr, + NULL, sc, &sc->sc_intrhand[i]) != 0) { + return (-1); + } + } + + return (0); +} + +static void +bcm_gpio_intr_detach(device_t dev) +{ + struct bcm_gpio_softc *sc; + int i; + + sc = device_get_softc(dev); + for (i = 0; i < BCM_GPIO_IRQS; i++) { + if (sc->sc_intrhand[i]) { + bus_teardown_intr(dev, sc->sc_res[i + 1], + sc->sc_intrhand[i]); + } + } +} + +static int bcm_gpio_attach(device_t dev) { int i, j; @@ -686,30 +764,34 @@ struct bcm_gpio_softc *sc; uint32_t func; - sc = device_get_softc(dev); - sc->sc_dev = dev; - mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_DEF); + if (bcm_gpio_sc != NULL) + return (ENXIO); + + bcm_gpio_sc = sc = device_get_softc(dev); + sc->sc_dev = dev; + mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN); if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) { device_printf(dev, "cannot allocate resources\n"); goto fail; } sc->sc_bst = rman_get_bustag(sc->sc_res[0]); sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); - + /* Setup the GPIO interrupt handler. */ + if (bcm_gpio_intr_attach(dev)) { + device_printf(dev, "unable to setup the gpio irq handler\n"); + goto fail; + } /* Find our node. */ gpio = ofw_bus_get_node(sc->sc_dev); - if (!OF_hasprop(gpio, "gpio-controller")) /* Node is not a GPIO controller. */ goto fail; - /* * Find the read-only pins. These are pins we never touch or bad * things could happen. */ if (bcm_gpio_get_reserved_pins(sc) == -1) goto fail; - /* Initialize the software controlled pins. */ for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) { snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, @@ -718,6 +800,9 @@ sc->sc_gpio_pins[i].gp_pin = j; sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS; sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func); + /* The default is active-low interrupts. */ + sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL; + sc->sc_irq_polarity[i] = INTR_POLARITY_LOW; i++; } sc->sc_gpio_npins = i; @@ -729,6 +814,7 @@ return (0); fail: + bcm_gpio_intr_detach(dev); bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res); mtx_destroy(&sc->sc_mtx); @@ -742,6 +828,177 @@ return (EBUSY); } +static uint32_t +bcm_gpio_intr_reg(struct bcm_gpio_softc *sc, unsigned int irq, uint32_t bank) +{ + + if (irq > BCM_GPIO_PINS) + return (0); + if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) { + if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) + return (BCM_GPIO_GPLEN(bank)); + else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) + return (BCM_GPIO_GPHEN(bank)); + } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) { + if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) + return (BCM_GPIO_GPFEN(bank)); + else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) + return (BCM_GPIO_GPREN(bank)); + } + + return (0); +} + +static void +bcm_gpio_mask_irq(void *source) +{ + uint32_t bank, mask, reg; + unsigned int irq; + + irq = (unsigned int)source; + if (irq > BCM_GPIO_PINS) + return; + if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq)) + return; + bank = BCM_GPIO_BANK(irq); + mask = BCM_GPIO_MASK(irq); + BCM_GPIO_LOCK(bcm_gpio_sc); + reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank); + if (reg != 0) + BCM_GPIO_CLEAR_BITS(bcm_gpio_sc, reg, mask); + BCM_GPIO_UNLOCK(bcm_gpio_sc); +} + +static void +bcm_gpio_unmask_irq(void *source) +{ + uint32_t bank, mask, reg; + unsigned int irq; + + irq = (unsigned int)source; + if (irq > BCM_GPIO_PINS) + return; + if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq)) + return; + bank = BCM_GPIO_BANK(irq); + mask = BCM_GPIO_MASK(irq); + BCM_GPIO_LOCK(bcm_gpio_sc); + reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank); + if (reg != 0) + BCM_GPIO_SET_BITS(bcm_gpio_sc, reg, mask); + BCM_GPIO_UNLOCK(bcm_gpio_sc); +} + +static int +bcm_gpio_activate_resource(device_t bus, device_t child, int type, int rid, + struct resource *res) +{ + int pin; + + if (type != SYS_RES_IRQ) + return (ENXIO); + /* Unmask the interrupt. */ + pin = rman_get_start(res); + bcm_gpio_unmask_irq((void *)pin); + + return (0); +} + +static int +bcm_gpio_deactivate_resource(device_t bus, device_t child, int type, int rid, + struct resource *res) +{ + int pin; + + if (type != SYS_RES_IRQ) + return (ENXIO); + /* Mask the interrupt. */ + pin = rman_get_start(res); + bcm_gpio_mask_irq((void *)pin); + + return (0); +} + +static int +bcm_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, + enum intr_polarity pol) +{ + int bank; + struct bcm_gpio_softc *sc; + uint32_t mask, oldreg, reg; + + if (irq > BCM_GPIO_PINS) + return (EINVAL); + /* There is no standard trigger or polarity. */ + if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) + return (EINVAL); + sc = device_get_softc(dev); + if (bcm_gpio_pin_is_ro(sc, irq)) + return (EINVAL); + bank = BCM_GPIO_BANK(irq); + mask = BCM_GPIO_MASK(irq); + BCM_GPIO_LOCK(sc); + oldreg = bcm_gpio_intr_reg(sc, irq, bank); + sc->sc_irq_trigger[irq] = trig; + sc->sc_irq_polarity[irq] = pol; + reg = bcm_gpio_intr_reg(sc, irq, bank); + if (reg != 0) + BCM_GPIO_SET_BITS(sc, reg, mask); + if (reg != oldreg && oldreg != 0) + BCM_GPIO_CLEAR_BITS(sc, oldreg, mask); + BCM_GPIO_UNLOCK(sc); + + return (0); +} + +static int +bcm_gpio_setup_intr(device_t bus, device_t child, struct resource *ires, + int flags, driver_filter_t *filt, driver_intr_t *handler, + void *arg, void **cookiep) +{ + struct bcm_gpio_softc *sc; + struct intr_event *event; + int pin, error; + + sc = device_get_softc(bus); + pin = rman_get_start(ires); + if (pin > BCM_GPIO_PINS) + panic("%s: bad pin %d", __func__, pin); + event = sc->sc_events[pin]; + if (event == NULL) { + error = intr_event_create(&event, (void *)pin, 0, pin, + bcm_gpio_mask_irq, bcm_gpio_unmask_irq, NULL, NULL, + "gpio%d pin%d:", device_get_unit(bus), pin); + if (error != 0) + return (error); + sc->sc_events[pin] = event; + } + intr_event_add_handler(event, device_get_nameunit(child), filt, + handler, arg, intr_priority(flags), flags, cookiep); + + return (0); +} + +static int +bcm_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires, + void *cookie) +{ + struct bcm_gpio_softc *sc; + int pin, err; + + sc = device_get_softc(dev); + pin = rman_get_start(ires); + if (pin > BCM_GPIO_PINS) + panic("%s: bad pin %d", __func__, pin); + if (sc->sc_events[pin] == NULL) + panic("Trying to teardown unoccupied IRQ"); + err = intr_event_remove_handler(cookie); + if (!err) + sc->sc_events[pin] = NULL; + + return (err); +} + static phandle_t bcm_gpio_get_node(device_t bus, device_t dev) { @@ -767,6 +1024,13 @@ DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle), + /* Bus interface */ + DEVMETHOD(bus_activate_resource, bcm_gpio_activate_resource), + DEVMETHOD(bus_deactivate_resource, bcm_gpio_deactivate_resource), + DEVMETHOD(bus_config_intr, bcm_gpio_config_intr), + DEVMETHOD(bus_setup_intr, bcm_gpio_setup_intr), + DEVMETHOD(bus_teardown_intr, bcm_gpio_teardown_intr), + /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node), ==== //depot/projects/pciehotplug/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c#2 (text+ko) ==== @@ -25,36 +25,21 @@ * */ #include -__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c 277346 2015-01-18 20:47:21Z ian $"); +__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c 278213 2015-02-04 16:36:51Z loos $"); #include #include -#include #include -#include -#include #include -#include #include #include #include #include -#include -#include #include #include #include -#include -#include -#include -#include - #include -#include -#include -#include -#include #include #include @@ -82,19 +67,9 @@ #define dprintf(fmt, args...) #endif -/* - * Arasan HC seems to have problem with Data CRC on lower frequencies. - * Use this tunable to cap initialization sequence frequency at higher - * value. Default is standard 400kHz. - * HS mode brings too many problems for most of cards, so disable HS mode - * until a better fix comes up. - * HS mode still can be enabled with the tunable. - */ -static int bcm2835_sdhci_min_freq = 400000; static int bcm2835_sdhci_hs = 1; static int bcm2835_sdhci_pio_mode = 0; -TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); @@ -211,16 +186,12 @@ RF_ACTIVE); if (!sc->sc_irq_res) { device_printf(dev, "cannot allocate interrupt\n"); - bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); err = ENXIO; goto fail; } >>> TRUNCATED FOR MAIL (1000 lines) <<<