Date: Sun, 20 Aug 2017 21:02:44 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r322727 - in vendor/llvm/dist: . docs include/llvm/CodeGen include/llvm/ExecutionEngine/Orc include/llvm/Object lib/Analysis lib/CodeGen lib/CodeGen/SelectionDAG lib/DebugInfo/DWARF lib... Message-ID: <201708202102.v7KL2ia0015324@repo.freebsd.org>
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Author: dim Date: Sun Aug 20 21:02:43 2017 New Revision: 322727 URL: https://svnweb.freebsd.org/changeset/base/322727 Log: Vendor import of llvm release_50 branch r311219: https://llvm.org/svn/llvm-project/llvm/branches/release_50@311219 Added: vendor/llvm/dist/test/Analysis/ScalarEvolution/max-addrec-size.ll vendor/llvm/dist/test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir vendor/llvm/dist/test/CodeGen/ARM/virtregrewriter-subregliveness.mir vendor/llvm/dist/test/CodeGen/X86/pr33349.ll vendor/llvm/dist/test/CodeGen/X86/pr34088.ll vendor/llvm/dist/test/CodeGen/X86/select-mmx.ll vendor/llvm/dist/test/Instrumentation/DataFlowSanitizer/Inputs/shadow-args-abilist.txt (contents, props changed) vendor/llvm/dist/test/Instrumentation/DataFlowSanitizer/shadow-args-zext.ll vendor/llvm/dist/test/Transforms/BDCE/invalidate-assumptions.ll vendor/llvm/dist/test/Transforms/SimplifyCFG/pr34131.ll vendor/llvm/dist/utils/lit/tests/Inputs/max-failures/ vendor/llvm/dist/utils/lit/tests/Inputs/max-failures/lit.cfg Modified: vendor/llvm/dist/CMakeLists.txt vendor/llvm/dist/docs/LangRef.rst vendor/llvm/dist/docs/ReleaseNotes.rst vendor/llvm/dist/include/llvm/CodeGen/SelectionDAG.h vendor/llvm/dist/include/llvm/ExecutionEngine/Orc/LazyEmittingLayer.h vendor/llvm/dist/include/llvm/Object/COFFImportFile.h vendor/llvm/dist/lib/Analysis/ScalarEvolution.cpp vendor/llvm/dist/lib/Analysis/ValueTracking.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp vendor/llvm/dist/lib/CodeGen/VirtRegMap.cpp vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFContext.cpp vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFVerifier.cpp vendor/llvm/dist/lib/Object/COFFImportFile.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp vendor/llvm/dist/lib/Target/ARM/ARMExpandPseudoInsts.cpp vendor/llvm/dist/lib/Target/ARM/ARMInstrInfo.td vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td vendor/llvm/dist/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp vendor/llvm/dist/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp vendor/llvm/dist/lib/Transforms/Scalar/BDCE.cpp vendor/llvm/dist/test/CodeGen/ARM/cmpxchg-O0.ll vendor/llvm/dist/test/CodeGen/X86/adx-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/avx512bw-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/avx512bwvl-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-128-v16.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-128-v8.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v16.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v32.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-512-v32.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-512-v64.ll vendor/llvm/dist/test/Instrumentation/DataFlowSanitizer/abilist.ll vendor/llvm/dist/test/Transforms/IndVarSimplify/exit_value_test2.ll vendor/llvm/dist/tools/llvm-objdump/llvm-objdump.cpp vendor/llvm/dist/utils/lit/lit/LitConfig.py vendor/llvm/dist/utils/lit/lit/TestRunner.py vendor/llvm/dist/utils/lit/lit/formats/__init__.py vendor/llvm/dist/utils/lit/lit/formats/base.py vendor/llvm/dist/utils/lit/lit/formats/shtest.py vendor/llvm/dist/utils/lit/lit/run.py vendor/llvm/dist/utils/lit/tests/max-failures.py vendor/llvm/dist/utils/lit/tests/selecting.py vendor/llvm/dist/utils/release/test-release.sh Modified: vendor/llvm/dist/CMakeLists.txt ============================================================================== --- vendor/llvm/dist/CMakeLists.txt Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/CMakeLists.txt Sun Aug 20 21:02:43 2017 (r322727) @@ -314,6 +314,7 @@ set(LLVM_CMAKE_PATH ${LLVM_MAIN_SRC_DIR}/cmake/modules set(LLVM_EXAMPLES_BINARY_DIR ${LLVM_BINARY_DIR}/examples) set(LLVM_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/include) +# List of all targets to be built by default: set(LLVM_ALL_TARGETS AArch64 AMDGPU @@ -325,7 +326,6 @@ set(LLVM_ALL_TARGETS MSP430 NVPTX PowerPC - RISCV Sparc SystemZ X86 Modified: vendor/llvm/dist/docs/LangRef.rst ============================================================================== --- vendor/llvm/dist/docs/LangRef.rst Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/docs/LangRef.rst Sun Aug 20 21:02:43 2017 (r322727) @@ -5369,6 +5369,10 @@ The following behaviors are supported: nodes. However, duplicate entries in the second list are dropped during the append operation. + * - 7 + - **Max** + Takes the max of the two values, which are required to be integers. + It is an error for a particular unique flag ID to have multiple behaviors, except in the case of **Require** (which adds restrictions on another metadata value) or **Override**. Modified: vendor/llvm/dist/docs/ReleaseNotes.rst ============================================================================== --- vendor/llvm/dist/docs/ReleaseNotes.rst Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/docs/ReleaseNotes.rst Sun Aug 20 21:02:43 2017 (r322727) @@ -117,6 +117,18 @@ Changes to the X86 Target * Added support for AMD Lightweight Profiling (LWP) instructions. +* Avoid using slow LEA instructions. + +* Use alternative sequences for multiply by constant. + +* Improved lowering of strided shuffles. + +* Improved the AVX512 cost model used by the vectorizer. + +* Fix scalar code performance when AVX512 is enabled by making i1's illegal. + +* Fixed many inline assembly bugs. + Changes to the AMDGPU Target ----------------------------- @@ -160,7 +172,29 @@ Changes to the C API External Open Source Projects Using LLVM 5 ========================================== -* A project... +Zig Programming Language +------------------------ + +`Zig <http://ziglang.org>`_ is an open-source programming language designed +for robustness, optimality, and clarity. It integrates closely with C and is +intended to eventually take the place of C. It uses LLVM to produce highly +optimized native code and to cross-compile for any target out of the box. Zig +is in alpha; with a beta release expected in September. + +LDC - the LLVM-based D compiler +------------------------------- + +`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It +pragmatically combines efficiency, control, and modeling power, with safety and +programmer productivity. D supports powerful concepts like Compile-Time Function +Execution (CTFE) and Template Meta-Programming, provides an innovative approach +to concurrency and offers many classical paradigms. + +`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler +combined with LLVM as backend to produce efficient native code. LDC targets +x86/x86_64 systems like Linux, OS X, FreeBSD and Windows and also Linux on ARM +and PowerPC (32/64 bit). Ports to other architectures like AArch64 and MIPS64 +are underway. Additional Information Modified: vendor/llvm/dist/include/llvm/CodeGen/SelectionDAG.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/SelectionDAG.h Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/include/llvm/CodeGen/SelectionDAG.h Sun Aug 20 21:02:43 2017 (r322727) @@ -1220,8 +1220,9 @@ class SelectionDAG { (public) /// If an existing load has uses of its chain, create a token factor node with /// that chain and the new memory node's chain and update users of the old /// chain to the token factor. This ensures that the new memory node will have - /// the same relative memory dependency position as the old load. - void makeEquivalentMemoryOrdering(LoadSDNode *Old, SDValue New); + /// the same relative memory dependency position as the old load. Returns the + /// new merged load chain. + SDValue makeEquivalentMemoryOrdering(LoadSDNode *Old, SDValue New); /// Topological-sort the AllNodes list and a /// assign a unique node id for each node in the DAG based on their Modified: vendor/llvm/dist/include/llvm/ExecutionEngine/Orc/LazyEmittingLayer.h ============================================================================== --- vendor/llvm/dist/include/llvm/ExecutionEngine/Orc/LazyEmittingLayer.h Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/include/llvm/ExecutionEngine/Orc/LazyEmittingLayer.h Sun Aug 20 21:02:43 2017 (r322727) @@ -94,9 +94,9 @@ template <typename BaseLayerT> class LazyEmittingLayer llvm_unreachable("Invalid emit-state."); } - void removeModuleFromBaseLayer(BaseLayerT &BaseLayer) { - if (EmitState != NotEmitted) - BaseLayer.removeModule(Handle); + Error removeModuleFromBaseLayer(BaseLayerT& BaseLayer) { + return EmitState != NotEmitted ? BaseLayer.removeModule(Handle) + : Error::success(); } void emitAndFinalize(BaseLayerT &BaseLayer) { @@ -226,9 +226,9 @@ template <typename BaseLayerT> class LazyEmittingLayer /// This method will free the memory associated with the given module, both /// in this layer, and the base layer. Error removeModule(ModuleHandleT H) { - (*H)->removeModuleFromBaseLayer(BaseLayer); + Error Err = (*H)->removeModuleFromBaseLayer(BaseLayer); ModuleList.erase(H); - return Error::success(); + return Err; } /// @brief Search for the given named symbol. Modified: vendor/llvm/dist/include/llvm/Object/COFFImportFile.h ============================================================================== --- vendor/llvm/dist/include/llvm/Object/COFFImportFile.h Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/include/llvm/Object/COFFImportFile.h Sun Aug 20 21:02:43 2017 (r322727) @@ -73,6 +73,7 @@ class COFFImportFile : public SymbolicFile { (private) struct COFFShortExport { std::string Name; std::string ExtName; + std::string SymbolName; uint16_t Ordinal = 0; bool Noname = false; @@ -98,7 +99,8 @@ struct COFFShortExport { std::error_code writeImportLibrary(StringRef ImportName, StringRef Path, ArrayRef<COFFShortExport> Exports, - COFF::MachineTypes Machine); + COFF::MachineTypes Machine, + bool MakeWeakAliases); } // namespace object } // namespace llvm Modified: vendor/llvm/dist/lib/Analysis/ScalarEvolution.cpp ============================================================================== --- vendor/llvm/dist/lib/Analysis/ScalarEvolution.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Analysis/ScalarEvolution.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -162,6 +162,11 @@ static cl::opt<unsigned> cl::desc("Maximum depth of recursive SExt/ZExt"), cl::init(8)); +static cl::opt<unsigned> + MaxAddRecSize("scalar-evolution-max-add-rec-size", cl::Hidden, + cl::desc("Max coefficients in AddRec during evolving"), + cl::init(16)); + //===----------------------------------------------------------------------===// // SCEV class definitions //===----------------------------------------------------------------------===// @@ -2878,6 +2883,12 @@ const SCEV *ScalarEvolution::getMulExpr(SmallVectorImp if (!OtherAddRec || OtherAddRec->getLoop() != AddRecLoop) continue; + // Limit max number of arguments to avoid creation of unreasonably big + // SCEVAddRecs with very complex operands. + if (AddRec->getNumOperands() + OtherAddRec->getNumOperands() - 1 > + MaxAddRecSize) + continue; + bool Overflow = false; Type *Ty = AddRec->getType(); bool LargerThan64Bits = getTypeSizeInBits(Ty) > 64; @@ -7582,6 +7593,25 @@ const SCEV *ScalarEvolution::computeSCEVAtScope(const const SCEV *BackedgeTakenCount = getBackedgeTakenCount(LI); if (const SCEVConstant *BTCC = dyn_cast<SCEVConstant>(BackedgeTakenCount)) { + + // This trivial case can show up in some degenerate cases where + // the incoming IR has not yet been fully simplified. + if (BTCC->getValue()->isZero()) { + Value *InitValue = nullptr; + bool MultipleInitValues = false; + for (unsigned i = 0; i < PN->getNumIncomingValues(); i++) { + if (!LI->contains(PN->getIncomingBlock(i))) { + if (!InitValue) + InitValue = PN->getIncomingValue(i); + else if (InitValue != PN->getIncomingValue(i)) { + MultipleInitValues = true; + break; + } + } + if (!MultipleInitValues && InitValue) + return getSCEV(InitValue); + } + } // Okay, we know how many times the containing loop executes. If // this is a constant evolving PHI node, get the final value at // the specified iteration number. Modified: vendor/llvm/dist/lib/Analysis/ValueTracking.cpp ============================================================================== --- vendor/llvm/dist/lib/Analysis/ValueTracking.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Analysis/ValueTracking.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -4458,6 +4458,10 @@ Optional<bool> llvm::isImpliedCondition(const Value *L unsigned Depth, AssumptionCache *AC, const Instruction *CxtI, const DominatorTree *DT) { + // Bail out when we hit the limit. + if (Depth == MaxDepth) + return None; + // A mismatch occurs when we compare a scalar cmp to a vector cmp, for example. if (LHS->getType() != RHS->getType()) return None; Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -302,7 +302,21 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VE } SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) { - SDValue Cond = GetScalarizedVector(N->getOperand(0)); + SDValue Cond = N->getOperand(0); + EVT OpVT = Cond.getValueType(); + SDLoc DL(N); + // The vselect result and true/value operands needs scalarizing, but it's + // not a given that the Cond does. For instance, in AVX512 v1i1 is legal. + // See the similar logic in ScalarizeVecRes_VSETCC + if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { + Cond = GetScalarizedVector(Cond); + } else { + EVT VT = OpVT.getVectorElementType(); + Cond = DAG.getNode( + ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond, + DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))); + } + SDValue LHS = GetScalarizedVector(N->getOperand(1)); TargetLowering::BooleanContent ScalarBool = TLI.getBooleanContents(false, false); Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -7262,22 +7262,23 @@ void SelectionDAG::TransferDbgValues(SDValue From, SDV AddDbgValue(I, ToNode, false); } -void SelectionDAG::makeEquivalentMemoryOrdering(LoadSDNode *OldLoad, - SDValue NewMemOp) { +SDValue SelectionDAG::makeEquivalentMemoryOrdering(LoadSDNode *OldLoad, + SDValue NewMemOp) { assert(isa<MemSDNode>(NewMemOp.getNode()) && "Expected a memop node"); - if (!OldLoad->hasAnyUseOfValue(1)) - return; - // The new memory operation must have the same position as the old load in // terms of memory dependency. Create a TokenFactor for the old load and new // memory operation and update uses of the old load's output chain to use that // TokenFactor. SDValue OldChain = SDValue(OldLoad, 1); SDValue NewChain = SDValue(NewMemOp.getNode(), 1); + if (!OldLoad->hasAnyUseOfValue(1)) + return NewChain; + SDValue TokenFactor = getNode(ISD::TokenFactor, SDLoc(OldLoad), MVT::Other, OldChain, NewChain); ReplaceAllUsesOfValueWith(OldChain, TokenFactor); UpdateNodeOperands(TokenFactor.getNode(), OldChain, NewChain); + return TokenFactor; } //===----------------------------------------------------------------------===// Modified: vendor/llvm/dist/lib/CodeGen/VirtRegMap.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/VirtRegMap.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/CodeGen/VirtRegMap.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -180,6 +180,7 @@ class VirtRegRewriter : public MachineFunctionPass { void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const; void handleIdentityCopy(MachineInstr &MI) const; void expandCopyBundle(MachineInstr &MI) const; + bool subRegLiveThrough(const MachineInstr &MI, unsigned SuperPhysReg) const; public: static char ID; @@ -415,6 +416,32 @@ void VirtRegRewriter::expandCopyBundle(MachineInstr &M } } +/// Check whether (part of) \p SuperPhysReg is live through \p MI. +/// \pre \p MI defines a subregister of a virtual register that +/// has been assigned to \p SuperPhysReg. +bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI, + unsigned SuperPhysReg) const { + SlotIndex MIIndex = LIS->getInstructionIndex(MI); + SlotIndex BeforeMIUses = MIIndex.getBaseIndex(); + SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex(); + for (MCRegUnitIterator Unit(SuperPhysReg, TRI); Unit.isValid(); ++Unit) { + const LiveRange &UnitRange = LIS->getRegUnit(*Unit); + // If the regunit is live both before and after MI, + // we assume it is live through. + // Generally speaking, this is not true, because something like + // "RU = op RU" would match that description. + // However, we know that we are trying to assess whether + // a def of a virtual reg, vreg, is live at the same time of RU. + // If we are in the "RU = op RU" situation, that means that vreg + // is defined at the same time as RU (i.e., "vreg, RU = op RU"). + // Thus, vreg and RU interferes and vreg cannot be assigned to + // SuperPhysReg. Therefore, this situation cannot happen. + if (UnitRange.liveAt(AfterMIDefs) && UnitRange.liveAt(BeforeMIUses)) + return true; + } + return false; +} + void VirtRegRewriter::rewrite() { bool NoSubRegLiveness = !MRI->subRegLivenessEnabled(); SmallVector<unsigned, 8> SuperDeads; @@ -452,7 +479,8 @@ void VirtRegRewriter::rewrite() { // A virtual register kill refers to the whole register, so we may // have to add <imp-use,kill> operands for the super-register. A // partial redef always kills and redefines the super-register. - if (MO.readsReg() && (MO.isDef() || MO.isKill())) + if ((MO.readsReg() && (MO.isDef() || MO.isKill())) || + (MO.isDef() && subRegLiveThrough(*MI, PhysReg))) SuperKills.push_back(PhysReg); if (MO.isDef()) { Modified: vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFContext.cpp ============================================================================== --- vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFContext.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFContext.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -134,13 +134,13 @@ dumpDWARFv5StringOffsetsSection(raw_ostream &OS, Strin uint64_t StringOffset = StrOffsetExt.getRelocatedValue(EntrySize, &Offset); if (Format == DWARF32) { - OS << format("%8.8x ", StringOffset); uint32_t StringOffset32 = (uint32_t)StringOffset; + OS << format("%8.8x ", StringOffset32); const char *S = StrData.getCStr(&StringOffset32); if (S) OS << format("\"%s\"", S); } else - OS << format("%16.16x ", StringOffset); + OS << format("%16.16" PRIx64 " ", StringOffset); OS << "\n"; } } Modified: vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFVerifier.cpp ============================================================================== --- vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFVerifier.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFVerifier.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -196,7 +196,7 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const ++NumErrors; OS << "error: DW_AT_stmt_list offset is beyond .debug_line " "bounds: " - << format("0x%08" PRIx32, *SectionOffset) << "\n"; + << format("0x%08" PRIx64, *SectionOffset) << "\n"; Die.dump(OS, 0); OS << "\n"; } @@ -234,7 +234,7 @@ unsigned DWARFVerifier::verifyDebugInfoForm(const DWAR if (CUOffset >= CUSize) { ++NumErrors; OS << "error: " << FormEncodingString(Form) << " CU offset " - << format("0x%08" PRIx32, CUOffset) + << format("0x%08" PRIx64, CUOffset) << " is invalid (must be less than CU size of " << format("0x%08" PRIx32, CUSize) << "):\n"; Die.dump(OS, 0); @@ -366,7 +366,7 @@ void DWARFVerifier::verifyDebugLineRows() { if (Row.Address < PrevAddress) { ++NumDebugLineErrors; OS << "error: .debug_line[" - << format("0x%08" PRIx32, + << format("0x%08" PRIx64, *toSectionOffset(Die.find(DW_AT_stmt_list))) << "] row[" << RowIndex << "] decreases in address from previous row:\n"; @@ -381,7 +381,7 @@ void DWARFVerifier::verifyDebugLineRows() { if (Row.File > MaxFileIndex) { ++NumDebugLineErrors; OS << "error: .debug_line[" - << format("0x%08" PRIx32, + << format("0x%08" PRIx64, *toSectionOffset(Die.find(DW_AT_stmt_list))) << "][" << RowIndex << "] has invalid file index " << Row.File << " (valid values are [1," << MaxFileIndex << "]):\n"; Modified: vendor/llvm/dist/lib/Object/COFFImportFile.cpp ============================================================================== --- vendor/llvm/dist/lib/Object/COFFImportFile.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Object/COFFImportFile.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -557,7 +557,7 @@ NewArchiveMember ObjectFactory::createWeakExternal(Str std::error_code writeImportLibrary(StringRef ImportName, StringRef Path, ArrayRef<COFFShortExport> Exports, - MachineTypes Machine) { + MachineTypes Machine, bool MakeWeakAliases) { std::vector<NewArchiveMember> Members; ObjectFactory OF(llvm::sys::path::filename(ImportName), Machine); @@ -575,7 +575,7 @@ std::error_code writeImportLibrary(StringRef ImportNam if (E.Private) continue; - if (E.isWeak()) { + if (E.isWeak() && MakeWeakAliases) { Members.push_back(OF.createWeakExternal(E.Name, E.ExtName, false)); Members.push_back(OF.createWeakExternal(E.Name, E.ExtName, true)); continue; @@ -587,7 +587,7 @@ std::error_code writeImportLibrary(StringRef ImportNam if (E.Constant) ImportType = IMPORT_CONST; - StringRef SymbolName = E.isWeak() ? E.ExtName : E.Name; + StringRef SymbolName = E.SymbolName.empty() ? E.Name : E.SymbolName; ImportNameType NameType = getNameType(SymbolName, E.Name, Machine); Expected<std::string> Name = E.ExtName.empty() ? SymbolName Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -388,6 +388,10 @@ static unsigned isMatchingStore(MachineInstr &LoadInst } static unsigned getPreIndexedOpcode(unsigned Opc) { + // FIXME: We don't currently support creating pre-indexed loads/stores when + // the load or store is the unscaled version. If we decide to perform such an + // optimization in the future the cases for the unscaled loads/stores will + // need to be added here. switch (Opc) { default: llvm_unreachable("Opcode has no pre-indexed equivalent!"); @@ -451,32 +455,42 @@ static unsigned getPostIndexedOpcode(unsigned Opc) { default: llvm_unreachable("Opcode has no post-indexed wise equivalent!"); case AArch64::STRSui: + case AArch64::STURSi: return AArch64::STRSpost; case AArch64::STRDui: + case AArch64::STURDi: return AArch64::STRDpost; case AArch64::STRQui: + case AArch64::STURQi: return AArch64::STRQpost; case AArch64::STRBBui: return AArch64::STRBBpost; case AArch64::STRHHui: return AArch64::STRHHpost; case AArch64::STRWui: + case AArch64::STURWi: return AArch64::STRWpost; case AArch64::STRXui: + case AArch64::STURXi: return AArch64::STRXpost; case AArch64::LDRSui: + case AArch64::LDURSi: return AArch64::LDRSpost; case AArch64::LDRDui: + case AArch64::LDURDi: return AArch64::LDRDpost; case AArch64::LDRQui: + case AArch64::LDURQi: return AArch64::LDRQpost; case AArch64::LDRBBui: return AArch64::LDRBBpost; case AArch64::LDRHHui: return AArch64::LDRHHpost; case AArch64::LDRWui: + case AArch64::LDURWi: return AArch64::LDRWpost; case AArch64::LDRXui: + case AArch64::LDURXi: return AArch64::LDRXpost; case AArch64::LDRSWui: return AArch64::LDRSWpost; @@ -1694,8 +1708,9 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBl ++NumPostFolded; break; } - // Don't know how to handle pre/post-index versions, so move to the next - // instruction. + + // Don't know how to handle unscaled pre/post-index versions below, so + // move to the next instruction. if (TII->isUnscaledLdSt(Opc)) { ++MBBI; break; Modified: vendor/llvm/dist/lib/Target/ARM/ARMExpandPseudoInsts.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/ARM/ARMExpandPseudoInsts.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Target/ARM/ARMExpandPseudoInsts.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -769,8 +769,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock MachineInstr &MI = *MBBI; DebugLoc DL = MI.getDebugLoc(); const MachineOperand &Dest = MI.getOperand(0); - unsigned StatusReg = MI.getOperand(1).getReg(); - bool StatusDead = MI.getOperand(1).isDead(); + unsigned TempReg = MI.getOperand(1).getReg(); // Duplicating undef operands into 2 instructions does not guarantee the same // value on both; However undef should be replaced by xzr anyway. assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); @@ -797,23 +796,9 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock } // .Lloadcmp: - // mov wStatus, #0 // ldrex rDest, [rAddr] // cmp rDest, rDesired // bne .Ldone - if (!StatusDead) { - if (IsThumb) { - BuildMI(LoadCmpBB, DL, TII->get(ARM::tMOVi8), StatusReg) - .addDef(ARM::CPSR, RegState::Dead) - .addImm(0) - .add(predOps(ARMCC::AL)); - } else { - BuildMI(LoadCmpBB, DL, TII->get(ARM::MOVi), StatusReg) - .addImm(0) - .add(predOps(ARMCC::AL)) - .add(condCodeOp()); - } - } MachineInstrBuilder MIB; MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); @@ -836,10 +821,10 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock LoadCmpBB->addSuccessor(StoreBB); // .Lstore: - // strex rStatus, rNew, [rAddr] - // cmp rStatus, #0 + // strex rTempReg, rNew, [rAddr] + // cmp rTempReg, #0 // bne .Lloadcmp - MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), StatusReg) + MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) .addReg(NewReg) .addReg(AddrReg); if (StrexOp == ARM::t2STREX) @@ -848,7 +833,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; BuildMI(StoreBB, DL, TII->get(CMPri)) - .addReg(StatusReg, getKillRegState(StatusDead)) + .addReg(TempReg, RegState::Kill) .addImm(0) .add(predOps(ARMCC::AL)); BuildMI(StoreBB, DL, TII->get(Bcc)) @@ -904,8 +889,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBl MachineInstr &MI = *MBBI; DebugLoc DL = MI.getDebugLoc(); MachineOperand &Dest = MI.getOperand(0); - unsigned StatusReg = MI.getOperand(1).getReg(); - bool StatusDead = MI.getOperand(1).isDead(); + unsigned TempReg = MI.getOperand(1).getReg(); // Duplicating undef operands into 2 instructions does not guarantee the same // value on both; However undef should be replaced by xzr anyway. assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); @@ -931,7 +915,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBl // .Lloadcmp: // ldrexd rDestLo, rDestHi, [rAddr] // cmp rDestLo, rDesiredLo - // sbcs rStatus<dead>, rDestHi, rDesiredHi + // sbcs rTempReg<dead>, rDestHi, rDesiredHi // bne .Ldone unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; MachineInstrBuilder MIB; @@ -959,17 +943,17 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBl LoadCmpBB->addSuccessor(StoreBB); // .Lstore: - // strexd rStatus, rNewLo, rNewHi, [rAddr] - // cmp rStatus, #0 + // strexd rTempReg, rNewLo, rNewHi, [rAddr] + // cmp rTempReg, #0 // bne .Lloadcmp unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; - MIB = BuildMI(StoreBB, DL, TII->get(STREXD), StatusReg); + MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); addExclusiveRegPair(MIB, New, 0, IsThumb, TRI); MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; BuildMI(StoreBB, DL, TII->get(CMPri)) - .addReg(StatusReg, getKillRegState(StatusDead)) + .addReg(TempReg, RegState::Kill) .addImm(0) .add(predOps(ARMCC::AL)); BuildMI(StoreBB, DL, TII->get(Bcc)) Modified: vendor/llvm/dist/lib/Target/ARM/ARMInstrInfo.td ============================================================================== --- vendor/llvm/dist/lib/Target/ARM/ARMInstrInfo.td Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Target/ARM/ARMInstrInfo.td Sun Aug 20 21:02:43 2017 (r322727) @@ -6053,21 +6053,21 @@ def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$si // significantly more naive than the standard expansion: we conservatively // assume seq_cst, strong cmpxchg and omit clrex on failure. -let Constraints = "@earlyclobber $Rd,@earlyclobber $status", +let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", mayLoad = 1, mayStore = 1 in { -def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$status), +def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), (ins GPR:$addr, GPR:$desired, GPR:$new), NoItinerary, []>, Sched<[]>; -def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$status), +def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), (ins GPR:$addr, GPR:$desired, GPR:$new), NoItinerary, []>, Sched<[]>; -def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$status), +def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), (ins GPR:$addr, GPR:$desired, GPR:$new), NoItinerary, []>, Sched<[]>; -def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$status), +def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), NoItinerary, []>, Sched<[]>; } Modified: vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -419,6 +419,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMa setOperationAction(ISD::SELECT, VT, Custom); setOperationAction(ISD::SETCC, VT, Custom); } + + // Custom action for SELECT MMX and expand action for SELECT_CC MMX + setOperationAction(ISD::SELECT, MVT::x86mmx, Custom); + setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand); + setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support // SjLj exception handling but a light-weight setjmp/longjmp replacement to @@ -1383,7 +1388,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMa // (result) is 256-bit but the source is 512-bit wide. // 128-bit was made Custom under AVX1. for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, - MVT::v8f32, MVT::v4f64 }) + MVT::v8f32, MVT::v4f64, MVT::v1i1 }) setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1, MVT::v32i1, MVT::v64i1 }) @@ -14570,6 +14575,21 @@ static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, cons unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); MVT ResVT = Op.getSimpleValueType(); + // When v1i1 is legal a scalarization of a vselect with a vXi1 Cond + // would result with: v1i1 = extract_subvector(vXi1, idx). + // Lower these into extract_vector_elt which is already selectable. + if (ResVT == MVT::v1i1) { + assert(Subtarget.hasAVX512() && + "Boolean EXTRACT_SUBVECTOR requires AVX512"); + + MVT EltVT = ResVT.getVectorElementType(); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + MVT LegalVT = + (TLI.getTypeToTransformTo(*DAG.getContext(), EltVT)).getSimpleVT(); + SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LegalVT, In, Idx); + return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ResVT, Res); + } + assert((In.getSimpleValueType().is256BitVector() || In.getSimpleValueType().is512BitVector()) && "Can only extract from 256-bit or 512-bit vectors"); @@ -20651,8 +20671,8 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, cons } // ADC/ADCX/SBB case ADX: { - SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other); - SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other); + SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::i32); + SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::i32); SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2), DAG.getConstant(-1, dl, MVT::i8)); SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3), @@ -30663,6 +30683,14 @@ static SDValue combineSelect(SDNode *N, SelectionDAG & return SDValue(N, 0); } + // Custom action for SELECT MMX + if (VT == MVT::x86mmx) { + LHS = DAG.getBitcast(MVT::i64, LHS); + RHS = DAG.getBitcast(MVT::i64, RHS); + SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::i64, Cond, LHS, RHS); + return DAG.getBitcast(VT, newSelect); + } + return SDValue(); } @@ -33358,7 +33386,8 @@ static SDValue combineStore(SDNode *N, SelectionDAG &D SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), Ld->getAlignment(), Ld->getMemOperand()->getFlags()); - SDValue NewChain = NewLd.getValue(1); + // Make sure new load is placed in same chain order. + SDValue NewChain = DAG.makeEquivalentMemoryOrdering(Ld, NewLd); if (TokenFactorIndex >= 0) { Ops.push_back(NewChain); NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops); @@ -33379,11 +33408,12 @@ static SDValue combineStore(SDNode *N, SelectionDAG &D Ld->getPointerInfo().getWithOffset(4), MinAlign(Ld->getAlignment(), 4), Ld->getMemOperand()->getFlags()); + // Make sure new loads are placed in same chain order. + SDValue NewChain = DAG.makeEquivalentMemoryOrdering(Ld, LoLd); + NewChain = DAG.makeEquivalentMemoryOrdering(Ld, HiLd); - SDValue NewChain = LoLd.getValue(1); if (TokenFactorIndex >= 0) { - Ops.push_back(LoLd); - Ops.push_back(HiLd); + Ops.push_back(NewChain); NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops); } Modified: vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td Sun Aug 20 21:02:43 2017 (r322727) @@ -978,6 +978,44 @@ multiclass avx512_int_broadcast_reg<bits<8> opc, X86Ve (_.VT (OpNode SrcRC:$src))>, T8PD, EVEX; } +multiclass avx512_int_broadcastbw_reg<bits<8> opc, string Name, + X86VectorVTInfo _, SDPatternOperator OpNode, + RegisterClass SrcRC, SubRegIndex Subreg> { + let ExeDomain = _.ExeDomain in + defm r : AVX512_maskable_custom<opc, MRMSrcReg, + (outs _.RC:$dst), (ins GR32:$src), + !con((ins _.RC:$src0, _.KRCWM:$mask), (ins GR32:$src)), + !con((ins _.KRCWM:$mask), (ins GR32:$src)), + "vpbroadcast"##_.Suffix, "$src", "$src", [], [], [], + "$src0 = $dst">, T8PD, EVEX; + + def : Pat <(_.VT (OpNode SrcRC:$src)), + (!cast<Instruction>(Name#r) + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>; + + def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.RC:$src0), + (!cast<Instruction>(Name#rk) _.RC:$src0, _.KRCWM:$mask, + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>; + + def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.ImmAllZerosV), + (!cast<Instruction>(Name#rkz) _.KRCWM:$mask, + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>; +} + +multiclass avx512_int_broadcastbw_reg_vl<bits<8> opc, string Name, + AVX512VLVectorVTInfo _, SDPatternOperator OpNode, + RegisterClass SrcRC, SubRegIndex Subreg, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_int_broadcastbw_reg<opc, Name#Z, _.info512, OpNode, SrcRC, + Subreg>, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_int_broadcastbw_reg<opc, Name#Z256, _.info256, OpNode, + SrcRC, Subreg>, EVEX_V256; + defm Z128 : avx512_int_broadcastbw_reg<opc, Name#Z128, _.info128, OpNode, + SrcRC, Subreg>, EVEX_V128; + } +} + multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _, SDPatternOperator OpNode, RegisterClass SrcRC, Predicate prd> { @@ -989,18 +1027,11 @@ multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AV } } -let isCodeGenOnly = 1 in { -defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, - X86VBroadcast, GR8, HasBWI>; -defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, - X86VBroadcast, GR16, HasBWI>; -} -let isAsmParserOnly = 1 in { - defm VPBROADCASTBr_Alt : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, - null_frag, GR32, HasBWI>; - defm VPBROADCASTWr_Alt : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, - null_frag, GR32, HasBWI>; -} +defm VPBROADCASTBr : avx512_int_broadcastbw_reg_vl<0x7A, "VPBROADCASTBr", + avx512vl_i8_info, X86VBroadcast, GR8, sub_8bit, HasBWI>; +defm VPBROADCASTWr : avx512_int_broadcastbw_reg_vl<0x7B, "VPBROADCASTWr", + avx512vl_i16_info, X86VBroadcast, GR16, sub_16bit, + HasBWI>; defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, X86VBroadcast, GR32, HasAVX512>; defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, Modified: vendor/llvm/dist/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp ============================================================================== --- vendor/llvm/dist/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -60,11 +60,13 @@ std::vector<std::unique_ptr<MemoryBuffer>> OwningMBs; // Opens a file. Path has to be resolved already. // Newly created memory buffers are owned by this driver. -MemoryBufferRef openFile(StringRef Path) { +Optional<MemoryBufferRef> openFile(StringRef Path) { ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> MB = MemoryBuffer::getFile(Path); - if (std::error_code EC = MB.getError()) + if (std::error_code EC = MB.getError()) { llvm::errs() << "fail openFile: " << EC.message() << "\n"; + return None; + } MemoryBufferRef MBRef = MB.get()->getMemBufferRef(); OwningMBs.push_back(std::move(MB.get())); // take ownership @@ -114,11 +116,16 @@ int llvm::dlltoolDriverMain(llvm::ArrayRef<const char for (auto *Arg : Args.filtered(OPT_UNKNOWN)) llvm::errs() << "ignoring unknown argument: " << Arg->getSpelling() << "\n"; - MemoryBufferRef MB; - if (auto *Arg = Args.getLastArg(OPT_d)) - MB = openFile(Arg->getValue()); + if (!Args.hasArg(OPT_d)) { + llvm::errs() << "no definition file specified\n"; + return 1; + } - if (!MB.getBufferSize()) { + Optional<MemoryBufferRef> MB = openFile(Args.getLastArg(OPT_d)->getValue()); + if (!MB) + return 1; + + if (!MB->getBufferSize()) { llvm::errs() << "definition file empty\n"; return 1; } @@ -133,7 +140,7 @@ int llvm::dlltoolDriverMain(llvm::ArrayRef<const char } Expected<COFFModuleDefinition> Def = - parseCOFFModuleDefinition(MB, Machine, true); + parseCOFFModuleDefinition(*MB, Machine, true); if (!Def) { llvm::errs() << "error parsing definition\n" @@ -154,7 +161,7 @@ int llvm::dlltoolDriverMain(llvm::ArrayRef<const char if (Path.empty()) Path = getImplibPath(Def->OutputFile); - if (writeImportLibrary(Def->OutputFile, Path, Def->Exports, Machine)) + if (writeImportLibrary(Def->OutputFile, Path, Def->Exports, Machine, true)) return 1; return 0; } Modified: vendor/llvm/dist/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -1470,6 +1470,7 @@ void DFSanVisitor::visitCallSite(CallSite CS) { } i = CS.arg_begin(); + const unsigned ShadowArgStart = Args.size(); for (unsigned n = FT->getNumParams(); n != 0; ++i, --n) Args.push_back(DFSF.getShadow(*i)); @@ -1504,6 +1505,15 @@ void DFSanVisitor::visitCallSite(CallSite CS) { CallInst *CustomCI = IRB.CreateCall(CustomF, Args); CustomCI->setCallingConv(CI->getCallingConv()); CustomCI->setAttributes(CI->getAttributes()); + + // Update the parameter attributes of the custom call instruction to + // zero extend the shadow parameters. This is required for targets + // which consider ShadowTy an illegal type. + for (unsigned n = 0; n < FT->getNumParams(); n++) { + const unsigned ArgNo = ShadowArgStart + n; + if (CustomCI->getArgOperand(ArgNo)->getType() == DFSF.DFS.ShadowTy) + CustomCI->addParamAttr(ArgNo, Attribute::ZExt); + } if (!FT->getReturnType()->isVoidTy()) { LoadInst *LabelLoad = IRB.CreateLoad(DFSF.LabelReturnAlloca); Modified: vendor/llvm/dist/lib/Transforms/Scalar/BDCE.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/Scalar/BDCE.cpp Sun Aug 20 20:38:15 2017 (r322726) +++ vendor/llvm/dist/lib/Transforms/Scalar/BDCE.cpp Sun Aug 20 21:02:43 2017 (r322727) @@ -15,6 +15,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Transforms/Scalar/BDCE.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/DemandedBits.h" @@ -35,6 +36,46 @@ using namespace llvm; STATISTIC(NumRemoved, "Number of instructions removed (unused)"); STATISTIC(NumSimplified, "Number of instructions trivialized (dead bits)"); +/// If an instruction is trivialized (dead), then the chain of users of that +/// instruction may need to be cleared of assumptions that can no longer be +/// guaranteed correct. +static void clearAssumptionsOfUsers(Instruction *I, DemandedBits &DB) { + assert(I->getType()->isIntegerTy() && "Trivializing a non-integer value?"); + + // Initialize the worklist with eligible direct users. + SmallVector<Instruction *, 16> WorkList; + for (User *JU : I->users()) { + // If all bits of a user are demanded, then we know that nothing below that + // in the def-use chain needs to be changed. + auto *J = dyn_cast<Instruction>(JU); + if (J && !DB.getDemandedBits(J).isAllOnesValue()) + WorkList.push_back(J); + } + + // DFS through subsequent users while tracking visits to avoid cycles. + SmallPtrSet<Instruction *, 16> Visited; + while (!WorkList.empty()) { + Instruction *J = WorkList.pop_back_val(); + + // NSW, NUW, and exact are based on operands that might have changed. + J->dropPoisonGeneratingFlags(); + + // We do not have to worry about llvm.assume or range metadata: + // 1. llvm.assume demands its operand, so trivializing can't change it. + // 2. range metadata only applies to memory accesses which demand all bits. + + Visited.insert(J); + + for (User *KU : J->users()) { + // If all bits of a user are demanded, then we know that nothing below + // that in the def-use chain needs to be changed. + auto *K = dyn_cast<Instruction>(KU); + if (K && !Visited.count(K) && !DB.getDemandedBits(K).isAllOnesValue()) + WorkList.push_back(K); + } + } +} + static bool bitTrackingDCE(Function &F, DemandedBits &DB) { SmallVector<Instruction*, 128> Worklist; bool Changed = false; @@ -51,6 +92,9 @@ static bool bitTrackingDCE(Function &F, DemandedBits & // replacing all uses with something else. Then, if they don't need to // remain live (because they have side effects, etc.) we can remove them. DEBUG(dbgs() << "BDCE: Trivializing: " << I << " (all bits dead)\n"); + + clearAssumptionsOfUsers(&I, DB); + // FIXME: In theory we could substitute undef here instead of zero. // This should be reconsidered once we settle on the semantics of // undef, poison, etc. Added: vendor/llvm/dist/test/Analysis/ScalarEvolution/max-addrec-size.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/Analysis/ScalarEvolution/max-addrec-size.ll Sun Aug 20 21:02:43 2017 (r322727) @@ -0,0 +1,33 @@ +; RUN: opt -analyze -scalar-evolution -scalar-evolution-max-add-rec-size=3 < %s | FileCheck %s + +; Show that we are able to avoid creation of huge SCEVs by capping the max +; AddRec size. +define i32 @test_01(i32 %a, i32 %b) { + +; CHECK-LABEL: Classifying expressions for: @test_01 +; CHECK-NEXT: %iv = phi i32 [ %a, %entry ], [ %iv.next, %loop ] +; CHECK-NEXT: --> {%a,+,%b}<%loop> U: full-set S: full-set +; CHECK-NEXT: %iv.next = add i32 %iv, %b +; CHECK-NEXT: --> {(%a + %b),+,%b}<%loop> U: full-set S: full-set +; CHECK-NEXT: %x1 = mul i32 %iv, %iv.next +; CHECK-NEXT: --> {((%a + %b) * %a),+,(((2 * %a) + (2 * %b)) * %b),+,(2 * %b * %b)}<%loop> U: full-set S: full-set +; CHECK-NEXT: %x2 = mul i32 %x1, %x1 +; CHECK-NEXT: --> ({((%a + %b) * %a),+,(((2 * %a) + (2 * %b)) * %b),+,(2 * %b * %b)}<%loop> * {((%a + %b) * %a),+,(((2 * %a) + (2 * %b)) * %b),+,(2 * %b * %b)}<%loop>) U: full-set S: full-set +; CHECK-NEXT: %x3 = mul i32 %x2, %x1 +; CHECK-NEXT: --> ({((%a + %b) * %a),+,(((2 * %a) + (2 * %b)) * %b),+,(2 * %b * %b)}<%loop> * {((%a + %b) * %a),+,(((2 * %a) + (2 * %b)) * %b),+,(2 * %b * %b)}<%loop> * {((%a + %b) * %a),+,(((2 * %a) + (2 * %b)) * %b),+,(2 * %b * %b)}<%loop>) U: full-set S: full-set + +entry: + br label %loop + +loop: + %iv = phi i32 [ %a, %entry ], [ %iv.next, %loop ] + %iv.next = add i32 %iv, %b + %cond = icmp slt i32 %iv.next, 1000 + br i1 %cond, label %loop, label %exit + +exit: + %x1 = mul i32 %iv, %iv.next + %x2 = mul i32 %x1, %x1 + %x3 = mul i32 %x2, %x1 + ret i32 %x3 +} Added: vendor/llvm/dist/test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir Sun Aug 20 21:02:43 2017 (r322727) @@ -0,0 +1,115 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s +--- +# CHECK-LABEL: name: test_LDURSi_post +# CHECK: LDRSpost %x0, -4 +name: test_LDURSi_post +body: | + bb.0.entry: + liveins: %x0 + + %s0 = LDURSi %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_LDURDi_post +# CHECK: LDRDpost %x0, -4 +name: test_LDURDi_post +body: | + bb.0.entry: + liveins: %x0 + + %d0 = LDURDi %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_LDURQi_post +# CHECK: LDRQpost %x0, -4 +name: test_LDURQi_post +body: | + bb.0.entry: + liveins: %x0 + + %q0 = LDURQi %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_LDURWi_post +# CHECK: LDRWpost %x0, -4 +name: test_LDURWi_post +body: | + bb.0.entry: + liveins: %x0 + *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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