Date: Thu, 27 Dec 2018 12:57:52 +0000 From: Ruslan Bukin <ruslan.bukin@cl.cam.ac.uk> To: nilakshan kunananthaseelan <nilakjhc@gmail.com> Cc: freebsd-riscv@freebsd.org Subject: Re: FreeBSD for RISC-V 32 Message-ID: <20181227125752.GA18710@bsdpad.com> In-Reply-To: <CA%2Bpg%2B_J5=hyn2VrWeJbYx-zHs3V%2BU3cD%2B7CrWyDygJQMr4SsnA@mail.gmail.com> References: <CA%2Bpg%2B_J5=hyn2VrWeJbYx-zHs3V%2BU3cD%2B7CrWyDygJQMr4SsnA@mail.gmail.com>
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Hi Nilakshan, FreeBSD/RISC-V most likely will support rv32 in future, although work has not started yet. It will require some effort to port it. For example all the Syntacore SCR cpu range is 32-bit. Regarding control status registers (CSRs), I'm not sure what do you mean? Ruslan On Sat, Dec 22, 2018 at 10:46:49PM +0530, nilakshan kunananthaseelan wrote: > Hi all, > We are developing a 32 bit processor based on RISC-V.So far we have > developed M and A extension and we have developed TLB for data and > instruction.In the CSR we have included the machine and supervisor > mode(tested with RISCV benchmark hex file).I have some issues regarding > porting a kernel for RISCV? > 1.If CSR testing is OK with RISCV benchmark hex file may I plug this into > the core system.If not is there any particular method to identify the flow > of CSR? > 2.Will freeBSD supports 32 bit machine?If so,what additional things I have > to do to port freeBSD for my processor? > What are the changes to be done for the steps given her > https://wiki.freebsd.org/riscv? > thanks in advance > -Nilakshan > _______________________________________________ > freebsd-riscv@freebsd.org mailing list > https://lists.freebsd.org/mailman/listinfo/freebsd-riscv > To unsubscribe, send any mail to "freebsd-riscv-unsubscribe@freebsd.org"
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