From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:07:59 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 372B2EC9703; Thu, 1 Feb 2018 21:07:59 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D67418632C; Thu, 1 Feb 2018 21:07:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id D12EC124E8; Thu, 1 Feb 2018 21:07:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11L7wQH073450; Thu, 1 Feb 2018 21:07:58 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11L7tio073418; Thu, 1 Feb 2018 21:07:55 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012107.w11L7tio073418@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:07:55 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328734 - in vendor/llvm/dist-release_60: docs include/llvm/Analysis include/llvm/MC lib/Analysis lib/CodeGen lib/CodeGen/GlobalISel lib/CodeGen/SelectionDAG lib/MC lib/Target/AArch64 l... X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/llvm/dist-release_60: docs include/llvm/Analysis include/llvm/MC lib/Analysis lib/CodeGen lib/CodeGen/GlobalISel lib/CodeGen/SelectionDAG lib/MC lib/Target/AArch64 lib/Target/AMDGPU lib/Targ... X-SVN-Commit-Revision: 328734 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:07:59 -0000 Author: dim Date: Thu Feb 1 21:07:55 2018 New Revision: 328734 URL: https://svnweb.freebsd.org/changeset/base/328734 Log: Vendor import of llvm release_60 branch r323948: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323948 Added: vendor/llvm/dist-release_60/test/Analysis/ValueTracking/select-pattern.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir vendor/llvm/dist-release_60/test/CodeGen/X86/pr34592.ll vendor/llvm/dist-release_60/test/MC/X86/eval-fill.s (contents, props changed) vendor/llvm/dist-release_60/test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll vendor/llvm/dist-release_60/test/ThinLTO/X86/dicompositetype-unique-alias.ll vendor/llvm/dist-release_60/test/Transforms/StructurizeCFG/bug36015.ll Modified: vendor/llvm/dist-release_60/docs/ReleaseNotes.rst vendor/llvm/dist-release_60/include/llvm/Analysis/ValueTracking.h vendor/llvm/dist-release_60/include/llvm/MC/MCFragment.h vendor/llvm/dist-release_60/include/llvm/MC/MCObjectStreamer.h vendor/llvm/dist-release_60/include/llvm/MC/MCStreamer.h vendor/llvm/dist-release_60/lib/Analysis/ValueTracking.cpp vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/IRTranslator.cpp vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/LegalizerHelper.cpp vendor/llvm/dist-release_60/lib/CodeGen/RegAllocFast.cpp vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp vendor/llvm/dist-release_60/lib/MC/MCAsmStreamer.cpp vendor/llvm/dist-release_60/lib/MC/MCAssembler.cpp vendor/llvm/dist-release_60/lib/MC/MCMachOStreamer.cpp vendor/llvm/dist-release_60/lib/MC/MCObjectStreamer.cpp vendor/llvm/dist-release_60/lib/MC/MCStreamer.cpp vendor/llvm/dist-release_60/lib/MC/MCWinCOFFStreamer.cpp vendor/llvm/dist-release_60/lib/MC/WasmObjectWriter.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FastISel.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64Subtarget.cpp vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInsertSkips.cpp vendor/llvm/dist-release_60/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/StructurizeCFG.cpp vendor/llvm/dist-release_60/lib/Transforms/Utils/ValueMapper.cpp vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir vendor/llvm/dist-release_60/test/CodeGen/AArch64/dllimport.ll vendor/llvm/dist-release_60/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll vendor/llvm/dist-release_60/test/CodeGen/AMDGPU/multilevel-break.ll vendor/llvm/dist-release_60/test/CodeGen/AMDGPU/nested-loop-conditions.ll vendor/llvm/dist-release_60/test/MC/X86/x86-32-coverage.s vendor/llvm/dist-release_60/test/Transforms/CallSiteSplitting/callsite-no-splitting.ll vendor/llvm/dist-release_60/test/Transforms/InstCombine/minmax-fold.ll vendor/llvm/dist-release_60/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll vendor/llvm/dist-release_60/test/Transforms/StructurizeCFG/nested-loop-order.ll Modified: vendor/llvm/dist-release_60/docs/ReleaseNotes.rst ============================================================================== --- vendor/llvm/dist-release_60/docs/ReleaseNotes.rst Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/docs/ReleaseNotes.rst Thu Feb 1 21:07:55 2018 (r328734) @@ -15,7 +15,7 @@ Introduction ============ This document contains the release notes for the LLVM Compiler Infrastructure, -release 5.0.0. Here we describe the status of LLVM, including major improvements +release 6.0.0. Here we describe the status of LLVM, including major improvements from the previous release, improvements in various subprojects of LLVM, and some of the current users of the code. All LLVM releases may be downloaded from the `LLVM releases web site `_. Modified: vendor/llvm/dist-release_60/include/llvm/Analysis/ValueTracking.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/Analysis/ValueTracking.h Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/include/llvm/Analysis/ValueTracking.h Thu Feb 1 21:07:55 2018 (r328734) @@ -508,7 +508,8 @@ class Value; /// -> LHS = %a, RHS = i32 4, *CastOp = Instruction::SExt /// SelectPatternResult matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, - Instruction::CastOps *CastOp = nullptr); + Instruction::CastOps *CastOp = nullptr, + unsigned Depth = 0); inline SelectPatternResult matchSelectPattern(const Value *V, const Value *&LHS, const Value *&RHS, Instruction::CastOps *CastOp = nullptr) { Modified: vendor/llvm/dist-release_60/include/llvm/MC/MCFragment.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/MC/MCFragment.h Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/include/llvm/MC/MCFragment.h Thu Feb 1 21:07:55 2018 (r328734) @@ -422,14 +422,21 @@ class MCFillFragment : public MCFragment { uint8_t Value; /// The number of bytes to insert. - uint64_t Size; + const MCExpr &Size; + /// Source location of the directive that this fragment was created for. + SMLoc Loc; + public: - MCFillFragment(uint8_t Value, uint64_t Size, MCSection *Sec = nullptr) - : MCFragment(FT_Fill, false, 0, Sec), Value(Value), Size(Size) {} + MCFillFragment(uint8_t Value, const MCExpr &Size, SMLoc Loc, + MCSection *Sec = nullptr) + : MCFragment(FT_Fill, false, 0, Sec), Value(Value), Size(Size), Loc(Loc) { + } uint8_t getValue() const { return Value; } - uint64_t getSize() const { return Size; } + const MCExpr &getSize() const { return Size; } + + SMLoc getLoc() const { return Loc; } static bool classof(const MCFragment *F) { return F->getKind() == MCFragment::FT_Fill; Modified: vendor/llvm/dist-release_60/include/llvm/MC/MCObjectStreamer.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/MC/MCObjectStreamer.h Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/include/llvm/MC/MCObjectStreamer.h Thu Feb 1 21:07:55 2018 (r328734) @@ -161,7 +161,6 @@ class MCObjectStreamer : public MCStreamer { (public) bool EmitRelocDirective(const MCExpr &Offset, StringRef Name, const MCExpr *Expr, SMLoc Loc) override; using MCStreamer::emitFill; - void emitFill(uint64_t NumBytes, uint8_t FillValue) override; void emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc = SMLoc()) override; void emitFill(const MCExpr &NumValues, int64_t Size, int64_t Expr, Modified: vendor/llvm/dist-release_60/include/llvm/MC/MCStreamer.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/MC/MCStreamer.h Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/include/llvm/MC/MCStreamer.h Thu Feb 1 21:07:55 2018 (r328734) @@ -662,7 +662,7 @@ class MCStreamer { (public) /// \brief Emit NumBytes bytes worth of the value specified by FillValue. /// This implements directives such as '.space'. - virtual void emitFill(uint64_t NumBytes, uint8_t FillValue); + void emitFill(uint64_t NumBytes, uint8_t FillValue); /// \brief Emit \p Size bytes worth of the value specified by \p FillValue. /// Modified: vendor/llvm/dist-release_60/lib/Analysis/ValueTracking.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Analysis/ValueTracking.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Analysis/ValueTracking.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -4165,17 +4165,18 @@ static SelectPatternResult matchClamp(CmpInst::Predica /// a < c ? min(a,b) : min(b,c) ==> min(min(a,b),min(b,c)) static SelectPatternResult matchMinMaxOfMinMax(CmpInst::Predicate Pred, Value *CmpLHS, Value *CmpRHS, - Value *TrueVal, Value *FalseVal) { + Value *TVal, Value *FVal, + unsigned Depth) { // TODO: Allow FP min/max with nnan/nsz. assert(CmpInst::isIntPredicate(Pred) && "Expected integer comparison"); Value *A, *B; - SelectPatternResult L = matchSelectPattern(TrueVal, A, B); + SelectPatternResult L = matchSelectPattern(TVal, A, B, nullptr, Depth + 1); if (!SelectPatternResult::isMinOrMax(L.Flavor)) return {SPF_UNKNOWN, SPNB_NA, false}; Value *C, *D; - SelectPatternResult R = matchSelectPattern(FalseVal, C, D); + SelectPatternResult R = matchSelectPattern(FVal, C, D, nullptr, Depth + 1); if (L.Flavor != R.Flavor) return {SPF_UNKNOWN, SPNB_NA, false}; @@ -4214,7 +4215,7 @@ static SelectPatternResult matchMinMaxOfMinMax(CmpInst break; return {SPF_UNKNOWN, SPNB_NA, false}; default: - llvm_unreachable("Bad flavor while matching min/max"); + return {SPF_UNKNOWN, SPNB_NA, false}; } // a pred c ? m(a, b) : m(c, b) --> m(m(a, b), m(c, b)) @@ -4240,7 +4241,8 @@ static SelectPatternResult matchMinMaxOfMinMax(CmpInst static SelectPatternResult matchMinMax(CmpInst::Predicate Pred, Value *CmpLHS, Value *CmpRHS, Value *TrueVal, Value *FalseVal, - Value *&LHS, Value *&RHS) { + Value *&LHS, Value *&RHS, + unsigned Depth) { // Assume success. If there's no match, callers should not use these anyway. LHS = TrueVal; RHS = FalseVal; @@ -4249,7 +4251,7 @@ static SelectPatternResult matchMinMax(CmpInst::Predic if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) return SPR; - SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal); + SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, Depth); if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) return SPR; @@ -4313,7 +4315,8 @@ static SelectPatternResult matchSelectPattern(CmpInst: FastMathFlags FMF, Value *CmpLHS, Value *CmpRHS, Value *TrueVal, Value *FalseVal, - Value *&LHS, Value *&RHS) { + Value *&LHS, Value *&RHS, + unsigned Depth) { LHS = CmpLHS; RHS = CmpRHS; @@ -4429,7 +4432,7 @@ static SelectPatternResult matchSelectPattern(CmpInst: } if (CmpInst::isIntPredicate(Pred)) - return matchMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, LHS, RHS); + return matchMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, LHS, RHS, Depth); // According to (IEEE 754-2008 5.3.1), minNum(0.0, -0.0) and similar // may return either -0.0 or 0.0, so fcmp/select pair has stricter @@ -4550,7 +4553,11 @@ static Value *lookThroughCast(CmpInst *CmpI, Value *V1 } SelectPatternResult llvm::matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, - Instruction::CastOps *CastOp) { + Instruction::CastOps *CastOp, + unsigned Depth) { + if (Depth >= MaxDepth) + return {SPF_UNKNOWN, SPNB_NA, false}; + SelectInst *SI = dyn_cast(V); if (!SI) return {SPF_UNKNOWN, SPNB_NA, false}; @@ -4579,7 +4586,7 @@ SelectPatternResult llvm::matchSelectPattern(Value *V, FMF.setNoSignedZeros(); return ::matchSelectPattern(Pred, FMF, CmpLHS, CmpRHS, cast(TrueVal)->getOperand(0), C, - LHS, RHS); + LHS, RHS, Depth); } if (Value *C = lookThroughCast(CmpI, FalseVal, TrueVal, CastOp)) { // If this is a potential fmin/fmax with a cast to integer, then ignore @@ -4588,11 +4595,11 @@ SelectPatternResult llvm::matchSelectPattern(Value *V, FMF.setNoSignedZeros(); return ::matchSelectPattern(Pred, FMF, CmpLHS, CmpRHS, C, cast(FalseVal)->getOperand(0), - LHS, RHS); + LHS, RHS, Depth); } } return ::matchSelectPattern(Pred, FMF, CmpLHS, CmpRHS, TrueVal, FalseVal, - LHS, RHS); + LHS, RHS, Depth); } /// Return true if "icmp Pred LHS RHS" is always true. Modified: vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/IRTranslator.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -812,6 +812,10 @@ bool IRTranslator::translateCall(const User &U, Machin auto TII = MF->getTarget().getIntrinsicInfo(); const Function *F = CI.getCalledFunction(); + // FIXME: support Windows dllimport function calls. + if (F && F->hasDLLImportStorageClass()) + return false; + if (CI.isInlineAsm()) return translateInlineAsm(CI, MIRBuilder); Modified: vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/LegalizerHelper.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -661,7 +661,24 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigne } case TargetOpcode::G_FCONSTANT: { unsigned DstExt = MRI.createGenericVirtualRegister(WideTy); - MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm()); + const ConstantFP *CFP = MI.getOperand(1).getFPImm(); + APFloat Val = CFP->getValueAPF(); + LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); + auto LLT2Sem = [](LLT Ty) { + switch (Ty.getSizeInBits()) { + case 32: + return &APFloat::IEEEsingle(); + break; + case 64: + return &APFloat::IEEEdouble(); + break; + default: + llvm_unreachable("Unhandled fp widen type"); + } + }; + bool LosesInfo; + Val.convert(*LLT2Sem(WideTy), APFloat::rmTowardZero, &LosesInfo); + MIRBuilder.buildFConstant(DstExt, *ConstantFP::get(Ctx, Val)); MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt); MI.eraseFromParent(); return Legalized; Modified: vendor/llvm/dist-release_60/lib/CodeGen/RegAllocFast.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/RegAllocFast.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/RegAllocFast.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -193,9 +193,10 @@ namespace { void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); void usePhysReg(MachineOperand &MO); - void definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, RegState NewState); + void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg, + RegState NewState); unsigned calcSpillCost(MCPhysReg PhysReg) const; - void assignVirtToPhysReg(LiveReg&, MCPhysReg PhysReg); + void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg); LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); @@ -434,8 +435,8 @@ void RegAllocFast::usePhysReg(MachineOperand &MO) { /// Mark PhysReg as reserved or free after spilling any virtregs. This is very /// similar to defineVirtReg except the physreg is reserved instead of /// allocated. -void RegAllocFast::definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, - RegState NewState) { +void RegAllocFast::definePhysReg(MachineBasicBlock::iterator MI, + MCPhysReg PhysReg, RegState NewState) { markRegUsedInInstr(PhysReg); switch (unsigned VirtReg = PhysRegState[PhysReg]) { case regDisabled: @@ -857,7 +858,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBloc // Add live-in registers as live. for (const MachineBasicBlock::RegisterMaskPair LI : MBB.liveins()) if (MRI->isAllocatable(LI.PhysReg)) - definePhysReg(*MII, LI.PhysReg, regReserved); + definePhysReg(MII, LI.PhysReg, regReserved); VirtDead.clear(); Coalesced.clear(); Modified: vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -1380,8 +1380,10 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Func FastISelFailed = false; // Initialize the Fast-ISel state, if needed. FastISel *FastIS = nullptr; - if (TM.Options.EnableFastISel) + if (TM.Options.EnableFastISel) { + DEBUG(dbgs() << "Enabling fast-isel\n"); FastIS = TLI->createFastISel(*FuncInfo, LibInfo); + } setupSwiftErrorVals(Fn, TLI, FuncInfo); Modified: vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -717,6 +717,8 @@ bool TargetPassConfig::addCoreISelPasses() { if (EnableGlobalISel == cl::BOU_TRUE || (EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled() && EnableFastISelOption != cl::BOU_TRUE)) { + TM->setFastISel(false); + if (addIRTranslator()) return true; Modified: vendor/llvm/dist-release_60/lib/MC/MCAsmStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCAsmStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCAsmStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -192,9 +192,6 @@ class MCAsmStreamer final : public MCStreamer { (publi void EmitGPRel32Value(const MCExpr *Value) override; - - void emitFill(uint64_t NumBytes, uint8_t FillValue) override; - void emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc = SMLoc()) override; @@ -965,17 +962,12 @@ void MCAsmStreamer::EmitGPRel32Value(const MCExpr *Val EmitEOL(); } -/// emitFill - Emit NumBytes bytes worth of the value specified by -/// FillValue. This implements directives such as '.space'. -void MCAsmStreamer::emitFill(uint64_t NumBytes, uint8_t FillValue) { - if (NumBytes == 0) return; - - const MCExpr *E = MCConstantExpr::create(NumBytes, getContext()); - emitFill(*E, FillValue); -} - void MCAsmStreamer::emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc) { + int64_t IntNumBytes; + if (NumBytes.evaluateAsAbsolute(IntNumBytes) && IntNumBytes == 0) + return; + if (const char *ZeroDirective = MAI->getZeroDirective()) { // FIXME: Emit location directives OS << ZeroDirective; Modified: vendor/llvm/dist-release_60/lib/MC/MCAssembler.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCAssembler.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCAssembler.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -281,8 +281,18 @@ uint64_t MCAssembler::computeFragmentSize(const MCAsmL return cast(F).getContents().size(); case MCFragment::FT_CompactEncodedInst: return cast(F).getContents().size(); - case MCFragment::FT_Fill: - return cast(F).getSize(); + case MCFragment::FT_Fill: { + auto &FF = cast(F); + int64_t Size = 0; + if (!FF.getSize().evaluateAsAbsolute(Size, Layout)) + getContext().reportError(FF.getLoc(), + "expected assembly-time absolute expression"); + if (Size < 0) { + getContext().reportError(FF.getLoc(), "invalid number of bytes"); + return 0; + } + return Size; + } case MCFragment::FT_LEB: return cast(F).getContents().size(); @@ -540,7 +550,7 @@ static void writeFragment(const MCAssembler &Asm, cons for (unsigned I = 1; I < MaxChunkSize; ++I) Data[I] = Data[0]; - uint64_t Size = FF.getSize(); + uint64_t Size = FragmentSize; for (unsigned ChunkSize = MaxChunkSize; ChunkSize; ChunkSize /= 2) { StringRef Ref(Data, ChunkSize); for (uint64_t I = 0, E = Size / ChunkSize; I != E; ++I) Modified: vendor/llvm/dist-release_60/lib/MC/MCMachOStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCMachOStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCMachOStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -411,29 +411,19 @@ void MCMachOStreamer::EmitLocalCommonSymbol(MCSymbol * void MCMachOStreamer::EmitZerofill(MCSection *Section, MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment) { - getAssembler().registerSection(*Section); - - // The symbol may not be present, which only creates the section. - if (!Symbol) - return; - // On darwin all virtual sections have zerofill type. assert(Section->isVirtualSection() && "Section does not have zerofill type!"); - assert(Symbol->isUndefined() && "Cannot define a symbol twice!"); + PushSection(); + SwitchSection(Section); - getAssembler().registerSymbol(*Symbol); - - // Emit an align fragment if necessary. - if (ByteAlignment != 1) - new MCAlignFragment(ByteAlignment, 0, 0, ByteAlignment, Section); - - MCFragment *F = new MCFillFragment(0, Size, Section); - Symbol->setFragment(F); - - // Update the maximum alignment on the zero fill section if necessary. - if (ByteAlignment > Section->getAlignment()) - Section->setAlignment(ByteAlignment); + // The symbol may not be present, which only creates the section. + if (Symbol) { + EmitValueToAlignment(ByteAlignment, 0, 1, 0); + EmitLabel(Symbol); + EmitZeros(Size); + } + PopSection(); } // This should always be called with the thread local bss section. Like the Modified: vendor/llvm/dist-release_60/lib/MC/MCObjectStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCObjectStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCObjectStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -577,28 +577,13 @@ bool MCObjectStreamer::EmitRelocDirective(const MCExpr return false; } -void MCObjectStreamer::emitFill(uint64_t NumBytes, uint8_t FillValue) { - assert(getCurrentSectionOnly() && "need a section"); - insert(new MCFillFragment(FillValue, NumBytes)); -} - void MCObjectStreamer::emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc) { MCDataFragment *DF = getOrCreateDataFragment(); flushPendingLabels(DF, DF->getContents().size()); - int64_t IntNumBytes; - if (!NumBytes.evaluateAsAbsolute(IntNumBytes, getAssembler())) { - getContext().reportError(Loc, "expected absolute expression"); - return; - } - - if (IntNumBytes <= 0) { - getContext().reportError(Loc, "invalid number of bytes"); - return; - } - - emitFill(IntNumBytes, FillValue); + assert(getCurrentSectionOnly() && "need a section"); + insert(new MCFillFragment(FillValue, NumBytes, Loc)); } void MCObjectStreamer::emitFill(const MCExpr &NumValues, int64_t Size, Modified: vendor/llvm/dist-release_60/lib/MC/MCStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -184,8 +184,7 @@ void MCStreamer::EmitGPRel32Value(const MCExpr *Value) /// Emit NumBytes bytes worth of the value specified by FillValue. /// This implements directives such as '.space'. void MCStreamer::emitFill(uint64_t NumBytes, uint8_t FillValue) { - for (uint64_t i = 0, e = NumBytes; i != e; ++i) - EmitIntValue(FillValue, 1); + emitFill(*MCConstantExpr::create(NumBytes, getContext()), FillValue); } void MCStreamer::emitFill(uint64_t NumValues, int64_t Size, int64_t Expr) { Modified: vendor/llvm/dist-release_60/lib/MC/MCWinCOFFStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCWinCOFFStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCWinCOFFStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -257,20 +257,13 @@ void MCWinCOFFStreamer::EmitLocalCommonSymbol(MCSymbol auto *Symbol = cast(S); MCSection *Section = getContext().getObjectFileInfo()->getBSSSection(); - getAssembler().registerSection(*Section); - if (Section->getAlignment() < ByteAlignment) - Section->setAlignment(ByteAlignment); - - getAssembler().registerSymbol(*Symbol); + PushSection(); + SwitchSection(Section); + EmitValueToAlignment(ByteAlignment, 0, 1, 0); + EmitLabel(Symbol); Symbol->setExternal(false); - - if (ByteAlignment != 1) - new MCAlignFragment(ByteAlignment, /*Value=*/0, /*ValueSize=*/0, - ByteAlignment, Section); - - MCFillFragment *Fragment = new MCFillFragment( - /*Value=*/0, Size, Section); - Symbol->setFragment(Fragment); + EmitZeros(Size); + PopSection(); } void MCWinCOFFStreamer::EmitZerofill(MCSection *Section, MCSymbol *Symbol, Modified: vendor/llvm/dist-release_60/lib/MC/WasmObjectWriter.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/WasmObjectWriter.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/WasmObjectWriter.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -528,7 +528,10 @@ static void addData(SmallVectorImpl &DataBytes, Align->getMaxBytesToEmit()); DataBytes.resize(Size, Value); } else if (auto *Fill = dyn_cast(&Frag)) { - DataBytes.insert(DataBytes.end(), Fill->getSize(), Fill->getValue()); + int64_t Size; + if (!Fill->getSize().evaluateAsAbsolute(Size)) + llvm_unreachable("The fill should be an assembler constant"); + DataBytes.insert(DataBytes.end(), Size, Fill->getValue()); } else { const auto &DataFrag = cast(Frag); const SmallVectorImpl &Contents = DataFrag.getContents(); Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FastISel.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FastISel.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FastISel.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -476,26 +476,27 @@ unsigned AArch64FastISel::materializeGV(const GlobalVa // ADRP + LDRX BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), ADRPReg) - .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE); + .addGlobalAddress(GV, 0, AArch64II::MO_PAGE | OpFlags); ResultReg = createResultReg(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui), ResultReg) - .addReg(ADRPReg) - .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF | - AArch64II::MO_NC); + .addReg(ADRPReg) + .addGlobalAddress(GV, 0, + AArch64II::MO_PAGEOFF | AArch64II::MO_NC | OpFlags); } else { // ADRP + ADDX BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), ADRPReg) - .addGlobalAddress(GV, 0, AArch64II::MO_PAGE); + .addGlobalAddress(GV, 0, AArch64II::MO_PAGE | OpFlags); ResultReg = createResultReg(&AArch64::GPR64spRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri), ResultReg) - .addReg(ADRPReg) - .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC) - .addImm(0); + .addReg(ADRPReg) + .addGlobalAddress(GV, 0, + AArch64II::MO_PAGEOFF | AArch64II::MO_NC | OpFlags) + .addImm(0); } return ResultReg; } Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -929,6 +929,12 @@ bool AArch64InstructionSelector::select(MachineInstr & return false; } + // FIXME: PR36018: Volatile loads in some cases are incorrectly selected by + // folding with an extend. Until we have a G_SEXTLOAD solution bail out if + // we hit one. + if (Opcode == TargetOpcode::G_LOAD && MemOp.isVolatile()) + return false; + const unsigned PtrReg = I.getOperand(1).getReg(); #ifndef NDEBUG const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64Subtarget.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64Subtarget.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64Subtarget.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -189,15 +189,18 @@ AArch64Subtarget::ClassifyGlobalReference(const Global if (TM.getCodeModel() == CodeModel::Large && isTargetMachO()) return AArch64II::MO_GOT; + unsigned Flags = GV->hasDLLImportStorageClass() ? AArch64II::MO_DLLIMPORT + : AArch64II::MO_NO_FLAG; + if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) - return AArch64II::MO_GOT; + return AArch64II::MO_GOT | Flags; // The small code model's direct accesses use ADRP, which cannot // necessarily produce the value 0 (if the code is above 4GB). if (useSmallAddressing() && GV->hasExternalWeakLinkage()) - return AArch64II::MO_GOT; + return AArch64II::MO_GOT | Flags; - return AArch64II::MO_NO_FLAG; + return Flags; } unsigned char AArch64Subtarget::classifyGlobalFunctionReference( Modified: vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInsertSkips.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInsertSkips.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInsertSkips.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -210,65 +210,73 @@ void SIInsertSkips::kill(MachineInstr &MI) { switch (MI.getOperand(2).getImm()) { case ISD::SETOEQ: case ISD::SETEQ: - Opcode = AMDGPU::V_CMPX_EQ_F32_e32; + Opcode = AMDGPU::V_CMPX_EQ_F32_e64; break; case ISD::SETOGT: case ISD::SETGT: - Opcode = AMDGPU::V_CMPX_LT_F32_e32; + Opcode = AMDGPU::V_CMPX_LT_F32_e64; break; case ISD::SETOGE: case ISD::SETGE: - Opcode = AMDGPU::V_CMPX_LE_F32_e32; + Opcode = AMDGPU::V_CMPX_LE_F32_e64; break; case ISD::SETOLT: case ISD::SETLT: - Opcode = AMDGPU::V_CMPX_GT_F32_e32; + Opcode = AMDGPU::V_CMPX_GT_F32_e64; break; case ISD::SETOLE: case ISD::SETLE: - Opcode = AMDGPU::V_CMPX_GE_F32_e32; + Opcode = AMDGPU::V_CMPX_GE_F32_e64; break; case ISD::SETONE: case ISD::SETNE: - Opcode = AMDGPU::V_CMPX_LG_F32_e32; + Opcode = AMDGPU::V_CMPX_LG_F32_e64; break; case ISD::SETO: - Opcode = AMDGPU::V_CMPX_O_F32_e32; + Opcode = AMDGPU::V_CMPX_O_F32_e64; break; case ISD::SETUO: - Opcode = AMDGPU::V_CMPX_U_F32_e32; + Opcode = AMDGPU::V_CMPX_U_F32_e64; break; case ISD::SETUEQ: - Opcode = AMDGPU::V_CMPX_NLG_F32_e32; + Opcode = AMDGPU::V_CMPX_NLG_F32_e64; break; case ISD::SETUGT: - Opcode = AMDGPU::V_CMPX_NGE_F32_e32; + Opcode = AMDGPU::V_CMPX_NGE_F32_e64; break; case ISD::SETUGE: - Opcode = AMDGPU::V_CMPX_NGT_F32_e32; + Opcode = AMDGPU::V_CMPX_NGT_F32_e64; break; case ISD::SETULT: - Opcode = AMDGPU::V_CMPX_NLE_F32_e32; + Opcode = AMDGPU::V_CMPX_NLE_F32_e64; break; case ISD::SETULE: - Opcode = AMDGPU::V_CMPX_NLT_F32_e32; + Opcode = AMDGPU::V_CMPX_NLT_F32_e64; break; case ISD::SETUNE: - Opcode = AMDGPU::V_CMPX_NEQ_F32_e32; + Opcode = AMDGPU::V_CMPX_NEQ_F32_e64; break; default: llvm_unreachable("invalid ISD:SET cond code"); } - // TODO: Allow this: - if (!MI.getOperand(0).isReg() || - !TRI->isVGPR(MBB.getParent()->getRegInfo(), - MI.getOperand(0).getReg())) - llvm_unreachable("SI_KILL operand should be a VGPR"); + assert(MI.getOperand(0).isReg()); - BuildMI(MBB, &MI, DL, TII->get(Opcode)) - .add(MI.getOperand(1)) - .add(MI.getOperand(0)); + if (TRI->isVGPR(MBB.getParent()->getRegInfo(), + MI.getOperand(0).getReg())) { + Opcode = AMDGPU::getVOPe32(Opcode); + BuildMI(MBB, &MI, DL, TII->get(Opcode)) + .add(MI.getOperand(1)) + .add(MI.getOperand(0)); + } else { + BuildMI(MBB, &MI, DL, TII->get(Opcode)) + .addReg(AMDGPU::VCC, RegState::Define) + .addImm(0) // src0 modifiers + .add(MI.getOperand(1)) + .addImm(0) // src1 modifiers + .add(MI.getOperand(0)) + .addImm(0); // omod + } break; } case AMDGPU::SI_KILL_I1_TERMINATOR: { Modified: vendor/llvm/dist-release_60/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -39,11 +39,11 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, const MCSubtargetInfo &STI) { const MCInstrDesc &Desc = MII.get(MI->getOpcode()); uint64_t TSFlags = Desc.TSFlags; + unsigned Flags = MI->getFlags(); - if (TSFlags & X86II::LOCK) + if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) OS << "\tlock\t"; - unsigned Flags = MI->getFlags(); if (Flags & X86::IP_HAS_REPEAT_NE) OS << "\trepne\t"; else if (Flags & X86::IP_HAS_REPEAT) Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -31776,9 +31776,10 @@ static SDValue combineSelect(SDNode *N, SelectionDAG & // Check all uses of the condition operand to check whether it will be // consumed by non-BLEND instructions. Those may require that all bits // are set properly. - for (SDNode *U : Cond->uses()) { + for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end(); + UI != UE; ++UI) { // TODO: Add other opcodes eventually lowered into BLEND. - if (U->getOpcode() != ISD::VSELECT) + if (UI->getOpcode() != ISD::VSELECT || UI.getOperandNo() != 0) return SDValue(); } Modified: vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -142,10 +142,11 @@ recordConditions(const CallSite &CS, BasicBlock *Pred, recordCondition(CS, Pred, CS.getInstruction()->getParent(), Conditions); BasicBlock *From = Pred; BasicBlock *To = Pred; - SmallPtrSet Visited = {From}; + SmallPtrSet Visited; while (!Visited.count(From->getSinglePredecessor()) && (From = From->getSinglePredecessor())) { recordCondition(CS, From, To, Conditions); + Visited.insert(From); To = From; } } Modified: vendor/llvm/dist-release_60/lib/Transforms/Scalar/StructurizeCFG.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Transforms/Scalar/StructurizeCFG.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Transforms/Scalar/StructurizeCFG.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -14,6 +14,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Analysis/DivergenceAnalysis.h" +#include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/RegionInfo.h" #include "llvm/Analysis/RegionIterator.h" #include "llvm/Analysis/RegionPass.h" @@ -176,8 +177,9 @@ class StructurizeCFG : public RegionPass { Region *ParentRegion; DominatorTree *DT; + LoopInfo *LI; - std::deque Order; + SmallVector Order; BBSet Visited; BBPhiMap DeletedPhis; @@ -202,7 +204,7 @@ class StructurizeCFG : public RegionPass { void gatherPredicates(RegionNode *N); - void analyzeNode(RegionNode *N); + void collectInfos(); void insertConditions(bool Loops); @@ -256,6 +258,7 @@ class StructurizeCFG : public RegionPass { AU.addRequired(); AU.addRequiredID(LowerSwitchID); AU.addRequired(); + AU.addRequired(); AU.addPreserved(); RegionPass::getAnalysisUsage(AU); @@ -289,17 +292,55 @@ bool StructurizeCFG::doInitialization(Region *R, RGPas /// \brief Build up the general order of nodes void StructurizeCFG::orderNodes() { - assert(Visited.empty()); - assert(Predicates.empty()); - assert(Loops.empty()); - assert(LoopPreds.empty()); + ReversePostOrderTraversal RPOT(ParentRegion); + SmallDenseMap LoopBlocks; - // This must be RPO order for the back edge detection to work - for (RegionNode *RN : ReversePostOrderTraversal(ParentRegion)) { - // FIXME: Is there a better order to use for structurization? - Order.push_back(RN); - analyzeNode(RN); + // The reverse post-order traversal of the list gives us an ordering close + // to what we want. The only problem with it is that sometimes backedges + // for outer loops will be visited before backedges for inner loops. + for (RegionNode *RN : RPOT) { + BasicBlock *BB = RN->getEntry(); + Loop *Loop = LI->getLoopFor(BB); + ++LoopBlocks[Loop]; } + + unsigned CurrentLoopDepth = 0; + Loop *CurrentLoop = nullptr; + for (auto I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { + BasicBlock *BB = (*I)->getEntry(); + unsigned LoopDepth = LI->getLoopDepth(BB); + + if (is_contained(Order, *I)) + continue; + + if (LoopDepth < CurrentLoopDepth) { + // Make sure we have visited all blocks in this loop before moving back to + // the outer loop. + + auto LoopI = I; + while (unsigned &BlockCount = LoopBlocks[CurrentLoop]) { + LoopI++; + BasicBlock *LoopBB = (*LoopI)->getEntry(); + if (LI->getLoopFor(LoopBB) == CurrentLoop) { + --BlockCount; + Order.push_back(*LoopI); + } + } + } + + CurrentLoop = LI->getLoopFor(BB); + if (CurrentLoop) + LoopBlocks[CurrentLoop]--; + + CurrentLoopDepth = LoopDepth; + Order.push_back(*I); + } + + // This pass originally used a post-order traversal and then operated on + // the list in reverse. Now that we are using a reverse post-order traversal + // rather than re-working the whole pass to operate on the list in order, + // we just reverse the list and continue to operate on it in reverse. + std::reverse(Order.begin(), Order.end()); } /// \brief Determine the end of the loops @@ -425,19 +466,32 @@ void StructurizeCFG::gatherPredicates(RegionNode *N) { } /// \brief Collect various loop and predicate infos -void StructurizeCFG::analyzeNode(RegionNode *RN) { - DEBUG(dbgs() << "Visiting: " - << (RN->isSubRegion() ? "SubRegion with entry: " : "") - << RN->getEntry()->getName() << '\n'); +void StructurizeCFG::collectInfos() { + // Reset predicate + Predicates.clear(); - // Analyze all the conditions leading to a node - gatherPredicates(RN); + // and loop infos + Loops.clear(); + LoopPreds.clear(); - // Remember that we've seen this node - Visited.insert(RN->getEntry()); + // Reset the visited nodes + Visited.clear(); - // Find the last back edges - analyzeLoops(RN); + for (RegionNode *RN : reverse(Order)) { + DEBUG(dbgs() << "Visiting: " + << (RN->isSubRegion() ? "SubRegion with entry: " : "") + << RN->getEntry()->getName() << " Loop Depth: " + << LI->getLoopDepth(RN->getEntry()) << "\n"); + + // Analyze all the conditions leading to a node + gatherPredicates(RN); + + // Remember that we've seen this node + Visited.insert(RN->getEntry()); + + // Find the last back edges + analyzeLoops(RN); + } } /// \brief Insert the missing branch conditions @@ -610,7 +664,7 @@ void StructurizeCFG::changeExit(RegionNode *Node, Basi BasicBlock *StructurizeCFG::getNextFlow(BasicBlock *Dominator) { LLVMContext &Context = Func->getContext(); BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() : - Order.front()->getEntry(); + Order.back()->getEntry(); BasicBlock *Flow = BasicBlock::Create(Context, FlowBlockName, Func, Insert); DT->addNewBlock(Flow, Dominator); @@ -690,8 +744,7 @@ bool StructurizeCFG::isPredictableTrue(RegionNode *Nod /// Take one node from the order vector and wire it up void StructurizeCFG::wireFlow(bool ExitUseAllowed, BasicBlock *LoopEnd) { - RegionNode *Node = Order.front(); - Order.pop_front(); + RegionNode *Node = Order.pop_back_val(); Visited.insert(Node->getEntry()); if (isPredictableTrue(Node)) { @@ -715,7 +768,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed, PrevNode = Node; while (!Order.empty() && !Visited.count(LoopEnd) && - dominatesPredicates(Entry, Order.front())) { + dominatesPredicates(Entry, Order.back())) { handleLoops(false, LoopEnd); } @@ -726,7 +779,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed, void StructurizeCFG::handleLoops(bool ExitUseAllowed, BasicBlock *LoopEnd) { - RegionNode *Node = Order.front(); + RegionNode *Node = Order.back(); BasicBlock *LoopStart = Node->getEntry(); if (!Loops.count(LoopStart)) { @@ -871,9 +924,10 @@ bool StructurizeCFG::runOnRegion(Region *R, RGPassMana ParentRegion = R; DT = &getAnalysis().getDomTree(); + LI = &getAnalysis().getLoopInfo(); orderNodes(); - + collectInfos(); createFlow(); insertConditions(false); insertConditions(true); Modified: vendor/llvm/dist-release_60/lib/Transforms/Utils/ValueMapper.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Transforms/Utils/ValueMapper.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Transforms/Utils/ValueMapper.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -25,6 +25,7 @@ #include "llvm/IR/CallSite.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" +#include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalAlias.h" @@ -536,13 +537,23 @@ Optional MDNodeMapper::tryToMapOperand(con return None; } +static Metadata *cloneOrBuildODR(const MDNode &N) { + auto *CT = dyn_cast(&N); + // If ODR type uniquing is enabled, we would have uniqued composite types + // with identifiers during bitcode reading, so we can just use CT. + if (CT && CT->getContext().isODRUniquingDebugTypes() && + CT->getIdentifier() != "") + return const_cast(CT); + return MDNode::replaceWithDistinct(N.clone()); +} + MDNode *MDNodeMapper::mapDistinctNode(const MDNode &N) { assert(N.isDistinct() && "Expected a distinct node"); assert(!M.getVM().getMappedMD(&N) && "Expected an unmapped node"); - DistinctWorklist.push_back(cast( - (M.Flags & RF_MoveDistinctMDs) - ? M.mapToSelf(&N) - : M.mapToMetadata(&N, MDNode::replaceWithDistinct(N.clone())))); + DistinctWorklist.push_back( + cast((M.Flags & RF_MoveDistinctMDs) + ? M.mapToSelf(&N) + : M.mapToMetadata(&N, cloneOrBuildODR(N)))); return DistinctWorklist.back(); } Added: vendor/llvm/dist-release_60/test/Analysis/ValueTracking/select-pattern.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_60/test/Analysis/ValueTracking/select-pattern.ll Thu Feb 1 21:07:55 2018 (r328734) @@ -0,0 +1,46 @@ +; RUN: opt -simplifycfg < %s -S | FileCheck %s + +; The dead code would cause a select that had itself +; as an operand to be analyzed. This would then cause +; infinite recursion and eventual crash. + +define void @PR36045(i1 %t, i32* %b) { +; CHECK-LABEL: @PR36045( +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +entry: + br i1 %t, label %if, label %end + +if: + br i1 %t, label %unreach, label %pre + +unreach: + unreachable + +pre: + %p = phi i32 [ 70, %if ], [ %sel, %for ] + br label %for + +for: + %cmp = icmp sgt i32 %p, 8 + %add = add i32 %p, 2 + %sel = select i1 %cmp, i32 %p, i32 %add + %cmp21 = icmp ult i32 %sel, 21 + br i1 %cmp21, label %pre, label %for.end + +for.end: + br i1 %t, label %unreach2, label %then12 + +then12: + store i32 0, i32* %b + br label %unreach2 + +unreach2: + %spec = phi i32 [ %sel, %for.end ], [ 42, %then12 ] + unreachable + +end: + ret void +} + Added: vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll Thu Feb 1 21:07:55 2018 (r328734) @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=aarch64_be-- %s -o /dev/null -debug-only=isel -O0 2>&1 | FileCheck %s +; REQUIRES: asserts + +; This test uses big endian in order to force an abort since it's not currently supported for GISel. +; The purpose is to check that we don't fall back to FastISel. Checking the pass structure is insufficient +; because the FastISel is set up in the SelectionDAGISel, so it doesn't appear on the pass structure. + +; CHECK-NOT: Enabling fast-ise +define void @empty() { + ret void +} Added: vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll Thu Feb 1 21:07:55 2018 (r328734) @@ -0,0 +1,14 @@ +; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s + +@g = global i16 0, align 2 +declare void @bar(i32) + *** DIFF OUTPUT TRUNCATED AT 1000 LINES *** From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:13:19 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 486CFEC9E2E; Thu, 1 Feb 2018 21:13:19 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id DCA4C86B53; Thu, 1 Feb 2018 21:13:18 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id BEBBE12684; Thu, 1 Feb 2018 21:13:18 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11LDIac078476; Thu, 1 Feb 2018 21:13:18 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11LDIai078475; Thu, 1 Feb 2018 21:13:18 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012113.w11LDIai078475@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:13:18 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328738 - vendor/llvm/llvm-release_60-r323948 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/llvm/llvm-release_60-r323948 X-SVN-Commit-Revision: 328738 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:13:19 -0000 Author: dim Date: Thu Feb 1 21:13:18 2018 New Revision: 328738 URL: https://svnweb.freebsd.org/changeset/base/328738 Log: Tag llvm release_60 branch r323948. Added: vendor/llvm/llvm-release_60-r323948/ - copied from r328737, vendor/llvm/dist-release_60/ From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:14:17 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id B97A2EC9F08; Thu, 1 Feb 2018 21:14:16 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 6A2B386CA4; Thu, 1 Feb 2018 21:14:16 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 64F4512685; Thu, 1 Feb 2018 21:14:16 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11LEGdw078589; Thu, 1 Feb 2018 21:14:16 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11LEFIM078580; Thu, 1 Feb 2018 21:14:15 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012114.w11LEFIM078580@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:14:15 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328739 - in vendor/clang/dist-release_60: docs include/clang/Basic include/clang/Driver lib/Basic/Targets lib/Driver/ToolChains test/Driver X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/clang/dist-release_60: docs include/clang/Basic include/clang/Driver lib/Basic/Targets lib/Driver/ToolChains test/Driver X-SVN-Commit-Revision: 328739 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:14:17 -0000 Author: dim Date: Thu Feb 1 21:14:15 2018 New Revision: 328739 URL: https://svnweb.freebsd.org/changeset/base/328739 Log: Vendor import of clang release_60 branch r323948: https://llvm.org/svn/llvm-project/cfe/branches/release_60@323948 Added: vendor/clang/dist-release_60/test/Driver/global-isel.c (contents, props changed) Modified: vendor/clang/dist-release_60/docs/ReleaseNotes.rst vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td vendor/clang/dist-release_60/include/clang/Basic/DiagnosticGroups.td vendor/clang/dist-release_60/include/clang/Driver/Options.td vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/Hexagon.cpp vendor/clang/dist-release_60/test/Driver/hexagon-hvx.c Modified: vendor/clang/dist-release_60/docs/ReleaseNotes.rst ============================================================================== --- vendor/clang/dist-release_60/docs/ReleaseNotes.rst Thu Feb 1 21:13:18 2018 (r328738) +++ vendor/clang/dist-release_60/docs/ReleaseNotes.rst Thu Feb 1 21:14:15 2018 (r328739) @@ -213,7 +213,49 @@ Objective-C Language Changes in Clang OpenCL C Language Changes in Clang ---------------------------------- -... + +- Added subgroup builtins to enqueue kernel support. + +- Added CL2.0 atomics as Clang builtins that now accept + an additional memory scope parameter propagated to atomic IR instructions + (this is to align with the corresponding change in LLVM IR) (see `spec s6.13.11.4 + `_). + +- Miscellaneous fixes in the CL header. + +- Allow per target selection of address space during CodeGen of certain OpenCL types. + Default target implementation is provided mimicking old behavior. + +- Macro ``__IMAGE_SUPPORT__`` is now automatically added (as per `spec s6.10 + `_). + +- Added ``cl_intel_subgroups`` and ``cl_intel_subgroups_short`` extensions. + +- All function calls are marked by `the convergent attribute + `_ + to prevent optimizations that break SPMD program semantics. This will be removed + by LLVM passes if it can be proved that the function does not use convergent + operations. + +- Create a kernel wrapper for enqueued blocks, which simplifies enqueue support by + providing common functionality. + +- Added private address space explicitly in AST and refactored address space support + with several simplifications and bug fixes (`PR33419 `_ + and `PR33420 `_). + +- OpenCL now allows functions with empty parameters to be treated as if they had a + void parameter list (inspired from C++ support). OpenCL C spec update to follow. + +- General miscellaneous refactoring and cleanup of blocks support for OpenCL to + remove unused parts inherited from Objective C implementation. + +- Miscellaneous improvements in vector diagnostics. + +- Added half float load and store builtins without enabling half as a legal type + (``__builtin_store_half for double``, ``__builtin_store_halff`` for double, + ``__builtin_load_half for double``, ``__builtin_load_halff`` for float). + OpenMP Support in Clang ---------------------------------- Modified: vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td Thu Feb 1 21:13:18 2018 (r328738) +++ vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td Thu Feb 1 21:14:15 2018 (r328739) @@ -354,4 +354,12 @@ def warn_drv_fine_grained_bitfield_accesses_ignored : def note_drv_verify_prefix_spelling : Note< "-verify prefixes must start with a letter and contain only alphanumeric" " characters, hyphens, and underscores">; + +def warn_drv_experimental_isel_incomplete : Warning< + "-fexperimental-isel support for the '%0' architecture is incomplete">, + InGroup; + +def warn_drv_experimental_isel_incomplete_opt : Warning< + "-fexperimental-isel support is incomplete for this architecture at the current optimization level">, + InGroup; } Modified: vendor/clang/dist-release_60/include/clang/Basic/DiagnosticGroups.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Basic/DiagnosticGroups.td Thu Feb 1 21:13:18 2018 (r328738) +++ vendor/clang/dist-release_60/include/clang/Basic/DiagnosticGroups.td Thu Feb 1 21:14:15 2018 (r328739) @@ -985,3 +985,6 @@ def UnknownArgument : DiagGroup<"unknown-argument">; // A warning group for warnings about code that clang accepts when // compiling OpenCL C/C++ but which is not compatible with the SPIR spec. def SpirCompat : DiagGroup<"spir-compat">; + +// Warning for the experimental-isel options. +def ExperimentalISel : DiagGroup<"experimental-isel">; Modified: vendor/clang/dist-release_60/include/clang/Driver/Options.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Driver/Options.td Thu Feb 1 21:13:18 2018 (r328738) +++ vendor/clang/dist-release_60/include/clang/Driver/Options.td Thu Feb 1 21:14:15 2018 (r328739) @@ -1031,6 +1031,8 @@ def finline_functions : Flag<["-"], "finline-functions def finline_hint_functions: Flag<["-"], "finline-hint-functions">, Group, Flags<[CC1Option]>, HelpText<"Inline functions which are (explicitly or implicitly) marked inline">; def finline : Flag<["-"], "finline">, Group; +def fexperimental_isel : Flag<["-"], "fexperimental-isel">, Group, + HelpText<"Enables the experimental global instruction selector">; def fexperimental_new_pass_manager : Flag<["-"], "fexperimental-new-pass-manager">, Group, Flags<[CC1Option]>, HelpText<"Enables an experimental new pass manager in LLVM.">; @@ -1237,6 +1239,8 @@ def fno_exceptions : Flag<["-"], "fno-exceptions">, Gr def fno_gnu_keywords : Flag<["-"], "fno-gnu-keywords">, Group, Flags<[CC1Option]>; def fno_inline_functions : Flag<["-"], "fno-inline-functions">, Group, Flags<[CC1Option]>; def fno_inline : Flag<["-"], "fno-inline">, Group, Flags<[CC1Option]>; +def fno_experimental_isel : Flag<["-"], "fno-experimental-isel">, Group, + HelpText<"Disables the experimental global instruction selector">; def fno_experimental_new_pass_manager : Flag<["-"], "fno-experimental-new-pass-manager">, Group, Flags<[CC1Option]>, HelpText<"Disables an experimental new pass manager in LLVM.">; Modified: vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp Thu Feb 1 21:13:18 2018 (r328738) +++ vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp Thu Feb 1 21:14:15 2018 (r328739) @@ -409,7 +409,7 @@ void X86TargetInfo::setSSELevel(llvm::StringMap if (Enabled) { switch (Level) { case AVX512F: - Features["avx512f"] = true; + Features["avx512f"] = Features["fma"] = Features["f16c"] = true; LLVM_FALLTHROUGH; case AVX2: Features["avx2"] = true; @@ -623,6 +623,8 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::String } else if (Name == "fma") { if (Enabled) setSSELevel(Features, AVX, Enabled); + else + setSSELevel(Features, AVX512F, Enabled); } else if (Name == "fma4") { setXOPLevel(Features, FMA4, Enabled); } else if (Name == "xop") { @@ -632,6 +634,8 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::String } else if (Name == "f16c") { if (Enabled) setSSELevel(Features, AVX, Enabled); + else + setSSELevel(Features, AVX512F, Enabled); } else if (Name == "sha") { if (Enabled) setSSELevel(Features, SSE2, Enabled); Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp Thu Feb 1 21:13:18 2018 (r328738) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp Thu Feb 1 21:14:15 2018 (r328739) @@ -4639,6 +4639,37 @@ void Clang::ConstructJob(Compilation &C, const JobActi CmdArgs.push_back("-fwhole-program-vtables"); } + if (Arg *A = Args.getLastArg(options::OPT_fexperimental_isel, + options::OPT_fno_experimental_isel)) { + CmdArgs.push_back("-mllvm"); + if (A->getOption().matches(options::OPT_fexperimental_isel)) { + CmdArgs.push_back("-global-isel=1"); + + // GISel is on by default on AArch64 -O0, so don't bother adding + // the fallback remarks for it. Other combinations will add a warning of + // some kind. + bool IsArchSupported = Triple.getArch() == llvm::Triple::aarch64; + bool IsOptLevelSupported = false; + + Arg *A = Args.getLastArg(options::OPT_O_Group); + if (Triple.getArch() == llvm::Triple::aarch64) { + if (!A || A->getOption().matches(options::OPT_O0)) + IsOptLevelSupported = true; + } + if (!IsArchSupported || !IsOptLevelSupported) { + CmdArgs.push_back("-mllvm"); + CmdArgs.push_back("-global-isel-abort=2"); + + if (!IsArchSupported) + D.Diag(diag::warn_drv_experimental_isel_incomplete) << Triple.getArchName(); + else + D.Diag(diag::warn_drv_experimental_isel_incomplete_opt); + } + } else { + CmdArgs.push_back("-global-isel=0"); + } + } + // Finally add the compile command to the compilation. if (Args.hasArg(options::OPT__SLASH_fallback) && Output.getType() == types::TY_Object && Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/Hexagon.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/Hexagon.cpp Thu Feb 1 21:13:18 2018 (r328738) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/Hexagon.cpp Thu Feb 1 21:14:15 2018 (r328739) @@ -46,7 +46,7 @@ static void handleHVXWarnings(const Driver &D, const A // Handle the unsupported values passed to mhvx-length. if (Arg *A = Args.getLastArg(options::OPT_mhexagon_hvx_length_EQ)) { StringRef Val = A->getValue(); - if (Val != "64B" && Val != "128B") + if (!Val.equals_lower("64b") && !Val.equals_lower("128b")) D.Diag(diag::err_drv_unsupported_option_argument) << A->getOption().getName() << Val; } Added: vendor/clang/dist-release_60/test/Driver/global-isel.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/clang/dist-release_60/test/Driver/global-isel.c Thu Feb 1 21:14:15 2018 (r328739) @@ -0,0 +1,24 @@ +// REQUIRES: x86-registered-target,aarch64-registered-target + +// RUN: %clang -fexperimental-isel -S -### %s 2>&1 | FileCheck --check-prefix=ENABLED %s +// RUN: %clang -fno-experimental-isel -S -### %s 2>&1 | FileCheck --check-prefix=DISABLED %s + +// RUN: %clang -target aarch64 -fexperimental-isel -S %s -### 2>&1 | FileCheck --check-prefix=ARM64-DEFAULT %s +// RUN: %clang -target aarch64 -fexperimental-isel -S -O0 %s -### 2>&1 | FileCheck --check-prefix=ARM64-O0 %s +// RUN: %clang -target aarch64 -fexperimental-isel -S -O2 %s -### 2>&1 | FileCheck --check-prefix=ARM64-O2 %s +// RUN: %clang -target aarch64 -fexperimental-isel -Wno-experimental-isel -S -O2 %s -### 2>&1 | FileCheck --check-prefix=ARM64-O2-NOWARN %s + +// RUN: %clang -target x86_64 -fexperimental-isel -S %s -### 2>&1 | FileCheck --check-prefix=X86_64 %s + +// ENABLED: "-mllvm" "-global-isel=1" +// DISABLED: "-mllvm" "-global-isel=0" + +// ARM64-DEFAULT-NOT: warning: -fexperimental-sel +// ARM64-DEFAULT-NOT: "-global-isel-abort=2" +// ARM64-O0-NOT: warning: -fexperimental-sel +// ARM64-O2: warning: -fexperimental-isel support is incomplete for this architecture at the current optimization level +// ARM64-O2: "-mllvm" "-global-isel-abort=2" +// ARM64-O2-NOWARN-NOT: warning: -fexperimental-isel + +// X86_64: -fexperimental-isel support for the 'x86_64' architecture is incomplete +// X86_64: "-mllvm" "-global-isel-abort=2" Modified: vendor/clang/dist-release_60/test/Driver/hexagon-hvx.c ============================================================================== --- vendor/clang/dist-release_60/test/Driver/hexagon-hvx.c Thu Feb 1 21:13:18 2018 (r328738) +++ vendor/clang/dist-release_60/test/Driver/hexagon-hvx.c Thu Feb 1 21:14:15 2018 (r328739) @@ -21,6 +21,9 @@ // RUN: %clang -c %s -### -target hexagon-unknown-elf -mv62 -mhvx \ // RUN: -mhvx-length=128B 2>&1 | FileCheck -check-prefix=CHECKHVX2 %s + +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv62 -mhvx \ +// RUN: -mhvx-length=128b 2>&1 | FileCheck -check-prefix=CHECKHVX2 %s // CHECKHVX2-NOT: "-target-feature" "+hvx-length64b" // CHECKHVX2: "-target-feature" "+hvx-length128b" @@ -79,8 +82,10 @@ // The default mode on v60,v62 is 64B. // RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-64B %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx -mhvx-length=64B\ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-64B %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx \ +// RUN: -mhvx-length=64b 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-64B %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx \ +// RUN: -mhvx-length=64B 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-64B %s // CHECK-HVXLENGTH-64B: "-target-feature" "+hvx{{.*}}" "-target-feature" "+hvx-length64b" // RUN: %clang -c %s -### -target hexagon-unknown-elf -mv62 -mhvx -mhvx-length=128B\ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-128B %s From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:14:19 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id CB5ECEC9F31; Thu, 1 Feb 2018 21:14:19 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 7EF8B86CB6; Thu, 1 Feb 2018 21:14:19 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 604B412686; Thu, 1 Feb 2018 21:14:19 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11LEJ41078637; Thu, 1 Feb 2018 21:14:19 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11LEJFX078636; Thu, 1 Feb 2018 21:14:19 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012114.w11LEJFX078636@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:14:19 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328740 - vendor/clang/clang-release_60-r323948 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/clang/clang-release_60-r323948 X-SVN-Commit-Revision: 328740 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:14:20 -0000 Author: dim Date: Thu Feb 1 21:14:19 2018 New Revision: 328740 URL: https://svnweb.freebsd.org/changeset/base/328740 Log: Tag clang release_60 branch r323948. Added: vendor/clang/clang-release_60-r323948/ - copied from r328739, vendor/clang/dist-release_60/ From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:14:24 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 96317EC9F71; Thu, 1 Feb 2018 21:14:24 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 25AB686D94; Thu, 1 Feb 2018 21:14:24 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 0CB3E12688; Thu, 1 Feb 2018 21:14:24 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11LENb7078733; Thu, 1 Feb 2018 21:14:23 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11LEN8t078731; Thu, 1 Feb 2018 21:14:23 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012114.w11LEN8t078731@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:14:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328742 - in vendor/compiler-rt/dist-release_60/lib: hwasan tsan/rtl X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/compiler-rt/dist-release_60/lib: hwasan tsan/rtl X-SVN-Commit-Revision: 328742 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:14:24 -0000 Author: dim Date: Thu Feb 1 21:14:23 2018 New Revision: 328742 URL: https://svnweb.freebsd.org/changeset/base/328742 Log: Vendor import of compiler-rt release_60 branch r323948: https://llvm.org/svn/llvm-project/compiler-rt/branches/release_60@323948 Modified: vendor/compiler-rt/dist-release_60/lib/hwasan/CMakeLists.txt vendor/compiler-rt/dist-release_60/lib/tsan/rtl/tsan_platform.h Modified: vendor/compiler-rt/dist-release_60/lib/hwasan/CMakeLists.txt ============================================================================== --- vendor/compiler-rt/dist-release_60/lib/hwasan/CMakeLists.txt Thu Feb 1 21:14:21 2018 (r328741) +++ vendor/compiler-rt/dist-release_60/lib/hwasan/CMakeLists.txt Thu Feb 1 21:14:23 2018 (r328742) @@ -17,7 +17,7 @@ set(HWASAN_RTL_CXX_SOURCES set(HWASAN_RTL_CFLAGS ${SANITIZER_COMMON_CFLAGS}) append_rtti_flag(OFF HWASAN_RTL_CFLAGS) -append_list_if(COMPILER_RT_HAS_FPIE_FLAG -fPIE HWASAN_RTL_CFLAGS) +append_list_if(COMPILER_RT_HAS_FPIC_FLAG -fPIC HWASAN_RTL_CFLAGS) # Prevent clang from generating libc calls. append_list_if(COMPILER_RT_HAS_FFREESTANDING_FLAG -ffreestanding HWASAN_RTL_CFLAGS) Modified: vendor/compiler-rt/dist-release_60/lib/tsan/rtl/tsan_platform.h ============================================================================== --- vendor/compiler-rt/dist-release_60/lib/tsan/rtl/tsan_platform.h Thu Feb 1 21:14:21 2018 (r328741) +++ vendor/compiler-rt/dist-release_60/lib/tsan/rtl/tsan_platform.h Thu Feb 1 21:14:23 2018 (r328742) @@ -79,25 +79,27 @@ struct Mapping { #define TSAN_MID_APP_RANGE 1 #elif defined(__mips64) /* -C/C++ on linux/mips64 -0100 0000 00 - 0200 0000 00: main binary -0200 0000 00 - 1400 0000 00: - -1400 0000 00 - 2400 0000 00: shadow -2400 0000 00 - 3000 0000 00: - -3000 0000 00 - 4000 0000 00: metainfo (memory blocks and sync objects) -4000 0000 00 - 6000 0000 00: - -6000 0000 00 - 6200 0000 00: traces -6200 0000 00 - fe00 0000 00: - -fe00 0000 00 - ff00 0000 00: heap -ff00 0000 00 - ff80 0000 00: - -ff80 0000 00 - ffff ffff ff: modules and main thread stack +C/C++ on linux/mips64 (40-bit VMA) +0000 0000 00 - 0100 0000 00: - (4 GB) +0100 0000 00 - 0200 0000 00: main binary (4 GB) +0200 0000 00 - 2000 0000 00: - (120 GB) +2000 0000 00 - 4000 0000 00: shadow (128 GB) +4000 0000 00 - 5000 0000 00: metainfo (memory blocks and sync objects) (64 GB) +5000 0000 00 - aa00 0000 00: - (360 GB) +aa00 0000 00 - ab00 0000 00: main binary (PIE) (4 GB) +ab00 0000 00 - b000 0000 00: - (20 GB) +b000 0000 00 - b200 0000 00: traces (8 GB) +b200 0000 00 - fe00 0000 00: - (304 GB) +fe00 0000 00 - ff00 0000 00: heap (4 GB) +ff00 0000 00 - ff80 0000 00: - (2 GB) +ff80 0000 00 - ffff ffff ff: modules and main thread stack (<2 GB) */ struct Mapping { static const uptr kMetaShadowBeg = 0x4000000000ull; static const uptr kMetaShadowEnd = 0x5000000000ull; static const uptr kTraceMemBeg = 0xb000000000ull; static const uptr kTraceMemEnd = 0xb200000000ull; - static const uptr kShadowBeg = 0x2400000000ull; + static const uptr kShadowBeg = 0x2000000000ull; static const uptr kShadowEnd = 0x4000000000ull; static const uptr kHeapMemBeg = 0xfe00000000ull; static const uptr kHeapMemEnd = 0xff00000000ull; From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:14:34 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 61C90EC9FDA; Thu, 1 Feb 2018 21:14:34 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 0CC6F86E48; Thu, 1 Feb 2018 21:14:27 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 01D3912689; Thu, 1 Feb 2018 21:14:27 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11LEQAS078781; Thu, 1 Feb 2018 21:14:26 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11LEQom078780; Thu, 1 Feb 2018 21:14:26 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012114.w11LEQom078780@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:14:26 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328743 - vendor/compiler-rt/compiler-rt-release_60-r323948 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/compiler-rt/compiler-rt-release_60-r323948 X-SVN-Commit-Revision: 328743 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:14:34 -0000 Author: dim Date: Thu Feb 1 21:14:26 2018 New Revision: 328743 URL: https://svnweb.freebsd.org/changeset/base/328743 Log: Tag compiler-rt release_60 branch r323948. Added: vendor/compiler-rt/compiler-rt-release_60-r323948/ - copied from r328742, vendor/compiler-rt/dist-release_60/ From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:14:34 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 7447EEC9FDB; Thu, 1 Feb 2018 21:14:34 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id DFC6A86F28; Thu, 1 Feb 2018 21:14:32 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 2B6331268A; Thu, 1 Feb 2018 21:14:32 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11LEW9V078832; Thu, 1 Feb 2018 21:14:32 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11LEWSg078831; Thu, 1 Feb 2018 21:14:32 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012114.w11LEWSg078831@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:14:32 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328744 - vendor/libc++/libc++-release_60-r323948 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/libc++/libc++-release_60-r323948 X-SVN-Commit-Revision: 328744 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:14:34 -0000 Author: dim Date: Thu Feb 1 21:14:31 2018 New Revision: 328744 URL: https://svnweb.freebsd.org/changeset/base/328744 Log: Tag libc++ release_60 branch r323948. Added: vendor/libc++/libc++-release_60-r323948/ - copied from r328743, vendor/libc++/dist-release_60/ From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:14:40 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6C578ECA059; Thu, 1 Feb 2018 21:14:40 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id C214286FD9; Thu, 1 Feb 2018 21:14:36 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id ECC481268B; Thu, 1 Feb 2018 21:14:35 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11LEZ7D078897; Thu, 1 Feb 2018 21:14:35 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11LEYt8078882; Thu, 1 Feb 2018 21:14:34 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012114.w11LEYt8078882@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:14:34 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328745 - in vendor/lld/dist-release_60: ELF test/ELF/linkerscript X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/lld/dist-release_60: ELF test/ELF/linkerscript X-SVN-Commit-Revision: 328745 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:14:40 -0000 Author: dim Date: Thu Feb 1 21:14:34 2018 New Revision: 328745 URL: https://svnweb.freebsd.org/changeset/base/328745 Log: Vendor import of lld release_60 branch r323948: https://llvm.org/svn/llvm-project/lld/branches/release_60@323948 Added: vendor/lld/dist-release_60/test/ELF/linkerscript/at3.s (contents, props changed) vendor/lld/dist-release_60/test/ELF/linkerscript/merge-header-load.s (contents, props changed) Modified: vendor/lld/dist-release_60/ELF/AArch64ErrataFix.cpp vendor/lld/dist-release_60/ELF/LinkerScript.cpp vendor/lld/dist-release_60/ELF/LinkerScript.h vendor/lld/dist-release_60/ELF/OutputSections.h vendor/lld/dist-release_60/ELF/ScriptParser.cpp vendor/lld/dist-release_60/ELF/Writer.cpp vendor/lld/dist-release_60/ELF/Writer.h Modified: vendor/lld/dist-release_60/ELF/AArch64ErrataFix.cpp ============================================================================== --- vendor/lld/dist-release_60/ELF/AArch64ErrataFix.cpp Thu Feb 1 21:14:31 2018 (r328744) +++ vendor/lld/dist-release_60/ELF/AArch64ErrataFix.cpp Thu Feb 1 21:14:34 2018 (r328745) @@ -47,6 +47,7 @@ using namespace llvm; using namespace llvm::ELF; using namespace llvm::object; +using namespace llvm::support; using namespace llvm::support::endian; using namespace lld; @@ -357,7 +358,7 @@ static uint64_t scanCortexA53Errata843419(InputSection uint64_t PatchOff = 0; const uint8_t *Buf = IS->Data.begin(); - const uint32_t *InstBuf = reinterpret_cast(Buf + Off); + const ulittle32_t *InstBuf = reinterpret_cast(Buf + Off); uint32_t Instr1 = *InstBuf++; uint32_t Instr2 = *InstBuf++; uint32_t Instr3 = *InstBuf++; Modified: vendor/lld/dist-release_60/ELF/LinkerScript.cpp ============================================================================== --- vendor/lld/dist-release_60/ELF/LinkerScript.cpp Thu Feb 1 21:14:31 2018 (r328744) +++ vendor/lld/dist-release_60/ELF/LinkerScript.cpp Thu Feb 1 21:14:34 2018 (r328745) @@ -589,8 +589,12 @@ void LinkerScript::output(InputSection *S) { // If there is a memory region associated with this input section, then // place the section in that region and update the region index. + if (Ctx->LMARegion) + Ctx->LMARegion->CurPos += Pos - Before; + // FIXME: should we also produce overflow errors for LMARegion? + if (Ctx->MemRegion) { - uint64_t &CurOffset = Ctx->MemRegionOffset[Ctx->MemRegion]; + uint64_t &CurOffset = Ctx->MemRegion->CurPos; CurOffset += Pos - Before; uint64_t CurSize = CurOffset - Ctx->MemRegion->Origin; if (CurSize > Ctx->MemRegion->Length) { @@ -617,9 +621,8 @@ MemoryRegion *LinkerScript::findMemoryRegion(OutputSec // If a memory region name was specified in the output section command, // then try to find that region first. if (!Sec->MemoryRegionName.empty()) { - auto It = MemoryRegions.find(Sec->MemoryRegionName); - if (It != MemoryRegions.end()) - return It->second; + if (MemoryRegion *M = MemoryRegions.lookup(Sec->MemoryRegionName)) + return M; error("memory region '" + Sec->MemoryRegionName + "' not declared"); return nullptr; } @@ -652,31 +655,24 @@ void LinkerScript::assignOffsets(OutputSection *Sec) { setDot(Sec->AddrExpr, Sec->Location, false); Ctx->MemRegion = Sec->MemRegion; + Ctx->LMARegion = Sec->LMARegion; if (Ctx->MemRegion) - Dot = Ctx->MemRegionOffset[Ctx->MemRegion]; + Dot = Ctx->MemRegion->CurPos; switchTo(Sec); - if (Sec->LMAExpr) { - uint64_t D = Dot; - Ctx->LMAOffset = [=] { return Sec->LMAExpr().getValue() - D; }; - } + if (Sec->LMAExpr) + Ctx->LMAOffset = Sec->LMAExpr().getValue() - Dot; - if (!Sec->LMARegionName.empty()) { - if (MemoryRegion *MR = MemoryRegions.lookup(Sec->LMARegionName)) { - uint64_t Offset = MR->Origin - Dot; - Ctx->LMAOffset = [=] { return Offset; }; - } else { - error("memory region '" + Sec->LMARegionName + "' not declared"); - } - } + if (MemoryRegion *MR = Sec->LMARegion) + Ctx->LMAOffset = MR->CurPos - Dot; // If neither AT nor AT> is specified for an allocatable section, the linker // will set the LMA such that the difference between VMA and LMA for the // section is the same as the preceding output section in the same region // https://sourceware.org/binutils/docs-2.20/ld/Output-Section-LMA.html - if (Ctx->LMAOffset) - Ctx->OutSec->LMAOffset = Ctx->LMAOffset(); + if (PhdrEntry *L = Ctx->OutSec->PtLoad) + L->LMAOffset = Ctx->LMAOffset; // The Size previously denoted how many InputSections had been added to this // section, and was used for sorting SHF_LINK_ORDER sections. Reset it to @@ -698,7 +694,9 @@ void LinkerScript::assignOffsets(OutputSection *Sec) { Cmd->Offset = Dot - Ctx->OutSec->Addr; Dot += Cmd->Size; if (Ctx->MemRegion) - Ctx->MemRegionOffset[Ctx->MemRegion] += Cmd->Size; + Ctx->MemRegion->CurPos += Cmd->Size; + if (Ctx->LMARegion) + Ctx->LMARegion->CurPos += Cmd->Size; Ctx->OutSec->Size = Dot - Ctx->OutSec->Addr; continue; } @@ -797,6 +795,12 @@ void LinkerScript::adjustSectionsAfterSorting() { if (auto *Sec = dyn_cast(Base)) { if (!Sec->Live) continue; + if (!Sec->LMARegionName.empty()) { + if (MemoryRegion *M = MemoryRegions.lookup(Sec->LMARegionName)) + Sec->LMARegion = M; + else + error("memory region '" + Sec->LMARegionName + "' not declared"); + } Sec->MemRegion = findMemoryRegion(Sec); // Handle align (e.g. ".foo : ALIGN(16) { ... }"). if (Sec->AlignExpr) @@ -887,8 +891,8 @@ void LinkerScript::allocateHeaders(std::vectorMemoryRegions) { - const MemoryRegion *MR = MRI.second; - MemRegionOffset[MR] = MR->Origin; + MemoryRegion *MR = MRI.second; + MR->CurPos = MR->Origin; } } Modified: vendor/lld/dist-release_60/ELF/LinkerScript.h ============================================================================== --- vendor/lld/dist-release_60/ELF/LinkerScript.h Thu Feb 1 21:14:31 2018 (r328744) +++ vendor/lld/dist-release_60/ELF/LinkerScript.h Thu Feb 1 21:14:34 2018 (r328745) @@ -118,11 +118,17 @@ enum class ConstraintKind { NoConstraint, ReadOnly, Re // target memory. Instances of the struct are created by parsing the // MEMORY command. struct MemoryRegion { + MemoryRegion(StringRef Name, uint64_t Origin, uint64_t Length, uint32_t Flags, + uint32_t NegFlags) + : Name(Name), Origin(Origin), Length(Length), Flags(Flags), + NegFlags(NegFlags) {} + std::string Name; uint64_t Origin; uint64_t Length; uint32_t Flags; uint32_t NegFlags; + uint64_t CurPos = 0; }; // This struct represents one section match pattern in SECTIONS() command. @@ -200,8 +206,8 @@ class LinkerScript final { uint64_t ThreadBssOffset = 0; OutputSection *OutSec = nullptr; MemoryRegion *MemRegion = nullptr; - llvm::DenseMap MemRegionOffset; - std::function LMAOffset; + MemoryRegion *LMARegion = nullptr; + uint64_t LMAOffset = 0; }; llvm::DenseMap NameToOutputSection; Modified: vendor/lld/dist-release_60/ELF/OutputSections.h ============================================================================== --- vendor/lld/dist-release_60/ELF/OutputSections.h Thu Feb 1 21:14:31 2018 (r328744) +++ vendor/lld/dist-release_60/ELF/OutputSections.h Thu Feb 1 21:14:34 2018 (r328745) @@ -49,7 +49,7 @@ class OutputSection final : public BaseCommand, public static bool classof(const BaseCommand *C); - uint64_t getLMA() const { return Addr + LMAOffset; } + uint64_t getLMA() const { return PtLoad ? Addr + PtLoad->LMAOffset : Addr; } template void writeHeaderTo(typename ELFT::Shdr *SHdr); unsigned SectionIndex; @@ -78,7 +78,6 @@ class OutputSection final : public BaseCommand, public // The following fields correspond to Elf_Shdr members. uint64_t Offset = 0; - uint64_t LMAOffset = 0; uint64_t Addr = 0; uint32_t ShName = 0; @@ -89,6 +88,7 @@ class OutputSection final : public BaseCommand, public // The following members are normally only used in linker scripts. MemoryRegion *MemRegion = nullptr; + MemoryRegion *LMARegion = nullptr; Expr AddrExpr; Expr AlignExpr; Expr LMAExpr; Modified: vendor/lld/dist-release_60/ELF/ScriptParser.cpp ============================================================================== --- vendor/lld/dist-release_60/ELF/ScriptParser.cpp Thu Feb 1 21:14:31 2018 (r328744) +++ vendor/lld/dist-release_60/ELF/ScriptParser.cpp Thu Feb 1 21:14:34 2018 (r328745) @@ -1293,8 +1293,8 @@ void ScriptParser::readMemory() { // Add the memory region to the region map. if (Script->MemoryRegions.count(Name)) setError("region '" + Name + "' already defined"); - MemoryRegion *MR = make(); - *MR = {Name, Origin, Length, Flags, NegFlags}; + MemoryRegion *MR = + make(Name, Origin, Length, Flags, NegFlags); Script->MemoryRegions[Name] = MR; } } Modified: vendor/lld/dist-release_60/ELF/Writer.cpp ============================================================================== --- vendor/lld/dist-release_60/ELF/Writer.cpp Thu Feb 1 21:14:31 2018 (r328744) +++ vendor/lld/dist-release_60/ELF/Writer.cpp Thu Feb 1 21:14:34 2018 (r328745) @@ -822,6 +822,8 @@ void PhdrEntry::add(OutputSection *Sec) { p_align = std::max(p_align, Sec->Alignment); if (p_type == PT_LOAD) Sec->PtLoad = this; + if (Sec->LMAExpr) + ASectionHasLMA = true; } // The beginning and the ending of .rel[a].plt section are marked @@ -1626,7 +1628,9 @@ template std::vector Writer< // different flags or is loaded at a discontiguous address using AT linker // script command. uint64_t NewFlags = computeFlags(Sec->getPhdrFlags()); - if (Sec->LMAExpr || Flags != NewFlags) { + if ((Sec->LMAExpr && Load->ASectionHasLMA) || + Sec->MemRegion != Load->FirstSec->MemRegion || Flags != NewFlags) { + Load = AddHdr(PT_LOAD, NewFlags); Flags = NewFlags; } Modified: vendor/lld/dist-release_60/ELF/Writer.h ============================================================================== --- vendor/lld/dist-release_60/ELF/Writer.h Thu Feb 1 21:14:31 2018 (r328744) +++ vendor/lld/dist-release_60/ELF/Writer.h Thu Feb 1 21:14:34 2018 (r328745) @@ -44,6 +44,13 @@ struct PhdrEntry { OutputSection *FirstSec = nullptr; OutputSection *LastSec = nullptr; bool HasLMA = false; + + // True if one of the sections in this program header has a LMA specified via + // linker script: AT(addr). We never allow 2 or more sections with LMA in the + // same program header. + bool ASectionHasLMA = false; + + uint64_t LMAOffset = 0; }; void addReservedSymbols(); Added: vendor/lld/dist-release_60/test/ELF/linkerscript/at3.s ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/lld/dist-release_60/test/ELF/linkerscript/at3.s Thu Feb 1 21:14:34 2018 (r328745) @@ -0,0 +1,38 @@ +# REQUIRES: x86 +# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o +# RUN: echo "MEMORY { \ +# RUN: FOO (ax) : ORIGIN = 0x1000, LENGTH = 0x100 \ +# RUN: BAR (ax) : ORIGIN = 0x2000, LENGTH = 0x100 \ +# RUN: ZED (ax) : ORIGIN = 0x3000, LENGTH = 0x100 \ +# RUN: FLASH (ax) : ORIGIN = 0x6000, LENGTH = 0x200 \ +# RUN: } \ +# RUN: SECTIONS { \ +# RUN: .foo1 : { *(.foo1) } > FOO AT>FLASH \ +# RUN: .foo2 : { *(.foo2) BYTE(0x42) } > BAR AT>FLASH \ +# RUN: .foo3 : { *(.foo3) } > ZED AT>FLASH \ +# RUN: }" > %t.script +# RUN: ld.lld %t.o --script %t.script -o %t +# RUN: llvm-readelf -sections -program-headers %t | FileCheck %s + +# CHECK: .foo1 PROGBITS 0000000000001000 001000 +# CHECK: .foo2 PROGBITS 0000000000002000 002000 +# CHECK: .foo3 PROGBITS 0000000000003000 003000 + +# CHECK: Program Headers: +# CHECK-NOT: LOAD + +# CHECK: Type Offset VirtAddr PhysAddr +# CHECK-NEXT: LOAD 0x001000 0x0000000000001000 0x0000000000006000 +# CHECK-NEXT: LOAD 0x002000 0x0000000000002000 0x0000000000006008 +# CHECK-NEXT: LOAD 0x003000 0x0000000000003000 0x0000000000006011 + +# CHECK-NOT: LOAD + +.section .foo1, "a" +.quad 0 + +.section .foo2, "ax" +.quad 0 + +.section .foo3, "ax" +.quad 0 Added: vendor/lld/dist-release_60/test/ELF/linkerscript/merge-header-load.s ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/lld/dist-release_60/test/ELF/linkerscript/merge-header-load.s Thu Feb 1 21:14:34 2018 (r328745) @@ -0,0 +1,21 @@ +# REQUIRES: x86 +# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o +# RUN: echo "SECTIONS { \ +# RUN: . = 0xffffffff80000200; \ +# RUN: .text : AT (0x4200) { *(.text) } \ +# RUN: }" > %t.script +# RUN: ld.lld %t.o --script %t.script -o %t +# RUN: llvm-readelf -program-headers %t | FileCheck %s + +# Test that we put the header in the first PT_LOAD. We used to create a PT_LOAD +# just for it and it would have a different virtual to physical address delta. + +# CHECK: Program Headers: +# CHECK: Type Offset VirtAddr PhysAddr +# CHECK-NEXT: PHDR 0x000040 0xffffffff80000040 0x0000000000004040 +# CHECK-NEXT: LOAD 0x000000 0xffffffff80000000 0x0000000000004000 +# CHECK-NOT: LOAD + +.global _start +_start: +nop From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:14:45 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E87E9ECA075; Thu, 1 Feb 2018 21:14:44 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id BB3F387053; Thu, 1 Feb 2018 21:14:40 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 8C20A1268C; Thu, 1 Feb 2018 21:14:40 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11LEee2078946; Thu, 1 Feb 2018 21:14:40 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11LEeGN078945; Thu, 1 Feb 2018 21:14:40 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012114.w11LEeGN078945@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:14:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328746 - vendor/lld/lld-release_60-r323948 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lld/lld-release_60-r323948 X-SVN-Commit-Revision: 328746 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:14:45 -0000 Author: dim Date: Thu Feb 1 21:14:40 2018 New Revision: 328746 URL: https://svnweb.freebsd.org/changeset/base/328746 Log: Tag lld release_60 branch r323948. Added: vendor/lld/lld-release_60-r323948/ - copied from r328745, vendor/lld/dist-release_60/ From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:14:50 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 3BDD7ECA0AE; Thu, 1 Feb 2018 21:14:50 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 749B187161; Thu, 1 Feb 2018 21:14:45 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id D57D61268D; Thu, 1 Feb 2018 21:14:44 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11LEiT4078994; Thu, 1 Feb 2018 21:14:44 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11LEie2078993; Thu, 1 Feb 2018 21:14:44 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012114.w11LEie2078993@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:14:44 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328747 - vendor/lldb/lldb-release_60-r323948 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lldb/lldb-release_60-r323948 X-SVN-Commit-Revision: 328747 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:14:50 -0000 Author: dim Date: Thu Feb 1 21:14:44 2018 New Revision: 328747 URL: https://svnweb.freebsd.org/changeset/base/328747 Log: Tag lldb release_60 branch r323948. Added: vendor/lldb/lldb-release_60-r323948/ - copied from r328746, vendor/lldb/dist-release_60/ From owner-svn-src-vendor@freebsd.org Fri Feb 2 17:07:57 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1C36CEE42EA; Fri, 2 Feb 2018 17:07:57 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id A8D0A747E3; Fri, 2 Feb 2018 17:07:56 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id A30971E801; Fri, 2 Feb 2018 17:07:56 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w12H7uWu080142; Fri, 2 Feb 2018 17:07:56 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w12H7rKg080110; Fri, 2 Feb 2018 17:07:53 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802021707.w12H7rKg080110@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Fri, 2 Feb 2018 17:07:53 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328786 - in vendor/llvm/dist-release_60: include/llvm include/llvm/CodeGen lib/CodeGen lib/CodeGen/SelectionDAG lib/Target/AMDGPU lib/Target/ARM lib/Target/Mips lib/Target/Sparc lib/Ta... X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/llvm/dist-release_60: include/llvm include/llvm/CodeGen lib/CodeGen lib/CodeGen/SelectionDAG lib/Target/AMDGPU lib/Target/ARM lib/Target/Mips lib/Target/Sparc lib/Target/X86 lib/Transforms/S... X-SVN-Commit-Revision: 328786 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 17:07:57 -0000 Author: dim Date: Fri Feb 2 17:07:53 2018 New Revision: 328786 URL: https://svnweb.freebsd.org/changeset/base/328786 Log: Vendor import of llvm release_60 branch r324090: https://llvm.org/svn/llvm-project/llvm/branches/release_60@324090 Added: vendor/llvm/dist-release_60/lib/CodeGen/IndirectBrExpandPass.cpp (contents, props changed) vendor/llvm/dist-release_60/lib/Target/X86/X86RetpolineThunks.cpp (contents, props changed) vendor/llvm/dist-release_60/test/CodeGen/Mips/pr36061.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/unsized-global.ll vendor/llvm/dist-release_60/test/CodeGen/Thumb/pr35836.ll vendor/llvm/dist-release_60/test/CodeGen/Thumb/pr35836_2.ll vendor/llvm/dist-release_60/test/CodeGen/X86/retpoline-external.ll vendor/llvm/dist-release_60/test/CodeGen/X86/retpoline.ll vendor/llvm/dist-release_60/test/Transforms/IndirectBrExpand/ vendor/llvm/dist-release_60/test/Transforms/IndirectBrExpand/basic.ll Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/Passes.h vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetLowering.h vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetPassConfig.h vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetSubtargetInfo.h vendor/llvm/dist-release_60/include/llvm/InitializePasses.h vendor/llvm/dist-release_60/lib/CodeGen/CMakeLists.txt vendor/llvm/dist-release_60/lib/CodeGen/CodeGen.cpp vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp vendor/llvm/dist-release_60/lib/CodeGen/TargetSubtargetInfo.cpp vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/ARM/Thumb1InstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/ARM/Thumb1InstrInfo.h vendor/llvm/dist-release_60/lib/Target/Mips/MipsISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsTargetObjectFile.cpp vendor/llvm/dist-release_60/lib/Target/Sparc/SparcFrameLowering.cpp vendor/llvm/dist-release_60/lib/Target/X86/CMakeLists.txt vendor/llvm/dist-release_60/lib/Target/X86/X86.h vendor/llvm/dist-release_60/lib/Target/X86/X86.td vendor/llvm/dist-release_60/lib/Target/X86/X86AsmPrinter.h vendor/llvm/dist-release_60/lib/Target/X86/X86FastISel.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86FrameLowering.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86ISelDAGToDAG.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.h vendor/llvm/dist-release_60/lib/Target/X86/X86InstrCompiler.td vendor/llvm/dist-release_60/lib/Target/X86/X86InstrControl.td vendor/llvm/dist-release_60/lib/Target/X86/X86InstrInfo.td vendor/llvm/dist-release_60/lib/Target/X86/X86MCInstLower.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86Subtarget.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86Subtarget.h vendor/llvm/dist-release_60/lib/Target/X86/X86TargetMachine.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/DeadStoreElimination.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp vendor/llvm/dist-release_60/test/CodeGen/AMDGPU/smrd.ll vendor/llvm/dist-release_60/test/CodeGen/SPARC/stack-align.ll vendor/llvm/dist-release_60/test/CodeGen/X86/O0-pipeline.ll vendor/llvm/dist-release_60/test/Transforms/DeadStoreElimination/merge-stores.ll vendor/llvm/dist-release_60/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll vendor/llvm/dist-release_60/tools/opt/opt.cpp Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/Passes.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/CodeGen/Passes.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/include/llvm/CodeGen/Passes.h Fri Feb 2 17:07:53 2018 (r328786) @@ -417,6 +417,9 @@ namespace llvm { // This pass expands memcmp() to load/stores. FunctionPass *createExpandMemCmpPass(); + // This pass expands indirectbr instructions. + FunctionPass *createIndirectBrExpandPass(); + } // End llvm namespace #endif Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h Fri Feb 2 17:07:53 2018 (r328786) @@ -950,6 +950,10 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// Return true when a target supports MachineCombiner. virtual bool useMachineCombiner() const { return false; } + /// Return true if the given SDNode can be copied during scheduling + /// even if it has glue. + virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; } + protected: /// Target-dependent implementation for foldMemoryOperand. /// Target-independent code in foldMemoryOperand will Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetLowering.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetLowering.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetLowering.h Fri Feb 2 17:07:53 2018 (r328786) @@ -800,7 +800,7 @@ class TargetLoweringBase { (public) } /// Return true if lowering to a jump table is allowed. - bool areJTsAllowed(const Function *Fn) const { + virtual bool areJTsAllowed(const Function *Fn) const { if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true") return false; Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetPassConfig.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetPassConfig.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetPassConfig.h Fri Feb 2 17:07:53 2018 (r328786) @@ -416,6 +416,13 @@ class TargetPassConfig : public ImmutablePass { (prote /// immediately before machine code is emitted. virtual void addPreEmitPass() { } + /// Targets may add passes immediately before machine code is emitted in this + /// callback. This is called even later than `addPreEmitPass`. + // FIXME: Rename `addPreEmitPass` to something more sensible given its actual + // position and remove the `2` suffix here as this callback is what + // `addPreEmitPass` *should* be but in reality isn't. + virtual void addPreEmitPass2() {} + /// Utilities for targets to add passes to the pass manager. /// Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetSubtargetInfo.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetSubtargetInfo.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetSubtargetInfo.h Fri Feb 2 17:07:53 2018 (r328786) @@ -174,6 +174,9 @@ class TargetSubtargetInfo : public MCSubtargetInfo { ( /// \brief True if the subtarget should run the atomic expansion pass. virtual bool enableAtomicExpand() const; + /// True if the subtarget should run the indirectbr expansion pass. + virtual bool enableIndirectBrExpand() const; + /// \brief Override generic scheduling policy within a region. /// /// This is a convenient way for targets that don't provide any custom Modified: vendor/llvm/dist-release_60/include/llvm/InitializePasses.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/InitializePasses.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/include/llvm/InitializePasses.h Fri Feb 2 17:07:53 2018 (r328786) @@ -161,6 +161,7 @@ void initializeIVUsersWrapperPassPass(PassRegistry&); void initializeIfConverterPass(PassRegistry&); void initializeImplicitNullChecksPass(PassRegistry&); void initializeIndVarSimplifyLegacyPassPass(PassRegistry&); +void initializeIndirectBrExpandPassPass(PassRegistry&); void initializeInductiveRangeCheckEliminationPass(PassRegistry&); void initializeInferAddressSpacesPass(PassRegistry&); void initializeInferFunctionAttrsLegacyPassPass(PassRegistry&); Modified: vendor/llvm/dist-release_60/lib/CodeGen/CMakeLists.txt ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/CMakeLists.txt Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/CodeGen/CMakeLists.txt Fri Feb 2 17:07:53 2018 (r328786) @@ -33,6 +33,7 @@ add_llvm_library(LLVMCodeGen GlobalMerge.cpp IfConversion.cpp ImplicitNullChecks.cpp + IndirectBrExpandPass.cpp InlineSpiller.cpp InterferenceCache.cpp InterleavedAccessPass.cpp Modified: vendor/llvm/dist-release_60/lib/CodeGen/CodeGen.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/CodeGen.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/CodeGen/CodeGen.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -38,6 +38,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeGCModuleInfoPass(Registry); initializeIfConverterPass(Registry); initializeImplicitNullChecksPass(Registry); + initializeIndirectBrExpandPassPass(Registry); initializeInterleavedAccessPass(Registry); initializeLiveDebugValuesPass(Registry); initializeLiveDebugVariablesPass(Registry); Added: vendor/llvm/dist-release_60/lib/CodeGen/IndirectBrExpandPass.cpp ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_60/lib/CodeGen/IndirectBrExpandPass.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -0,0 +1,221 @@ +//===- IndirectBrExpandPass.cpp - Expand indirectbr to switch -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// +/// Implements an expansion pass to turn `indirectbr` instructions in the IR +/// into `switch` instructions. This works by enumerating the basic blocks in +/// a dense range of integers, replacing each `blockaddr` constant with the +/// corresponding integer constant, and then building a switch that maps from +/// the integers to the actual blocks. All of the indirectbr instructions in the +/// function are redirected to this common switch. +/// +/// While this is generically useful if a target is unable to codegen +/// `indirectbr` natively, it is primarily useful when there is some desire to +/// get the builtin non-jump-table lowering of a switch even when the input +/// source contained an explicit indirect branch construct. +/// +/// Note that it doesn't make any sense to enable this pass unless a target also +/// disables jump-table lowering of switches. Doing that is likely to pessimize +/// the code. +/// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/Sequence.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" +#include "llvm/IR/BasicBlock.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/InstIterator.h" +#include "llvm/IR/Instruction.h" +#include "llvm/IR/Instructions.h" +#include "llvm/Pass.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" + +using namespace llvm; + +#define DEBUG_TYPE "indirectbr-expand" + +namespace { + +class IndirectBrExpandPass : public FunctionPass { + const TargetLowering *TLI = nullptr; + +public: + static char ID; // Pass identification, replacement for typeid + + IndirectBrExpandPass() : FunctionPass(ID) { + initializeIndirectBrExpandPassPass(*PassRegistry::getPassRegistry()); + } + + bool runOnFunction(Function &F) override; +}; + +} // end anonymous namespace + +char IndirectBrExpandPass::ID = 0; + +INITIALIZE_PASS(IndirectBrExpandPass, DEBUG_TYPE, + "Expand indirectbr instructions", false, false) + +FunctionPass *llvm::createIndirectBrExpandPass() { + return new IndirectBrExpandPass(); +} + +bool IndirectBrExpandPass::runOnFunction(Function &F) { + auto &DL = F.getParent()->getDataLayout(); + auto *TPC = getAnalysisIfAvailable(); + if (!TPC) + return false; + + auto &TM = TPC->getTM(); + auto &STI = *TM.getSubtargetImpl(F); + if (!STI.enableIndirectBrExpand()) + return false; + TLI = STI.getTargetLowering(); + + SmallVector IndirectBrs; + + // Set of all potential successors for indirectbr instructions. + SmallPtrSet IndirectBrSuccs; + + // Build a list of indirectbrs that we want to rewrite. + for (BasicBlock &BB : F) + if (auto *IBr = dyn_cast(BB.getTerminator())) { + // Handle the degenerate case of no successors by replacing the indirectbr + // with unreachable as there is no successor available. + if (IBr->getNumSuccessors() == 0) { + (void)new UnreachableInst(F.getContext(), IBr); + IBr->eraseFromParent(); + continue; + } + + IndirectBrs.push_back(IBr); + for (BasicBlock *SuccBB : IBr->successors()) + IndirectBrSuccs.insert(SuccBB); + } + + if (IndirectBrs.empty()) + return false; + + // If we need to replace any indirectbrs we need to establish integer + // constants that will correspond to each of the basic blocks in the function + // whose address escapes. We do that here and rewrite all the blockaddress + // constants to just be those integer constants cast to a pointer type. + SmallVector BBs; + + for (BasicBlock &BB : F) { + // Skip blocks that aren't successors to an indirectbr we're going to + // rewrite. + if (!IndirectBrSuccs.count(&BB)) + continue; + + auto IsBlockAddressUse = [&](const Use &U) { + return isa(U.getUser()); + }; + auto BlockAddressUseIt = llvm::find_if(BB.uses(), IsBlockAddressUse); + if (BlockAddressUseIt == BB.use_end()) + continue; + + assert(std::find_if(std::next(BlockAddressUseIt), BB.use_end(), + IsBlockAddressUse) == BB.use_end() && + "There should only ever be a single blockaddress use because it is " + "a constant and should be uniqued."); + + auto *BA = cast(BlockAddressUseIt->getUser()); + + // Skip if the constant was formed but ended up not being used (due to DCE + // or whatever). + if (!BA->isConstantUsed()) + continue; + + // Compute the index we want to use for this basic block. We can't use zero + // because null can be compared with block addresses. + int BBIndex = BBs.size() + 1; + BBs.push_back(&BB); + + auto *ITy = cast(DL.getIntPtrType(BA->getType())); + ConstantInt *BBIndexC = ConstantInt::get(ITy, BBIndex); + + // Now rewrite the blockaddress to an integer constant based on the index. + // FIXME: We could potentially preserve the uses as arguments to inline asm. + // This would allow some uses such as diagnostic information in crashes to + // have higher quality even when this transform is enabled, but would break + // users that round-trip blockaddresses through inline assembly and then + // back into an indirectbr. + BA->replaceAllUsesWith(ConstantExpr::getIntToPtr(BBIndexC, BA->getType())); + } + + if (BBs.empty()) { + // There are no blocks whose address is taken, so any indirectbr instruction + // cannot get a valid input and we can replace all of them with unreachable. + for (auto *IBr : IndirectBrs) { + (void)new UnreachableInst(F.getContext(), IBr); + IBr->eraseFromParent(); + } + return true; + } + + BasicBlock *SwitchBB; + Value *SwitchValue; + + // Compute a common integer type across all the indirectbr instructions. + IntegerType *CommonITy = nullptr; + for (auto *IBr : IndirectBrs) { + auto *ITy = + cast(DL.getIntPtrType(IBr->getAddress()->getType())); + if (!CommonITy || ITy->getBitWidth() > CommonITy->getBitWidth()) + CommonITy = ITy; + } + + auto GetSwitchValue = [DL, CommonITy](IndirectBrInst *IBr) { + return CastInst::CreatePointerCast( + IBr->getAddress(), CommonITy, + Twine(IBr->getAddress()->getName()) + ".switch_cast", IBr); + }; + + if (IndirectBrs.size() == 1) { + // If we only have one indirectbr, we can just directly replace it within + // its block. + SwitchBB = IndirectBrs[0]->getParent(); + SwitchValue = GetSwitchValue(IndirectBrs[0]); + IndirectBrs[0]->eraseFromParent(); + } else { + // Otherwise we need to create a new block to hold the switch across BBs, + // jump to that block instead of each indirectbr, and phi together the + // values for the switch. + SwitchBB = BasicBlock::Create(F.getContext(), "switch_bb", &F); + auto *SwitchPN = PHINode::Create(CommonITy, IndirectBrs.size(), + "switch_value_phi", SwitchBB); + SwitchValue = SwitchPN; + + // Now replace the indirectbr instructions with direct branches to the + // switch block and fill out the PHI operands. + for (auto *IBr : IndirectBrs) { + SwitchPN->addIncoming(GetSwitchValue(IBr), IBr->getParent()); + BranchInst::Create(SwitchBB, IBr); + IBr->eraseFromParent(); + } + } + + // Now build the switch in the block. The block will have no terminator + // already. + auto *SI = SwitchInst::Create(SwitchValue, BBs[0], BBs.size(), SwitchBB); + + // Add a case for each block. + for (int i : llvm::seq(1, BBs.size())) + SI->addCase(ConstantInt::get(CommonITy, i + 1), BBs[i]); + + return true; +} Modified: vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -1996,14 +1996,15 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Lib Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); Entry.Node = Op; Entry.Ty = ArgTy; - Entry.IsSExt = isSigned; - Entry.IsZExt = !isSigned; + Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned); + Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned); Args.push_back(Entry); } SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), TLI.getPointerTy(DAG.getDataLayout())); - Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); + EVT RetVT = Node->getValueType(0); + Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); // By default, the input chain to this libcall is the entry node of the // function. If the libcall is going to be emitted as a tail call then @@ -2022,13 +2023,14 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Lib InChain = TCChain; TargetLowering::CallLoweringInfo CLI(DAG); + bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned); CLI.setDebugLoc(SDLoc(Node)) .setChain(InChain) .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) .setTailCall(isTailCall) - .setSExtResult(isSigned) - .setZExtResult(!isSigned) + .setSExtResult(signExtend) + .setZExtResult(!signExtend) .setIsPostTypeLegalization(true); std::pair CallInfo = TLI.LowerCallTo(CLI); Modified: vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -1117,22 +1117,34 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit if (!N) return nullptr; - if (SU->getNode()->getGluedNode()) + DEBUG(dbgs() << "Considering duplicating the SU\n"); + DEBUG(SU->dump(this)); + + if (N->getGluedNode() && + !TII->canCopyGluedNodeDuringSchedule(N)) { + DEBUG(dbgs() + << "Giving up because it has incoming glue and the target does not " + "want to copy it\n"); return nullptr; + } SUnit *NewSU; bool TryUnfold = false; for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { MVT VT = N->getSimpleValueType(i); - if (VT == MVT::Glue) + if (VT == MVT::Glue) { + DEBUG(dbgs() << "Giving up because it has outgoing glue\n"); return nullptr; - else if (VT == MVT::Other) + } else if (VT == MVT::Other) TryUnfold = true; } for (const SDValue &Op : N->op_values()) { MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); - if (VT == MVT::Glue) + if (VT == MVT::Glue && !TII->canCopyGluedNodeDuringSchedule(N)) { + DEBUG(dbgs() << "Giving up because it one of the operands is glue and " + "the target does not want to copy it\n"); return nullptr; + } } // If possible unfold instruction. Modified: vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -907,6 +907,9 @@ void TargetPassConfig::addMachinePasses() { if (EnableMachineOutliner) PM->add(createMachineOutlinerPass(EnableLinkOnceODROutlining)); + // Add passes that directly emit MI after all other MI passes. + addPreEmitPass2(); + AddingMachinePasses = false; } Modified: vendor/llvm/dist-release_60/lib/CodeGen/TargetSubtargetInfo.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/TargetSubtargetInfo.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/CodeGen/TargetSubtargetInfo.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -38,6 +38,10 @@ bool TargetSubtargetInfo::enableAtomicExpand() const { return true; } +bool TargetSubtargetInfo::enableIndirectBrExpand() const { + return false; +} + bool TargetSubtargetInfo::enableMachineScheduler() const { return false; } Modified: vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstrInfo.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstrInfo.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstrInfo.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -3756,36 +3756,45 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) co // FIXME: This isn't safe because the addressing mode doesn't work // correctly if vaddr is negative. // - // FIXME: Handle v_add_u32 and VOP3 form. Also don't rely on immediate - // being in src0. - // // FIXME: Should probably be done somewhere else, maybe SIFoldOperands. // // See if we can extract an immediate offset by recognizing one of these: // V_ADD_I32_e32 dst, imm, src1 // V_ADD_I32_e32 dst, (S_MOV_B32 imm), src1 // V_ADD will be removed by "Remove dead machine instructions". - if (Add && Add->getOpcode() == AMDGPU::V_ADD_I32_e32) { - const MachineOperand *Src = - getNamedOperand(*Add, AMDGPU::OpName::src0); + if (Add && + (Add->getOpcode() == AMDGPU::V_ADD_I32_e32 || + Add->getOpcode() == AMDGPU::V_ADD_U32_e64)) { + static const unsigned SrcNames[2] = { + AMDGPU::OpName::src0, + AMDGPU::OpName::src1, + }; - if (Src->isReg()) { - auto Mov = MRI.getUniqueVRegDef(Src->getReg()); - if (Mov && Mov->getOpcode() == AMDGPU::S_MOV_B32) - Src = &Mov->getOperand(1); - } + // Find a literal offset in one of source operands. + for (int i = 0; i < 2; i++) { + const MachineOperand *Src = + getNamedOperand(*Add, SrcNames[i]); - if (Src) { - if (Src->isImm()) - Offset = Src->getImm(); - else if (Src->isCImm()) - Offset = Src->getCImm()->getZExtValue(); - } + if (Src->isReg()) { + auto Mov = MRI.getUniqueVRegDef(Src->getReg()); + if (Mov && Mov->getOpcode() == AMDGPU::S_MOV_B32) + Src = &Mov->getOperand(1); + } - if (Offset && isLegalMUBUFImmOffset(Offset)) - VAddr = getNamedOperand(*Add, AMDGPU::OpName::src1); - else + if (Src) { + if (Src->isImm()) + Offset = Src->getImm(); + else if (Src->isCImm()) + Offset = Src->getCImm()->getZExtValue(); + } + + if (Offset && isLegalMUBUFImmOffset(Offset)) { + VAddr = getNamedOperand(*Add, SrcNames[!i]); + break; + } + Offset = 0; + } } BuildMI(*MBB, Inst, Inst.getDebugLoc(), Modified: vendor/llvm/dist-release_60/lib/Target/ARM/Thumb1InstrInfo.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/ARM/Thumb1InstrInfo.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/ARM/Thumb1InstrInfo.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -141,3 +141,16 @@ void Thumb1InstrInfo::expandLoadStackGuard( else expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi); } + +bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const { + // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR + // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS + // even if they have glue. + // FIXME. Actually implement the cross-copy where it is possible (post v6) + // because these copies entail more spilling. + unsigned Opcode = N->getMachineOpcode(); + if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS) + return true; + + return false; +} Modified: vendor/llvm/dist-release_60/lib/Target/ARM/Thumb1InstrInfo.h ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/ARM/Thumb1InstrInfo.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/ARM/Thumb1InstrInfo.h Fri Feb 2 17:07:53 2018 (r328786) @@ -53,6 +53,7 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo { (pub const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; + bool canCopyGluedNodeDuringSchedule(SDNode *N) const override; private: void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override; }; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/MipsISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/MipsISelLowering.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/Mips/MipsISelLowering.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -3507,10 +3507,9 @@ MipsTargetLowering::CanLowerReturn(CallingConv::ID Cal bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { - if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { - if (Type == MVT::i32) + if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) return true; - } + return IsSigned; } Modified: vendor/llvm/dist-release_60/lib/Target/Mips/MipsTargetObjectFile.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/MipsTargetObjectFile.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/Mips/MipsTargetObjectFile.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -136,6 +136,13 @@ IsGlobalInSmallSectionImpl(const GlobalObject *GO, return false; Type *Ty = GVA->getValueType(); + + // It is possible that the type of the global is unsized, i.e. a declaration + // of a extern struct. In this case don't presume it is in the small data + // section. This happens e.g. when building the FreeBSD kernel. + if (!Ty->isSized()) + return false; + return IsInSmallSection( GVA->getParent()->getDataLayout().getTypeAllocSize(Ty)); } Modified: vendor/llvm/dist-release_60/lib/Target/Sparc/SparcFrameLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Sparc/SparcFrameLowering.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/Sparc/SparcFrameLowering.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -88,10 +88,11 @@ void SparcFrameLowering::emitPrologue(MachineFunction assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); MachineFrameInfo &MFI = MF.getFrameInfo(); + const SparcSubtarget &Subtarget = MF.getSubtarget(); const SparcInstrInfo &TII = - *static_cast(MF.getSubtarget().getInstrInfo()); + *static_cast(Subtarget.getInstrInfo()); const SparcRegisterInfo &RegInfo = - *static_cast(MF.getSubtarget().getRegisterInfo()); + *static_cast(Subtarget.getRegisterInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); // Debug location must be unknown since the first debug location is used // to determine the end of the prologue. @@ -141,7 +142,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction // Adds the SPARC subtarget-specific spill area to the stack // size. Also ensures target-required alignment. - NumBytes = MF.getSubtarget().getAdjustedFrameSize(NumBytes); + NumBytes = Subtarget.getAdjustedFrameSize(NumBytes); // Finally, ensure that the size is sufficiently aligned for the // data on the stack. @@ -176,9 +177,27 @@ void SparcFrameLowering::emitPrologue(MachineFunction .addCFIIndex(CFIIndex); if (NeedsStackRealignment) { - // andn %o6, MaxAlign-1, %o6 + int64_t Bias = Subtarget.getStackPointerBias(); + unsigned regUnbiased; + if (Bias) { + // This clobbers G1 which we always know is available here. + regUnbiased = SP::G1; + // add %o6, BIAS, %g1 + BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased) + .addReg(SP::O6).addImm(Bias); + } else + regUnbiased = SP::O6; + + // andn %regUnbiased, MaxAlign-1, %regUnbiased int MaxAlign = MFI.getMaxAlignment(); - BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), SP::O6).addReg(SP::O6).addImm(MaxAlign - 1); + BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased) + .addReg(regUnbiased).addImm(MaxAlign - 1); + + if (Bias) { + // add %g1, -BIAS, %o6 + BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6) + .addReg(regUnbiased).addImm(-Bias); + } } } Modified: vendor/llvm/dist-release_60/lib/Target/X86/CMakeLists.txt ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/CMakeLists.txt Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/CMakeLists.txt Fri Feb 2 17:07:53 2018 (r328786) @@ -48,6 +48,7 @@ set(sources X86PadShortFunction.cpp X86RegisterBankInfo.cpp X86RegisterInfo.cpp + X86RetpolineThunks.cpp X86SelectionDAGInfo.cpp X86ShuffleDecodeConstantPool.cpp X86Subtarget.cpp Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86.h ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86.h Fri Feb 2 17:07:53 2018 (r328786) @@ -22,6 +22,7 @@ namespace llvm { class FunctionPass; class ImmutablePass; class InstructionSelector; +class ModulePass; class PassRegistry; class X86RegisterBankInfo; class X86Subtarget; @@ -101,6 +102,9 @@ void initializeFixupBWInstPassPass(PassRegistry &); /// This pass replaces EVEX encoded of AVX-512 instructiosn by VEX /// encoding when possible in order to reduce code size. FunctionPass *createX86EvexToVexInsts(); + +/// This pass creates the thunks for the retpoline feature. +FunctionPass *createX86RetpolineThunksPass(); InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM, X86Subtarget &, Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86.td Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86.td Fri Feb 2 17:07:53 2018 (r328786) @@ -329,6 +329,27 @@ def FeatureHasFastGather : SubtargetFeature<"fast-gather", "HasFastGather", "true", "Indicates if gather is reasonably fast.">; +// Enable mitigation of some aspects of speculative execution related +// vulnerabilities by removing speculatable indirect branches. This disables +// jump-table formation, rewrites explicit `indirectbr` instructions into +// `switch` instructions, and uses a special construct called a "retpoline" to +// prevent speculation of the remaining indirect branches (indirect calls and +// tail calls). +def FeatureRetpoline + : SubtargetFeature<"retpoline", "UseRetpoline", "true", + "Remove speculation of indirect branches from the " + "generated code, either by avoiding them entirely or " + "lowering them with a speculation blocking construct.">; + +// Rely on external thunks for the emitted retpoline calls. This allows users +// to provide their own custom thunk definitions in highly specialized +// environments such as a kernel that does boot-time hot patching. +def FeatureRetpolineExternalThunk + : SubtargetFeature< + "retpoline-external-thunk", "UseRetpolineExternalThunk", "true", + "Enable retpoline, but with an externally provided thunk.", + [FeatureRetpoline]>; + //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86AsmPrinter.h ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86AsmPrinter.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86AsmPrinter.h Fri Feb 2 17:07:53 2018 (r328786) @@ -32,6 +32,7 @@ class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public A FaultMaps FM; std::unique_ptr CodeEmitter; bool EmitFPOData = false; + bool NeedsRetpoline = false; // This utility class tracks the length of a stackmap instruction's 'shadow'. // It is used by the X86AsmPrinter to ensure that the stackmap shadow Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86FastISel.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86FastISel.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86FastISel.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -3172,6 +3172,10 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) (CalledFn && CalledFn->hasFnAttribute("no_caller_saved_registers"))) return false; + // Functions using retpoline should use SDISel for calls. + if (Subtarget->useRetpoline()) + return false; + // Handle only C, fastcc, and webkit_js calling conventions for now. switch (CC) { default: return false; Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86FrameLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86FrameLowering.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86FrameLowering.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -741,6 +741,11 @@ void X86FrameLowering::emitStackProbeCall(MachineFunct bool InProlog) const { bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large; + // FIXME: Add retpoline support and remove this. + if (Is64Bit && IsLargeCodeModel && STI.useRetpoline()) + report_fatal_error("Emitting stack probe calls on 64-bit with the large " + "code model and retpoline not yet implemented."); + unsigned CallOp; if (Is64Bit) CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32; @@ -2345,6 +2350,10 @@ void X86FrameLowering::adjustForSegmentedStacks( // This solution is not perfect, as it assumes that the .rodata section // is laid out within 2^31 bytes of each function body, but this seems // to be sufficient for JIT. + // FIXME: Add retpoline support and remove the error here.. + if (STI.useRetpoline()) + report_fatal_error("Emitting morestack calls on 64-bit with the large " + "code model and retpoline not yet implemented."); BuildMI(allocMBB, DL, TII.get(X86::CALL64m)) .addReg(X86::RIP) .addImm(0) Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86ISelDAGToDAG.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -629,11 +629,11 @@ void X86DAGToDAGISel::PreprocessISelDAG() { SDNode *N = &*I++; // Preincrement iterator to avoid invalidation issues. if (OptLevel != CodeGenOpt::None && - // Only does this when target favors doesn't favor register indirect - // call. + // Only do this when the target can fold the load into the call or + // jmp. + !Subtarget->useRetpoline() && ((N->getOpcode() == X86ISD::CALL && !Subtarget->slowTwoMemOps()) || (N->getOpcode() == X86ISD::TC_RETURN && - // Only does this if load can be folded into TC_RETURN. (Subtarget->is64Bit() || !getTargetMachine().isPositionIndependent())))) { /// Also try moving call address load from outside callseq_start to just Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp Fri Feb 2 17:07:53 2018 (r328786) @@ -25767,6 +25767,15 @@ X86TargetLowering::isVectorClearMaskLegal(const SmallV return isShuffleMaskLegal(Mask, VT); } +bool X86TargetLowering::areJTsAllowed(const Function *Fn) const { + // If the subtarget is using retpolines, we need to not generate jump tables. + if (Subtarget.useRetpoline()) + return false; + + // Otherwise, fallback on the generic logic. + return TargetLowering::areJTsAllowed(Fn); +} + //===----------------------------------------------------------------------===// // X86 Scheduler Hooks //===----------------------------------------------------------------------===// @@ -27069,7 +27078,116 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr &MI return BB; } +static unsigned getOpcodeForRetpoline(unsigned RPOpc) { + switch (RPOpc) { + case X86::RETPOLINE_CALL32: + return X86::CALLpcrel32; + case X86::RETPOLINE_CALL64: + return X86::CALL64pcrel32; + case X86::RETPOLINE_TCRETURN32: + return X86::TCRETURNdi; + case X86::RETPOLINE_TCRETURN64: + return X86::TCRETURNdi64; + } + llvm_unreachable("not retpoline opcode"); +} + +static const char *getRetpolineSymbol(const X86Subtarget &Subtarget, + unsigned Reg) { + switch (Reg) { + case 0: + assert(!Subtarget.is64Bit() && "R11 should always be available on x64"); + return Subtarget.useRetpolineExternalThunk() + ? "__llvm_external_retpoline_push" + : "__llvm_retpoline_push"; + case X86::EAX: + return Subtarget.useRetpolineExternalThunk() + ? "__llvm_external_retpoline_eax" + : "__llvm_retpoline_eax"; + case X86::ECX: + return Subtarget.useRetpolineExternalThunk() + ? "__llvm_external_retpoline_ecx" + : "__llvm_retpoline_ecx"; + case X86::EDX: + return Subtarget.useRetpolineExternalThunk() + ? "__llvm_external_retpoline_edx" + : "__llvm_retpoline_edx"; + case X86::R11: + return Subtarget.useRetpolineExternalThunk() + ? "__llvm_external_retpoline_r11" + : "__llvm_retpoline_r11"; + } + llvm_unreachable("unexpected reg for retpoline"); +} + MachineBasicBlock * +X86TargetLowering::EmitLoweredRetpoline(MachineInstr &MI, + MachineBasicBlock *BB) const { + // Copy the virtual register into the R11 physical register and + // call the retpoline thunk. + DebugLoc DL = MI.getDebugLoc(); + const X86InstrInfo *TII = Subtarget.getInstrInfo(); + unsigned CalleeVReg = MI.getOperand(0).getReg(); + unsigned Opc = getOpcodeForRetpoline(MI.getOpcode()); + + // Find an available scratch register to hold the callee. On 64-bit, we can + // just use R11, but we scan for uses anyway to ensure we don't generate + // incorrect code. On 32-bit, we use one of EAX, ECX, or EDX that isn't + // already a register use operand to the call to hold the callee. If none + // are available, push the callee instead. This is less efficient, but is + // necessary for functions using 3 regparms. Such function calls are + // (currently) not eligible for tail call optimization, because there is no + // scratch register available to hold the address of the callee. + SmallVector AvailableRegs; + if (Subtarget.is64Bit()) + AvailableRegs.push_back(X86::R11); + else + AvailableRegs.append({X86::EAX, X86::ECX, X86::EDX}); + + // Zero out any registers that are already used. + for (const auto &MO : MI.operands()) { + if (MO.isReg() && MO.isUse()) + for (unsigned &Reg : AvailableRegs) + if (Reg == MO.getReg()) + Reg = 0; + } + + // Choose the first remaining non-zero available register. + unsigned AvailableReg = 0; + for (unsigned MaybeReg : AvailableRegs) { + if (MaybeReg) { + AvailableReg = MaybeReg; + break; + } + } + + const char *Symbol = getRetpolineSymbol(Subtarget, AvailableReg); + + if (AvailableReg == 0) { + // No register available. Use PUSH. This must not be a tailcall, and this + // must not be x64. + if (Subtarget.is64Bit()) + report_fatal_error( + "Cannot make an indirect call on x86-64 using both retpoline and a " + "calling convention that preservers r11"); + if (Opc != X86::CALLpcrel32) + report_fatal_error("Cannot make an indirect tail call on x86 using " + "retpoline without a preserved register"); + BuildMI(*BB, MI, DL, TII->get(X86::PUSH32r)).addReg(CalleeVReg); + MI.getOperand(0).ChangeToES(Symbol); + MI.setDesc(TII->get(Opc)); + } else { + BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), AvailableReg) + .addReg(CalleeVReg); + MI.getOperand(0).ChangeToES(Symbol); + MI.setDesc(TII->get(Opc)); + MachineInstrBuilder(*BB->getParent(), &MI) + .addReg(AvailableReg, RegState::Implicit | RegState::Kill); + } + return BB; +} + +MachineBasicBlock * X86TargetLowering::emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const { DebugLoc DL = MI.getDebugLoc(); @@ -27584,6 +27702,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(Machine case X86::TLS_base_addr32: case X86::TLS_base_addr64: return EmitLoweredTLSAddr(MI, BB); + case X86::RETPOLINE_CALL32: + case X86::RETPOLINE_CALL64: + case X86::RETPOLINE_TCRETURN32: + case X86::RETPOLINE_TCRETURN64: + return EmitLoweredRetpoline(MI, BB); case X86::CATCHRET: return EmitLoweredCatchRet(MI, BB); case X86::CATCHPAD: Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.h ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.h Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.h Fri Feb 2 17:07:53 2018 (r328786) @@ -982,6 +982,9 @@ namespace llvm { bool isVectorClearMaskLegal(const SmallVectorImpl &Mask, EVT VT) const override; + /// Returns true if lowering to a jump table is allowed. + bool areJTsAllowed(const Function *Fn) const override; + /// If true, then instruction selection should /// seek to shrink the FP constant of the specified type to a smaller type /// in order to save space and / or reduce runtime. @@ -1293,6 +1296,9 @@ namespace llvm { MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI, MachineBasicBlock *BB) const; + + MachineBasicBlock *EmitLoweredRetpoline(MachineInstr &MI, + MachineBasicBlock *BB) const; MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const; Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86InstrCompiler.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86InstrCompiler.td Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86InstrCompiler.td Fri Feb 2 17:07:53 2018 (r328786) @@ -1146,14 +1146,14 @@ def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, - Requires<[Not64BitMode]>; + Requires<[Not64BitMode, NotUseRetpoline]>; // FIXME: This is disabled for 32-bit PIC mode because the global base // register which is part of the address mode may be assigned a // callee-saved register. def : Pat<(X86tcret (load addr:$dst), imm:$off), (TCRETURNmi addr:$dst, imm:$off)>, - Requires<[Not64BitMode, IsNotPIC]>; + Requires<[Not64BitMode, IsNotPIC, NotUseRetpoline]>; def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), (TCRETURNdi tglobaladdr:$dst, imm:$off)>, @@ -1165,13 +1165,21 @@ def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off) def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode, NotUseRetpoline]>; // Don't fold loads into X86tcret requiring more than 6 regs. // There wouldn't be enough scratch registers for base+index. def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), (TCRETURNmi64 addr:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode, NotUseRetpoline]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (RETPOLINE_TCRETURN64 ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[In64BitMode, UseRetpoline]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (RETPOLINE_TCRETURN32 ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[Not64BitMode, UseRetpoline]>; def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86InstrControl.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86InstrControl.td Fri Feb 2 16:47:32 2018 (r328785) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86InstrControl.td Fri Feb 2 17:07:53 2018 (r328786) @@ -211,11 +211,12 @@ let isCall = 1 in Sched<[WriteJumpLd]>; def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>, - OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>; + OpSize32, Requires<[Not64BitMode,NotUseRetpoline]>, + Sched<[WriteJump]>; def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], IIC_CALL_MEM>, OpSize32, - Requires<[Not64BitMode,FavorMemIndirectCall]>, + Requires<[Not64BitMode,FavorMemIndirectCall,NotUseRetpoline]>, Sched<[WriteJumpLd]>; let Predicates = [Not64BitMode] in { @@ -298,11 +299,12 @@ let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJum def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), "call{q}\t{*}$dst", [(X86call GR64:$dst)], IIC_CALL_RI>, - Requires<[In64BitMode]>; + Requires<[In64BitMode,NotUseRetpoline]>; def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))], IIC_CALL_MEM>, - Requires<[In64BitMode,FavorMemIndirectCall]>; + Requires<[In64BitMode,FavorMemIndirectCall, + NotUseRetpoline]>; def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst), "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>; @@ -338,6 +340,27 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarr let mayLoad = 1 in def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; + } +} + +let isPseudo = 1, isCall = 1, isCodeGenOnly = 1, + Uses = [RSP, SSP], + usesCustomInserter = 1, + SchedRW = [WriteJump] in { + def RETPOLINE_CALL32 : + PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>, + Requires<[Not64BitMode,UseRetpoline]>; + + def RETPOLINE_CALL64 : + PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>, + Requires<[In64BitMode,UseRetpoline]>; + + // Retpoline variant of indirect tail calls. + let isTerminator = 1, isReturn = 1, isBarrier = 1 in { + def RETPOLINE_TCRETURN64 : + PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>; + def RETPOLINE_TCRETURN32 : + PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>; } *** DIFF OUTPUT TRUNCATED AT 1000 LINES *** From owner-svn-src-vendor@freebsd.org Fri Feb 2 17:08:04 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 7DE83EE431C; Fri, 2 Feb 2018 17:08:04 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id A7A167487B; Fri, 2 Feb 2018 17:08:02 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 74FBA1E802; Fri, 2 Feb 2018 17:08:01 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w12H81Na080194; Fri, 2 Feb 2018 17:08:01 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w12H81xu080193; Fri, 2 Feb 2018 17:08:01 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802021708.w12H81xu080193@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Fri, 2 Feb 2018 17:08:01 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328787 - vendor/llvm/llvm-release_60-r324090 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/llvm/llvm-release_60-r324090 X-SVN-Commit-Revision: 328787 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 17:08:04 -0000 Author: dim Date: Fri Feb 2 17:08:01 2018 New Revision: 328787 URL: https://svnweb.freebsd.org/changeset/base/328787 Log: Tag llvm release_60 branch r324090. Added: vendor/llvm/llvm-release_60-r324090/ - copied from r328786, vendor/llvm/dist-release_60/ From owner-svn-src-vendor@freebsd.org Fri Feb 2 17:08:12 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8656AEE434B; Fri, 2 Feb 2018 17:08:12 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D42F9749A1; Fri, 2 Feb 2018 17:08:11 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 249031E803; Fri, 2 Feb 2018 17:08:10 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w12H89o4080247; Fri, 2 Feb 2018 17:08:09 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w12H898x080243; Fri, 2 Feb 2018 17:08:09 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802021708.w12H898x080243@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Fri, 2 Feb 2018 17:08:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328788 - in vendor/clang/dist-release_60: include/clang/Driver lib/Basic/Targets test/Driver X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/clang/dist-release_60: include/clang/Driver lib/Basic/Targets test/Driver X-SVN-Commit-Revision: 328788 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 17:08:12 -0000 Author: dim Date: Fri Feb 2 17:08:09 2018 New Revision: 328788 URL: https://svnweb.freebsd.org/changeset/base/328788 Log: Vendor import of clang release_60 branch r324090: https://llvm.org/svn/llvm-project/cfe/branches/release_60@324090 Modified: vendor/clang/dist-release_60/include/clang/Driver/Options.td vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp vendor/clang/dist-release_60/lib/Basic/Targets/X86.h vendor/clang/dist-release_60/test/Driver/x86-target-features.c Modified: vendor/clang/dist-release_60/include/clang/Driver/Options.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Driver/Options.td Fri Feb 2 17:08:01 2018 (r328787) +++ vendor/clang/dist-release_60/include/clang/Driver/Options.td Fri Feb 2 17:08:09 2018 (r328788) @@ -2583,6 +2583,10 @@ def mshstk : Flag<["-"], "mshstk">, Group, Group; def mibt : Flag<["-"], "mibt">, Group; def mno_ibt : Flag<["-"], "mno-ibt">, Group; +def mretpoline : Flag<["-"], "mretpoline">, Group; +def mno_retpoline : Flag<["-"], "mno-retpoline">, Group; +def mretpoline_external_thunk : Flag<["-"], "mretpoline-external-thunk">, Group; +def mno_retpoline_external_thunk : Flag<["-"], "mno-retpoline-external-thunk">, Group; // These are legacy user-facing driver-level option spellings. They are always // aliases for options that are spelled using the more common Unix / GNU flag Modified: vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp Fri Feb 2 17:08:01 2018 (r328787) +++ vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp Fri Feb 2 17:08:09 2018 (r328788) @@ -763,6 +763,10 @@ bool X86TargetInfo::handleTargetFeatures(std::vector(Feature) @@ -1305,6 +1309,8 @@ bool X86TargetInfo::hasFeature(StringRef Feature) cons .Case("prfchw", HasPRFCHW) .Case("rdrnd", HasRDRND) .Case("rdseed", HasRDSEED) + .Case("retpoline", HasRetpoline) + .Case("retpoline-external-thunk", HasRetpolineExternalThunk) .Case("rtm", HasRTM) .Case("sgx", HasSGX) .Case("sha", HasSHA) Modified: vendor/clang/dist-release_60/lib/Basic/Targets/X86.h ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/X86.h Fri Feb 2 17:08:01 2018 (r328787) +++ vendor/clang/dist-release_60/lib/Basic/Targets/X86.h Fri Feb 2 17:08:09 2018 (r328788) @@ -96,6 +96,8 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public T bool HasCLWB = false; bool HasMOVBE = false; bool HasPREFETCHWT1 = false; + bool HasRetpoline = false; + bool HasRetpolineExternalThunk = false; /// \brief Enumeration of all of the X86 CPUs supported by Clang. /// Modified: vendor/clang/dist-release_60/test/Driver/x86-target-features.c ============================================================================== --- vendor/clang/dist-release_60/test/Driver/x86-target-features.c Fri Feb 2 17:08:01 2018 (r328787) +++ vendor/clang/dist-release_60/test/Driver/x86-target-features.c Fri Feb 2 17:08:09 2018 (r328788) @@ -125,3 +125,12 @@ // VBMI2: "-target-feature" "+avx512vbmi2" // NO-VBMI2: "-target-feature" "-avx512vbmi2" +// RUN: %clang -target i386-linux-gnu -mretpoline %s -### -o %t.o 2>&1 | FileCheck -check-prefix=RETPOLINE %s +// RUN: %clang -target i386-linux-gnu -mno-retpoline %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RETPOLINE %s +// RETPOLINE: "-target-feature" "+retpoline" +// NO-RETPOLINE: "-target-feature" "-retpoline" + +// RUN: %clang -target i386-linux-gnu -mretpoline -mretpoline-external-thunk %s -### -o %t.o 2>&1 | FileCheck -check-prefix=RETPOLINE-EXTERNAL-THUNK %s +// RUN: %clang -target i386-linux-gnu -mretpoline -mno-retpoline-external-thunk %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RETPOLINE-EXTERNAL-THUNK %s +// RETPOLINE-EXTERNAL-THUNK: "-target-feature" "+retpoline-external-thunk" +// NO-RETPOLINE-EXTERNAL-THUNK: "-target-feature" "-retpoline-external-thunk" From owner-svn-src-vendor@freebsd.org Fri Feb 2 17:08:16 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1A3C0EE437D; Fri, 2 Feb 2018 17:08:15 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 5BE2B749AB; Fri, 2 Feb 2018 17:08:13 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 3E9181E804; Fri, 2 Feb 2018 17:08:13 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w12H8Dk5080294; Fri, 2 Feb 2018 17:08:13 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w12H8DHJ080293; Fri, 2 Feb 2018 17:08:13 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802021708.w12H8DHJ080293@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Fri, 2 Feb 2018 17:08:13 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328789 - vendor/clang/clang-release_60-r324090 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/clang/clang-release_60-r324090 X-SVN-Commit-Revision: 328789 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 17:08:16 -0000 Author: dim Date: Fri Feb 2 17:08:12 2018 New Revision: 328789 URL: https://svnweb.freebsd.org/changeset/base/328789 Log: Tag clang release_60 branch r324090. Added: vendor/clang/clang-release_60-r324090/ - copied from r328788, vendor/clang/dist-release_60/ From owner-svn-src-vendor@freebsd.org Fri Feb 2 17:08:21 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 357B7EE43A7; Fri, 2 Feb 2018 17:08:21 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 06F5074A58; Fri, 2 Feb 2018 17:08:18 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 2D51A1E805; Fri, 2 Feb 2018 17:08:18 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w12H8Ivv080342; Fri, 2 Feb 2018 17:08:18 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w12H8I9P080341; Fri, 2 Feb 2018 17:08:18 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802021708.w12H8I9P080341@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Fri, 2 Feb 2018 17:08:18 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328790 - vendor/compiler-rt/compiler-rt-release_60-r324090 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/compiler-rt/compiler-rt-release_60-r324090 X-SVN-Commit-Revision: 328790 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 17:08:21 -0000 Author: dim Date: Fri Feb 2 17:08:17 2018 New Revision: 328790 URL: https://svnweb.freebsd.org/changeset/base/328790 Log: Tag compiler-rt release_60 branch r324090. Added: vendor/compiler-rt/compiler-rt-release_60-r324090/ - copied from r328789, vendor/compiler-rt/dist-release_60/ From owner-svn-src-vendor@freebsd.org Fri Feb 2 17:08:30 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id EBE22EE43CE; Fri, 2 Feb 2018 17:08:29 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id EA96074BB9; Fri, 2 Feb 2018 17:08:27 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id CC9A11E806; Fri, 2 Feb 2018 17:08:27 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w12H8R72080391; Fri, 2 Feb 2018 17:08:27 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w12H8RvC080390; Fri, 2 Feb 2018 17:08:27 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802021708.w12H8RvC080390@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Fri, 2 Feb 2018 17:08:27 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328791 - vendor/libc++/libc++-release_60-r324090 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/libc++/libc++-release_60-r324090 X-SVN-Commit-Revision: 328791 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 17:08:30 -0000 Author: dim Date: Fri Feb 2 17:08:27 2018 New Revision: 328791 URL: https://svnweb.freebsd.org/changeset/base/328791 Log: Tag libc++ release_60 branch r324090. Added: vendor/libc++/libc++-release_60-r324090/ - copied from r328790, vendor/libc++/dist-release_60/ From owner-svn-src-vendor@freebsd.org Fri Feb 2 17:08:34 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id ED1E3EE43EE; Fri, 2 Feb 2018 17:08:33 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id B772674C29; Fri, 2 Feb 2018 17:08:31 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id DEC7A1E807; Fri, 2 Feb 2018 17:08:30 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w12H8UJJ080448; Fri, 2 Feb 2018 17:08:30 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w12H8UdH080440; Fri, 2 Feb 2018 17:08:30 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802021708.w12H8UdH080440@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Fri, 2 Feb 2018 17:08:30 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328792 - in vendor/lld/dist-release_60: ELF ELF/Arch test/ELF X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/lld/dist-release_60: ELF ELF/Arch test/ELF X-SVN-Commit-Revision: 328792 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 17:08:34 -0000 Author: dim Date: Fri Feb 2 17:08:29 2018 New Revision: 328792 URL: https://svnweb.freebsd.org/changeset/base/328792 Log: Vendor import of lld release_60 branch r324090: https://llvm.org/svn/llvm-project/lld/branches/release_60@324090 Added: vendor/lld/dist-release_60/test/ELF/i386-retpoline-nopic.s (contents, props changed) vendor/lld/dist-release_60/test/ELF/i386-retpoline-pic.s (contents, props changed) vendor/lld/dist-release_60/test/ELF/x86-64-retpoline-znow.s (contents, props changed) vendor/lld/dist-release_60/test/ELF/x86-64-retpoline.s (contents, props changed) Modified: vendor/lld/dist-release_60/ELF/Arch/X86.cpp vendor/lld/dist-release_60/ELF/Arch/X86_64.cpp vendor/lld/dist-release_60/ELF/Config.h vendor/lld/dist-release_60/ELF/Driver.cpp Modified: vendor/lld/dist-release_60/ELF/Arch/X86.cpp ============================================================================== --- vendor/lld/dist-release_60/ELF/Arch/X86.cpp Fri Feb 2 17:08:27 2018 (r328791) +++ vendor/lld/dist-release_60/ELF/Arch/X86.cpp Fri Feb 2 17:08:29 2018 (r328792) @@ -21,7 +21,7 @@ using namespace lld; using namespace lld::elf; namespace { -class X86 final : public TargetInfo { +class X86 : public TargetInfo { public: X86(); RelExpr getRelExpr(RelType Type, const Symbol &S, @@ -399,7 +399,145 @@ void X86::relaxTlsLdToLe(uint8_t *Loc, RelType Type, u memcpy(Loc - 2, Inst, sizeof(Inst)); } +namespace { +class RetpolinePic : public X86 { +public: + RetpolinePic(); + void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; + void writePltHeader(uint8_t *Buf) const override; + void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, + int32_t Index, unsigned RelOff) const override; +}; + +class RetpolineNoPic : public X86 { +public: + RetpolineNoPic(); + void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; + void writePltHeader(uint8_t *Buf) const override; + void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, + int32_t Index, unsigned RelOff) const override; +}; +} // namespace + +RetpolinePic::RetpolinePic() { + PltHeaderSize = 48; + PltEntrySize = 32; +} + +void RetpolinePic::writeGotPlt(uint8_t *Buf, const Symbol &S) const { + write32le(Buf, S.getPltVA() + 17); +} + +void RetpolinePic::writePltHeader(uint8_t *Buf) const { + const uint8_t Insn[] = { + 0xff, 0xb3, 0, 0, 0, 0, // 0: pushl GOTPLT+4(%ebx) + 0x50, // 6: pushl %eax + 0x8b, 0x83, 0, 0, 0, 0, // 7: mov GOTPLT+8(%ebx), %eax + 0xe8, 0x0e, 0x00, 0x00, 0x00, // d: call next + 0xf3, 0x90, // 12: loop: pause + 0x0f, 0xae, 0xe8, // 14: lfence + 0xeb, 0xf9, // 17: jmp loop + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 19: int3; .align 16 + 0x89, 0x0c, 0x24, // 20: next: mov %ecx, (%esp) + 0x8b, 0x4c, 0x24, 0x04, // 23: mov 0x4(%esp), %ecx + 0x89, 0x44, 0x24, 0x04, // 27: mov %eax ,0x4(%esp) + 0x89, 0xc8, // 2b: mov %ecx, %eax + 0x59, // 2d: pop %ecx + 0xc3, // 2e: ret + }; + memcpy(Buf, Insn, sizeof(Insn)); + + uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize(); + uint32_t GotPlt = InX::GotPlt->getVA() - Ebx; + write32le(Buf + 2, GotPlt + 4); + write32le(Buf + 9, GotPlt + 8); +} + +void RetpolinePic::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, + uint64_t PltEntryAddr, int32_t Index, + unsigned RelOff) const { + const uint8_t Insn[] = { + 0x50, // pushl %eax + 0x8b, 0x83, 0, 0, 0, 0, // mov foo@GOT(%ebx), %eax + 0xe8, 0, 0, 0, 0, // call plt+0x20 + 0xe9, 0, 0, 0, 0, // jmp plt+0x12 + 0x68, 0, 0, 0, 0, // pushl $reloc_offset + 0xe9, 0, 0, 0, 0, // jmp plt+0 + }; + memcpy(Buf, Insn, sizeof(Insn)); + + uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize(); + write32le(Buf + 3, GotPltEntryAddr - Ebx); + write32le(Buf + 8, -Index * PltEntrySize - PltHeaderSize - 12 + 32); + write32le(Buf + 13, -Index * PltEntrySize - PltHeaderSize - 17 + 18); + write32le(Buf + 18, RelOff); + write32le(Buf + 23, -Index * PltEntrySize - PltHeaderSize - 27); +} + +RetpolineNoPic::RetpolineNoPic() { + PltHeaderSize = 48; + PltEntrySize = 32; +} + +void RetpolineNoPic::writeGotPlt(uint8_t *Buf, const Symbol &S) const { + write32le(Buf, S.getPltVA() + 16); +} + +void RetpolineNoPic::writePltHeader(uint8_t *Buf) const { + const uint8_t PltData[] = { + 0xff, 0x35, 0, 0, 0, 0, // 0: pushl GOTPLT+4 + 0x50, // 6: pushl %eax + 0xa1, 0, 0, 0, 0, // 7: mov GOTPLT+8, %eax + 0xe8, 0x0f, 0x00, 0x00, 0x00, // c: call next + 0xf3, 0x90, // 11: loop: pause + 0x0f, 0xae, 0xe8, // 13: lfence + 0xeb, 0xf9, // 16: jmp loop + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 18: int3 + 0xcc, 0xcc, 0xcc, // 1f: int3; .align 16 + 0x89, 0x0c, 0x24, // 20: next: mov %ecx, (%esp) + 0x8b, 0x4c, 0x24, 0x04, // 23: mov 0x4(%esp), %ecx + 0x89, 0x44, 0x24, 0x04, // 27: mov %eax ,0x4(%esp) + 0x89, 0xc8, // 2b: mov %ecx, %eax + 0x59, // 2d: pop %ecx + 0xc3, // 2e: ret + }; + memcpy(Buf, PltData, sizeof(PltData)); + + uint32_t GotPlt = InX::GotPlt->getVA(); + write32le(Buf + 2, GotPlt + 4); + write32le(Buf + 8, GotPlt + 8); +} + +void RetpolineNoPic::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, + uint64_t PltEntryAddr, int32_t Index, + unsigned RelOff) const { + const uint8_t Insn[] = { + 0x50, // 0: pushl %eax + 0xa1, 0, 0, 0, 0, // 1: mov foo_in_GOT, %eax + 0xe8, 0, 0, 0, 0, // 6: call plt+0x20 + 0xe9, 0, 0, 0, 0, // b: jmp plt+0x11 + 0x68, 0, 0, 0, 0, // 10: pushl $reloc_offset + 0xe9, 0, 0, 0, 0, // 15: jmp plt+0 + }; + memcpy(Buf, Insn, sizeof(Insn)); + + write32le(Buf + 2, GotPltEntryAddr); + write32le(Buf + 7, -Index * PltEntrySize - PltHeaderSize - 11 + 32); + write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16 + 17); + write32le(Buf + 17, RelOff); + write32le(Buf + 22, -Index * PltEntrySize - PltHeaderSize - 26); +} + TargetInfo *elf::getX86TargetInfo() { - static X86 Target; - return &Target; + if (Config->ZRetpolineplt) { + if (Config->Pic) { + static RetpolinePic T; + return &T; + } + static RetpolineNoPic T; + return &T; + } + + static X86 T; + return &T; } Modified: vendor/lld/dist-release_60/ELF/Arch/X86_64.cpp ============================================================================== --- vendor/lld/dist-release_60/ELF/Arch/X86_64.cpp Fri Feb 2 17:08:27 2018 (r328791) +++ vendor/lld/dist-release_60/ELF/Arch/X86_64.cpp Fri Feb 2 17:08:29 2018 (r328792) @@ -23,7 +23,7 @@ using namespace lld; using namespace lld::elf; namespace { -template class X86_64 final : public TargetInfo { +template class X86_64 : public TargetInfo { public: X86_64(); RelExpr getRelExpr(RelType Type, const Symbol &S, @@ -460,12 +460,125 @@ void X86_64::relaxGot(uint8_t *Loc, uint64_t Val write32le(Loc - 1, Val + 1); } -TargetInfo *elf::getX32TargetInfo() { - static X86_64 Target; - return &Target; +namespace { +template class Retpoline : public X86_64 { +public: + Retpoline(); + void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; + void writePltHeader(uint8_t *Buf) const override; + void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, + int32_t Index, unsigned RelOff) const override; +}; + +template class RetpolineZNow : public X86_64 { +public: + RetpolineZNow(); + void writeGotPlt(uint8_t *Buf, const Symbol &S) const override {} + void writePltHeader(uint8_t *Buf) const override; + void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, + int32_t Index, unsigned RelOff) const override; +}; +} // namespace + +template Retpoline::Retpoline() { + TargetInfo::PltHeaderSize = 48; + TargetInfo::PltEntrySize = 32; } -TargetInfo *elf::getX86_64TargetInfo() { - static X86_64 Target; - return &Target; +template +void Retpoline::writeGotPlt(uint8_t *Buf, const Symbol &S) const { + write32le(Buf, S.getPltVA() + 17); } + +template void Retpoline::writePltHeader(uint8_t *Buf) const { + const uint8_t Insn[] = { + 0xff, 0x35, 0, 0, 0, 0, // 0: pushq GOTPLT+8(%rip) + 0x4c, 0x8b, 0x1d, 0, 0, 0, 0, // 6: mov GOTPLT+16(%rip), %r11 + 0xe8, 0x0e, 0x00, 0x00, 0x00, // d: callq next + 0xf3, 0x90, // 12: loop: pause + 0x0f, 0xae, 0xe8, // 14: lfence + 0xeb, 0xf9, // 17: jmp loop + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 19: int3; .align 16 + 0x4c, 0x89, 0x1c, 0x24, // 20: next: mov %r11, (%rsp) + 0xc3, // 24: ret + }; + memcpy(Buf, Insn, sizeof(Insn)); + + uint64_t GotPlt = InX::GotPlt->getVA(); + uint64_t Plt = InX::Plt->getVA(); + write32le(Buf + 2, GotPlt - Plt - 6 + 8); + write32le(Buf + 9, GotPlt - Plt - 13 + 16); +} + +template +void Retpoline::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, + uint64_t PltEntryAddr, int32_t Index, + unsigned RelOff) const { + const uint8_t Insn[] = { + 0x4c, 0x8b, 0x1d, 0, 0, 0, 0, // 0: mov foo@GOTPLT(%rip), %r11 + 0xe8, 0, 0, 0, 0, // 7: callq plt+0x20 + 0xe9, 0, 0, 0, 0, // c: jmp plt+0x12 + 0x68, 0, 0, 0, 0, // 11: pushq + 0xe9, 0, 0, 0, 0, // 16: jmp plt+0 + }; + memcpy(Buf, Insn, sizeof(Insn)); + + uint64_t Off = TargetInfo::PltHeaderSize + TargetInfo::PltEntrySize * Index; + + write32le(Buf + 3, GotPltEntryAddr - PltEntryAddr - 7); + write32le(Buf + 8, -Off - 12 + 32); + write32le(Buf + 13, -Off - 17 + 18); + write32le(Buf + 18, Index); + write32le(Buf + 23, -Off - 27); +} + +template RetpolineZNow::RetpolineZNow() { + TargetInfo::PltHeaderSize = 32; + TargetInfo::PltEntrySize = 16; +} + +template +void RetpolineZNow::writePltHeader(uint8_t *Buf) const { + const uint8_t Insn[] = { + 0xe8, 0x0b, 0x00, 0x00, 0x00, // 0: call next + 0xf3, 0x90, // 5: loop: pause + 0x0f, 0xae, 0xe8, // 7: lfence + 0xeb, 0xf9, // a: jmp loop + 0xcc, 0xcc, 0xcc, 0xcc, // c: int3; .align 16 + 0x4c, 0x89, 0x1c, 0x24, // 10: next: mov %r11, (%rsp) + 0xc3, // 14: ret + }; + memcpy(Buf, Insn, sizeof(Insn)); +} + +template +void RetpolineZNow::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, + uint64_t PltEntryAddr, int32_t Index, + unsigned RelOff) const { + const uint8_t Insn[] = { + 0x4c, 0x8b, 0x1d, 0, 0, 0, 0, // mov foo@GOTPLT(%rip), %r11 + 0xe9, 0, 0, 0, 0, // jmp plt+0 + }; + memcpy(Buf, Insn, sizeof(Insn)); + + write32le(Buf + 3, GotPltEntryAddr - PltEntryAddr - 7); + write32le(Buf + 8, + -Index * TargetInfo::PltEntrySize - TargetInfo::PltHeaderSize - 12); +} + +template TargetInfo *getTargetInfo() { + if (Config->ZRetpolineplt) { + if (Config->ZNow) { + static RetpolineZNow T; + return &T; + } + static Retpoline T; + return &T; + } + + static X86_64 T; + return &T; +} + +TargetInfo *elf::getX32TargetInfo() { return getTargetInfo(); } +TargetInfo *elf::getX86_64TargetInfo() { return getTargetInfo(); } Modified: vendor/lld/dist-release_60/ELF/Config.h ============================================================================== --- vendor/lld/dist-release_60/ELF/Config.h Fri Feb 2 17:08:27 2018 (r328791) +++ vendor/lld/dist-release_60/ELF/Config.h Fri Feb 2 17:08:29 2018 (r328792) @@ -159,6 +159,7 @@ struct Configuration { bool ZRelro; bool ZRodynamic; bool ZText; + bool ZRetpolineplt; bool ExitEarly; bool ZWxneeded; DiscardPolicy Discard; Modified: vendor/lld/dist-release_60/ELF/Driver.cpp ============================================================================== --- vendor/lld/dist-release_60/ELF/Driver.cpp Fri Feb 2 17:08:27 2018 (r328791) +++ vendor/lld/dist-release_60/ELF/Driver.cpp Fri Feb 2 17:08:29 2018 (r328792) @@ -674,6 +674,7 @@ void LinkerDriver::readConfigs(opt::InputArgList &Args Config->ZNow = hasZOption(Args, "now"); Config->ZOrigin = hasZOption(Args, "origin"); Config->ZRelro = !hasZOption(Args, "norelro"); + Config->ZRetpolineplt = hasZOption(Args, "retpolineplt"); Config->ZRodynamic = hasZOption(Args, "rodynamic"); Config->ZStackSize = args::getZOptionValue(Args, OPT_z, "stack-size", 0); Config->ZText = !hasZOption(Args, "notext"); Added: vendor/lld/dist-release_60/test/ELF/i386-retpoline-nopic.s ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/lld/dist-release_60/test/ELF/i386-retpoline-nopic.s Fri Feb 2 17:08:29 2018 (r328792) @@ -0,0 +1,65 @@ +// REQUIRES: x86 +// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %s -o %t1.o +// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %p/Inputs/shared.s -o %t2.o +// RUN: ld.lld -shared %t2.o -o %t2.so + +// RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt +// RUN: llvm-objdump -d -s %t.exe | FileCheck %s + +// CHECK: Disassembly of section .plt: +// CHECK-NEXT: .plt: +// CHECK-NEXT: 11010: ff 35 04 20 01 00 pushl 73732 +// CHECK-NEXT: 11016: 50 pushl %eax +// CHECK-NEXT: 11017: a1 08 20 01 00 movl 73736, %eax +// CHECK-NEXT: 1101c: e8 0f 00 00 00 calll 15 <.plt+0x20> +// CHECK-NEXT: 11021: f3 90 pause +// CHECK-NEXT: 11023: 0f ae e8 lfence +// CHECK-NEXT: 11026: eb f9 jmp -7 <.plt+0x11> +// CHECK-NEXT: 11028: cc int3 +// CHECK-NEXT: 11029: cc int3 +// CHECK-NEXT: 1102a: cc int3 +// CHECK-NEXT: 1102b: cc int3 +// CHECK-NEXT: 1102c: cc int3 +// CHECK-NEXT: 1102d: cc int3 +// CHECK-NEXT: 1102e: cc int3 +// CHECK-NEXT: 1102f: cc int3 +// CHECK-NEXT: 11030: 89 0c 24 movl %ecx, (%esp) +// CHECK-NEXT: 11033: 8b 4c 24 04 movl 4(%esp), %ecx +// CHECK-NEXT: 11037: 89 44 24 04 movl %eax, 4(%esp) +// CHECK-NEXT: 1103b: 89 c8 movl %ecx, %eax +// CHECK-NEXT: 1103d: 59 popl %ecx +// CHECK-NEXT: 1103e: c3 retl +// CHECK-NEXT: 1103f: cc int3 +// CHECK-NEXT: 11040: 50 pushl %eax +// CHECK-NEXT: 11041: a1 0c 20 01 00 movl 73740, %eax +// CHECK-NEXT: 11046: e8 e5 ff ff ff calll -27 <.plt+0x20> +// CHECK-NEXT: 1104b: e9 d1 ff ff ff jmp -47 <.plt+0x11> +// CHECK-NEXT: 11050: 68 00 00 00 00 pushl $0 +// CHECK-NEXT: 11055: e9 b6 ff ff ff jmp -74 <.plt> +// CHECK-NEXT: 1105a: cc int3 +// CHECK-NEXT: 1105b: cc int3 +// CHECK-NEXT: 1105c: cc int3 +// CHECK-NEXT: 1105d: cc int3 +// CHECK-NEXT: 1105e: cc int3 +// CHECK-NEXT: 1105f: cc int3 +// CHECK-NEXT: 11060: 50 pushl %eax +// CHECK-NEXT: 11061: a1 10 20 01 00 movl 73744, %eax +// CHECK-NEXT: 11066: e8 c5 ff ff ff calll -59 <.plt+0x20> +// CHECK-NEXT: 1106b: e9 b1 ff ff ff jmp -79 <.plt+0x11> +// CHECK-NEXT: 11070: 68 08 00 00 00 pushl $8 +// CHECK-NEXT: 11075: e9 96 ff ff ff jmp -106 <.plt> +// CHECK-NEXT: 1107a: cc int3 +// CHECK-NEXT: 1107b: cc int3 +// CHECK-NEXT: 1107c: cc int3 +// CHECK-NEXT: 1107d: cc int3 +// CHECK-NEXT: 1107e: cc int3 +// CHECK-NEXT: 1107f: cc int3 + +// CHECK: Contents of section .got.plt: +// CHECK-NEXT: 00300100 00000000 00000000 50100100 +// CHECK-NEXT: 70100100 + +.global _start +_start: + jmp bar@PLT + jmp zed@PLT Added: vendor/lld/dist-release_60/test/ELF/i386-retpoline-pic.s ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/lld/dist-release_60/test/ELF/i386-retpoline-pic.s Fri Feb 2 17:08:29 2018 (r328792) @@ -0,0 +1,62 @@ +// REQUIRES: x86 +// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %s -o %t1.o +// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %p/Inputs/shared.s -o %t2.o +// RUN: ld.lld -shared %t2.o -o %t2.so + +// RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt -pie +// RUN: llvm-objdump -d -s %t.exe | FileCheck %s + +// CHECK: Disassembly of section .plt: +// CHECK-NEXT: .plt: +// CHECK-NEXT: 1010: ff b3 04 20 00 00 pushl 8196(%ebx) +// CHECK-NEXT: 1016: 50 pushl %eax +// CHECK-NEXT: 1017: 8b 83 08 20 00 00 movl 8200(%ebx), %eax +// CHECK-NEXT: 101d: e8 0e 00 00 00 calll 14 <.plt+0x20> +// CHECK-NEXT: 1022: f3 90 pause +// CHECK-NEXT: 1024: 0f ae e8 lfence +// CHECK-NEXT: 1027: eb f9 jmp -7 <.plt+0x12> +// CHECK-NEXT: 1029: cc int3 +// CHECK-NEXT: 102a: cc int3 +// CHECK-NEXT: 102b: cc int3 +// CHECK-NEXT: 102c: cc int3 +// CHECK-NEXT: 102d: cc int3 +// CHECK-NEXT: 102e: cc int3 +// CHECK-NEXT: 102f: cc int3 +// CHECK-NEXT: 1030: 89 0c 24 movl %ecx, (%esp) +// CHECK-NEXT: 1033: 8b 4c 24 04 movl 4(%esp), %ecx +// CHECK-NEXT: 1037: 89 44 24 04 movl %eax, 4(%esp) +// CHECK-NEXT: 103b: 89 c8 movl %ecx, %eax +// CHECK-NEXT: 103d: 59 popl %ecx +// CHECK-NEXT: 103e: c3 retl +// CHECK-NEXT: 103f: cc int3 +// CHECK-NEXT: 1040: 50 pushl %eax +// CHECK-NEXT: 1041: 8b 83 0c 20 00 00 movl 8204(%ebx), %eax +// CHECK-NEXT: 1047: e8 e4 ff ff ff calll -28 <.plt+0x20> +// CHECK-NEXT: 104c: e9 d1 ff ff ff jmp -47 <.plt+0x12> +// CHECK-NEXT: 1051: 68 00 00 00 00 pushl $0 +// CHECK-NEXT: 1056: e9 b5 ff ff ff jmp -75 <.plt> +// CHECK-NEXT: 105b: cc int3 +// CHECK-NEXT: 105c: cc int3 +// CHECK-NEXT: 105d: cc int3 +// CHECK-NEXT: 105e: cc int3 +// CHECK-NEXT: 105f: cc int3 +// CHECK-NEXT: 1060: 50 pushl %eax +// CHECK-NEXT: 1061: 8b 83 10 20 00 00 movl 8208(%ebx), %eax +// CHECK-NEXT: 1067: e8 c4 ff ff ff calll -60 <.plt+0x20> +// CHECK-NEXT: 106c: e9 b1 ff ff ff jmp -79 <.plt+0x12> +// CHECK-NEXT: 1071: 68 08 00 00 00 pushl $8 +// CHECK-NEXT: 1076: e9 95 ff ff ff jmp -107 <.plt> +// CHECK-NEXT: 107b: cc int3 +// CHECK-NEXT: 107c: cc int3 +// CHECK-NEXT: 107d: cc int3 +// CHECK-NEXT: 107e: cc int3 +// CHECK-NEXT: 107f: cc int3 + +// CHECK: Contents of section .got.plt: +// CHECK-NEXT: 2000 00300000 00000000 00000000 51100000 +// CHECK-NEXT: 2010 71100000 + +.global _start +_start: + jmp bar@PLT + jmp zed@PLT Added: vendor/lld/dist-release_60/test/ELF/x86-64-retpoline-znow.s ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/lld/dist-release_60/test/ELF/x86-64-retpoline-znow.s Fri Feb 2 17:08:29 2018 (r328792) @@ -0,0 +1,53 @@ +// REQUIRES: x86 +// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o +// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o +// RUN: ld.lld -shared %t2.o -o %t2.so + +// RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt -z now +// RUN: llvm-objdump -d -s %t.exe | FileCheck %s + +// CHECK: Disassembly of section .plt: +// CHECK-NEXT: .plt: +// CHECK-NEXT: 1010: e8 0b 00 00 00 callq 11 <.plt+0x10> +// CHECK-NEXT: 1015: f3 90 pause +// CHECK-NEXT: 1017: 0f ae e8 lfence +// CHECK-NEXT: 101a: eb f9 jmp -7 <.plt+0x5> +// CHECK-NEXT: 101c: cc int3 +// CHECK-NEXT: 101d: cc int3 +// CHECK-NEXT: 101e: cc int3 +// CHECK-NEXT: 101f: cc int3 +// CHECK-NEXT: 1020: 4c 89 1c 24 movq %r11, (%rsp) +// CHECK-NEXT: 1024: c3 retq +// CHECK-NEXT: 1025: cc int3 +// CHECK-NEXT: 1026: cc int3 +// CHECK-NEXT: 1027: cc int3 +// CHECK-NEXT: 1028: cc int3 +// CHECK-NEXT: 1029: cc int3 +// CHECK-NEXT: 102a: cc int3 +// CHECK-NEXT: 102b: cc int3 +// CHECK-NEXT: 102c: cc int3 +// CHECK-NEXT: 102d: cc int3 +// CHECK-NEXT: 102e: cc int3 +// CHECK-NEXT: 102f: cc int3 +// CHECK-NEXT: 1030: 4c 8b 1d c1 10 00 00 movq 4289(%rip), %r11 +// CHECK-NEXT: 1037: e9 d4 ff ff ff jmp -44 <.plt> +// CHECK-NEXT: 103c: cc int3 +// CHECK-NEXT: 103d: cc int3 +// CHECK-NEXT: 103e: cc int3 +// CHECK-NEXT: 103f: cc int3 +// CHECK-NEXT: 1040: 4c 8b 1d b9 10 00 00 movq 4281(%rip), %r11 +// CHECK-NEXT: 1047: e9 c4 ff ff ff jmp -60 <.plt> +// CHECK-NEXT: 104c: cc int3 +// CHECK-NEXT: 104d: cc int3 +// CHECK-NEXT: 104e: cc int3 +// CHECK-NEXT: 104f: cc int3 + +// CHECK: Contents of section .got.plt: +// CHECK-NEXT: 20e0 00200000 00000000 00000000 00000000 +// CHECK-NEXT: 20f0 00000000 00000000 00000000 00000000 +// CHECK-NEXT: 2100 00000000 00000000 + +.global _start +_start: + jmp bar@PLT + jmp zed@PLT Added: vendor/lld/dist-release_60/test/ELF/x86-64-retpoline.s ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/lld/dist-release_60/test/ELF/x86-64-retpoline.s Fri Feb 2 17:08:29 2018 (r328792) @@ -0,0 +1,66 @@ +// REQUIRES: x86 +// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o +// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o +// RUN: ld.lld -shared %t2.o -o %t2.so + +// RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt +// RUN: llvm-objdump -d -s %t.exe | FileCheck %s + +// CHECK: Disassembly of section .plt: +// CHECK-NEXT: .plt: +// CHECK-NEXT: 1010: ff 35 f2 0f 00 00 pushq 4082(%rip) +// CHECK-NEXT: 1016: 4c 8b 1d f3 0f 00 00 movq 4083(%rip), %r11 +// CHECK-NEXT: 101d: e8 0e 00 00 00 callq 14 <.plt+0x20> +// CHECK-NEXT: 1022: f3 90 pause +// CHECK-NEXT: 1024: 0f ae e8 lfence +// CHECK-NEXT: 1027: eb f9 jmp -7 <.plt+0x12> +// CHECK-NEXT: 1029: cc int3 +// CHECK-NEXT: 102a: cc int3 +// CHECK-NEXT: 102b: cc int3 +// CHECK-NEXT: 102c: cc int3 +// CHECK-NEXT: 102d: cc int3 +// CHECK-NEXT: 102e: cc int3 +// CHECK-NEXT: 102f: cc int3 +// CHECK-NEXT: 1030: 4c 89 1c 24 movq %r11, (%rsp) +// CHECK-NEXT: 1034: c3 retq +// CHECK-NEXT: 1035: cc int3 +// CHECK-NEXT: 1036: cc int3 +// CHECK-NEXT: 1037: cc int3 +// CHECK-NEXT: 1038: cc int3 +// CHECK-NEXT: 1039: cc int3 +// CHECK-NEXT: 103a: cc int3 +// CHECK-NEXT: 103b: cc int3 +// CHECK-NEXT: 103c: cc int3 +// CHECK-NEXT: 103d: cc int3 +// CHECK-NEXT: 103e: cc int3 +// CHECK-NEXT: 103f: cc int3 +// CHECK-NEXT: 1040: 4c 8b 1d d1 0f 00 00 movq 4049(%rip), %r11 +// CHECK-NEXT: 1047: e8 e4 ff ff ff callq -28 <.plt+0x20> +// CHECK-NEXT: 104c: e9 d1 ff ff ff jmp -47 <.plt+0x12> +// CHECK-NEXT: 1051: 68 00 00 00 00 pushq $0 +// CHECK-NEXT: 1056: e9 b5 ff ff ff jmp -75 <.plt> +// CHECK-NEXT: 105b: cc int3 +// CHECK-NEXT: 105c: cc int3 +// CHECK-NEXT: 105d: cc int3 +// CHECK-NEXT: 105e: cc int3 +// CHECK-NEXT: 105f: cc int3 +// CHECK-NEXT: 1060: 4c 8b 1d b9 0f 00 00 movq 4025(%rip), %r11 +// CHECK-NEXT: 1067: e8 c4 ff ff ff callq -60 <.plt+0x20> +// CHECK-NEXT: 106c: e9 b1 ff ff ff jmp -79 <.plt+0x12> +// CHECK-NEXT: 1071: 68 01 00 00 00 pushq $1 +// CHECK-NEXT: 1076: e9 95 ff ff ff jmp -107 <.plt> +// CHECK-NEXT: 107b: cc int3 +// CHECK-NEXT: 107c: cc int3 +// CHECK-NEXT: 107d: cc int3 +// CHECK-NEXT: 107e: cc int3 +// CHECK-NEXT: 107f: cc int3 + +// CHECK: Contents of section .got.plt: +// CHECK-NEXT: 2000 00300000 00000000 00000000 00000000 +// CHECK-NEXT: 2010 00000000 00000000 51100000 00000000 +// CHECK-NEXT: 2020 71100000 00000000 + +.global _start +_start: + jmp bar@PLT + jmp zed@PLT From owner-svn-src-vendor@freebsd.org Fri Feb 2 17:08:37 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 09345EE4402; Fri, 2 Feb 2018 17:08:37 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 8E19674CDA; Fri, 2 Feb 2018 17:08:36 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4C7C61E808; Fri, 2 Feb 2018 17:08:36 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w12H8aQg080495; Fri, 2 Feb 2018 17:08:36 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w12H8aq0080494; Fri, 2 Feb 2018 17:08:36 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802021708.w12H8aq0080494@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Fri, 2 Feb 2018 17:08:36 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328793 - vendor/lld/lld-release_60-r324090 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lld/lld-release_60-r324090 X-SVN-Commit-Revision: 328793 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 17:08:37 -0000 Author: dim Date: Fri Feb 2 17:08:35 2018 New Revision: 328793 URL: https://svnweb.freebsd.org/changeset/base/328793 Log: Tag lld release_60 branch r324090. Added: vendor/lld/lld-release_60-r324090/ - copied from r328792, vendor/lld/dist-release_60/ From owner-svn-src-vendor@freebsd.org Fri Feb 2 17:08:44 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 48AFCEE4450; Fri, 2 Feb 2018 17:08:44 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 1846674E00; Fri, 2 Feb 2018 17:08:42 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 6B2611E809; Fri, 2 Feb 2018 17:08:40 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w12H8eOp080543; Fri, 2 Feb 2018 17:08:40 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w12H8eGA080542; Fri, 2 Feb 2018 17:08:40 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802021708.w12H8eGA080542@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Fri, 2 Feb 2018 17:08:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328794 - vendor/lldb/lldb-release_60-r324090 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lldb/lldb-release_60-r324090 X-SVN-Commit-Revision: 328794 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 17:08:44 -0000 Author: dim Date: Fri Feb 2 17:08:39 2018 New Revision: 328794 URL: https://svnweb.freebsd.org/changeset/base/328794 Log: Tag lldb release_60 branch r324090. Added: vendor/lldb/lldb-release_60-r324090/ - copied from r328793, vendor/lldb/dist-release_60/