From owner-svn-src-vendor@freebsd.org Mon Nov 26 11:01:53 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 47B2F1154E0F; Mon, 26 Nov 2018 11:01:53 +0000 (UTC) (envelope-from mm@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id E1FD56C18C; Mon, 26 Nov 2018 11:01:52 +0000 (UTC) (envelope-from mm@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id A8F5A2B8E; Mon, 26 Nov 2018 11:01:52 +0000 (UTC) (envelope-from mm@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wAQB1qZj010759; Mon, 26 Nov 2018 11:01:52 GMT (envelope-from mm@FreeBSD.org) Received: (from mm@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wAQB1peW010754; Mon, 26 Nov 2018 11:01:51 GMT (envelope-from mm@FreeBSD.org) Message-Id: <201811261101.wAQB1peW010754@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mm set sender to mm@FreeBSD.org using -f From: Martin Matuska Date: Mon, 26 Nov 2018 11:01:51 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r340938 - in vendor/libarchive/dist: . libarchive libarchive/test X-SVN-Group: vendor X-SVN-Commit-Author: mm X-SVN-Commit-Paths: in vendor/libarchive/dist: . libarchive libarchive/test X-SVN-Commit-Revision: 340938 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: E1FD56C18C X-Spamd-Result: default: False [1.08 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.27)[-0.272,0]; NEURAL_SPAM_LONG(0.68)[0.678,0]; NEURAL_SPAM_MEDIUM(0.68)[0.676,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Nov 2018 11:01:53 -0000 Author: mm Date: Mon Nov 26 11:01:51 2018 New Revision: 340938 URL: https://svnweb.freebsd.org/changeset/base/340938 Log: Update vendor/libarchive/dist to git 2c5e9bdbb62eeb56a37776f796c15ed16727193e Relevant vendor changes: Issue #1096: Support extracting ACLs with in-entry comments (GNU tar) PR #1023: Support extracting extattrs as non-root on non-user-writable files Modified: vendor/libarchive/dist/CMakeLists.txt vendor/libarchive/dist/libarchive/archive_acl.c vendor/libarchive/dist/libarchive/archive_write_disk_posix.c vendor/libarchive/dist/libarchive/test/test_extattr_freebsd.c vendor/libarchive/dist/libarchive/test/test_read_format_rar5.c Modified: vendor/libarchive/dist/CMakeLists.txt ============================================================================== --- vendor/libarchive/dist/CMakeLists.txt Mon Nov 26 10:53:17 2018 (r340937) +++ vendor/libarchive/dist/CMakeLists.txt Mon Nov 26 11:01:51 2018 (r340938) @@ -592,6 +592,8 @@ ENDIF(ZSTD_FOUND) MARK_AS_ADVANCED(CLEAR ZSTD_INCLUDE_DIR) MARK_AS_ADVANCED(CLEAR ZSTD_LIBRARY) +set(CMAKE_REQUIRED_LIBRARIES) + # # Check headers # Modified: vendor/libarchive/dist/libarchive/archive_acl.c ============================================================================== --- vendor/libarchive/dist/libarchive/archive_acl.c Mon Nov 26 10:53:17 2018 (r340937) +++ vendor/libarchive/dist/libarchive/archive_acl.c Mon Nov 26 11:01:51 2018 (r340938) @@ -1585,18 +1585,30 @@ next_field_w(const wchar_t **wp, const wchar_t **start /* Scan for the separator. */ while (**wp != L'\0' && **wp != L',' && **wp != L':' && - **wp != L'\n') { + **wp != L'\n' && **wp != L'#') { (*wp)++; } *sep = **wp; - /* Trim trailing whitespace to locate end of field. */ - *end = *wp - 1; - while (**end == L' ' || **end == L'\t' || **end == L'\n') { - (*end)--; + /* Locate end of field, trim trailing whitespace if necessary */ + if (*wp == *start) { + *end = *wp; + } else { + *end = *wp - 1; + while (**end == L' ' || **end == L'\t' || **end == L'\n') { + (*end)--; + } + (*end)++; } - (*end)++; + /* Handle in-field comments */ + if (*sep == L'#') { + while (**wp != L'\0' && **wp != L',' && **wp != L'\n') { + (*wp)++; + } + *sep = **wp; + } + /* Adjust scanner location. */ if (**wp != L'\0') (*wp)++; @@ -1646,7 +1658,7 @@ archive_acl_from_text_l(struct archive_acl *acl, const ret = ARCHIVE_OK; types = 0; - while (text != NULL && *text != '\0') { + while (text != NULL && *text != '\0') { /* * Parse the fields out of the next entry, * advance 'text' to start of next entry. @@ -2057,23 +2069,30 @@ next_field(const char **p, const char **start, *start = *p; /* Scan for the separator. */ - while (**p != '\0' && **p != ',' && **p != ':' && **p != '\n') { + while (**p != '\0' && **p != ',' && **p != ':' && **p != '\n' && + **p != '#') { (*p)++; } *sep = **p; - /* If the field is only whitespace, bail out now. */ - if (**p == '\0') { + /* Locate end of field, trim trailing whitespace if necessary */ + if (*p == *start) { *end = *p; - return; + } else { + *end = *p - 1; + while (**end == ' ' || **end == '\t' || **end == '\n') { + (*end)--; + } + (*end)++; } - /* Trim trailing whitespace to locate end of field. */ - *end = *p - 1; - while (**end == ' ' || **end == '\t' || **end == '\n') { - (*end)--; + /* Handle in-field comments */ + if (*sep == '#') { + while (**p != '\0' && **p != ',' && **p != '\n') { + (*p)++; + } + *sep = **p; } - (*end)++; /* Adjust scanner location. */ if (**p != '\0') Modified: vendor/libarchive/dist/libarchive/archive_write_disk_posix.c ============================================================================== --- vendor/libarchive/dist/libarchive/archive_write_disk_posix.c Mon Nov 26 10:53:17 2018 (r340937) +++ vendor/libarchive/dist/libarchive/archive_write_disk_posix.c Mon Nov 26 11:01:51 2018 (r340938) @@ -1705,6 +1705,20 @@ _archive_write_disk_finish_entry(struct archive *_a) } /* + * HYPOTHESIS: + * If we're not root, we won't be setting any security + * attributes that may be wiped by the set_mode() routine + * below. We also can't set xattr on non-owner-writable files, + * which may be the state after set_mode(). Perform + * set_xattrs() first based on these constraints. + */ + if (a->user_uid != 0 && + (a->todo & TODO_XATTR)) { + int r2 = set_xattrs(a); + if (r2 < ret) ret = r2; + } + + /* * set_mode must precede ACLs on systems such as Solaris and * FreeBSD where setting the mode implicitly clears extended ACLs */ @@ -1717,8 +1731,10 @@ _archive_write_disk_finish_entry(struct archive *_a) * Security-related extended attributes (such as * security.capability on Linux) have to be restored last, * since they're implicitly removed by other file changes. + * We do this last only when root. */ - if (a->todo & TODO_XATTR) { + if (a->user_uid == 0 && + (a->todo & TODO_XATTR)) { int r2 = set_xattrs(a); if (r2 < ret) ret = r2; } @@ -2222,6 +2238,15 @@ create_filesystem_object(struct archive_write_disk *a) * security, so we never restore them at this point. */ mode = final_mode & 0777 & ~a->user_umask; + + /* + * Always create writable such that [f]setxattr() works if we're not + * root. + */ + if (a->user_uid != 0 && + a->todo & (TODO_HFS_COMPRESSION | TODO_XATTR)) { + mode |= 0200; + } switch (a->mode & AE_IFMT) { default: Modified: vendor/libarchive/dist/libarchive/test/test_extattr_freebsd.c ============================================================================== --- vendor/libarchive/dist/libarchive/test/test_extattr_freebsd.c Mon Nov 26 10:53:17 2018 (r340937) +++ vendor/libarchive/dist/libarchive/test/test_extattr_freebsd.c Mon Nov 26 11:01:51 2018 (r340938) @@ -48,7 +48,6 @@ DEFINE_TEST(test_extattr_freebsd) struct archive *a; struct archive_entry *ae; int n, fd; - int extattr_privilege_bug = 0; /* * First, do a quick manual set/read of an extended attribute @@ -72,24 +71,6 @@ DEFINE_TEST(test_extattr_freebsd) assertEqualInt(4, n); close(fd); - /* - * Repeat the above, but with file permissions set to 0000. - * This should work (extattr_set_fd() should follow fd - * permissions, not file permissions), but is known broken on - * some versions of FreeBSD. - */ - fd = open("pretest2", O_RDWR | O_CREAT, 00000); - failure("Could not create test file?!"); - if (!assert(fd >= 0)) - return; - - n = extattr_set_fd(fd, EXTATTR_NAMESPACE_USER, "testattr", "1234", 4); - if (n != 4) { - skipping("Restoring xattr to an unwritable file seems to be broken on this platform"); - extattr_privilege_bug = 1; - } - close(fd); - /* Create a write-to-disk object. */ assert(NULL != (a = archive_write_disk_new())); archive_write_disk_set_options(a, @@ -119,16 +100,12 @@ DEFINE_TEST(test_extattr_freebsd) archive_entry_free(ae); /* Close the archive. */ - if (extattr_privilege_bug) - /* If the bug is here, write_close will return warning. */ - assertEqualIntA(a, ARCHIVE_WARN, archive_write_close(a)); - else - assertEqualIntA(a, ARCHIVE_OK, archive_write_close(a)); - assertEqualInt(ARCHIVE_OK, archive_write_free(a)); + assertEqualIntA(a, ARCHIVE_OK, archive_write_close(a)); /* Verify the data on disk. */ assertEqualInt(0, stat("test0", &st)); assertEqualInt(st.st_mtime, 123456); + assertEqualInt(st.st_mode & 0777, 0755); /* Verify extattr */ n = extattr_get_file("test0", EXTATTR_NAMESPACE_USER, "foo", buff, sizeof(buff)); @@ -140,17 +117,20 @@ DEFINE_TEST(test_extattr_freebsd) /* Verify the data on disk. */ assertEqualInt(0, stat("test1", &st)); assertEqualInt(st.st_mtime, 12345678); + assertEqualInt(st.st_mode & 0777, 0); + /* + * If we are not root, we have to make test1 user readable + * or extattr_get_file() will fail + */ + if (geteuid() != 0) { + chmod("test1", S_IRUSR); + } /* Verify extattr */ n = extattr_get_file("test1", EXTATTR_NAMESPACE_USER, "bar", buff, sizeof(buff)); - if (extattr_privilege_bug) { - /* If we have the bug, the extattr won't have been written. */ - assertEqualInt(n, -1); - } else { - if (assertEqualInt(n, 6)) { - buff[n] = '\0'; - assertEqualString(buff, "123456"); - } + if (assertEqualInt(n, 6)) { + buff[n] = '\0'; + assertEqualString(buff, "123456"); } /* Use libarchive APIs to read the file back into an entry and Modified: vendor/libarchive/dist/libarchive/test/test_read_format_rar5.c ============================================================================== --- vendor/libarchive/dist/libarchive/test/test_read_format_rar5.c Mon Nov 26 10:53:17 2018 (r340937) +++ vendor/libarchive/dist/libarchive/test/test_read_format_rar5.c Mon Nov 26 11:01:51 2018 (r340938) @@ -90,7 +90,7 @@ int verify_data(const uint8_t* data_ptr, int magic, in static int extract_one(struct archive* a, struct archive_entry* ae, uint32_t crc) { - la_ssize_t fsize, read; + la_ssize_t fsize, bytes_read; uint8_t* buf; int ret = 1; uint32_t computed_crc; @@ -100,9 +100,9 @@ int extract_one(struct archive* a, struct archive_entr if(buf == NULL) return 1; - read = archive_read_data(a, buf, fsize); - if(read != fsize) { - assertEqualInt(read, fsize); + bytes_read = archive_read_data(a, buf, fsize); + if(bytes_read != fsize) { + assertEqualInt(bytes_read, fsize); goto fn_exit; } From owner-svn-src-vendor@freebsd.org Tue Nov 27 12:31:59 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 5B74E1149EA9; Tue, 27 Nov 2018 12:31:59 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 249AA76E5F; Tue, 27 Nov 2018 12:31:59 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id E2EBE1B4F4; Tue, 27 Nov 2018 12:31:58 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wARCVwDW007815; Tue, 27 Nov 2018 12:31:58 GMT (envelope-from marius@FreeBSD.org) Received: (from marius@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wARCVwok007814; Tue, 27 Nov 2018 12:31:58 GMT (envelope-from marius@FreeBSD.org) Message-Id: <201811271231.wARCVwok007814@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: marius set sender to marius@FreeBSD.org using -f From: Marius Strobl Date: Tue, 27 Nov 2018 12:31:58 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341039 - vendor-sys/ck/dist/include/gcc/sparcv9 X-SVN-Group: vendor-sys X-SVN-Commit-Author: marius X-SVN-Commit-Paths: vendor-sys/ck/dist/include/gcc/sparcv9 X-SVN-Commit-Revision: 341039 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 249AA76E5F X-Spamd-Result: default: False [1.69 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_SPAM_LONG(0.51)[0.511,0]; NEURAL_SPAM_MEDIUM(0.69)[0.687,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US]; NEURAL_SPAM_SHORT(0.49)[0.488,0] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Nov 2018 12:31:59 -0000 Author: marius Date: Tue Nov 27 12:31:58 2018 New Revision: 341039 URL: https://svnweb.freebsd.org/changeset/base/341039 Log: Import CK as of 21d3e319407d19dece16ee317c757ffc54a452bc, which makes its sparcv9 atomics compatible with the FreeBSD kernel by using instructions which access the appropriate address space. Modified: vendor-sys/ck/dist/include/gcc/sparcv9/ck_pr.h Modified: vendor-sys/ck/dist/include/gcc/sparcv9/ck_pr.h ============================================================================== --- vendor-sys/ck/dist/include/gcc/sparcv9/ck_pr.h Tue Nov 27 12:23:01 2018 (r341038) +++ vendor-sys/ck/dist/include/gcc/sparcv9/ck_pr.h Tue Nov 27 12:31:58 2018 (r341039) @@ -136,11 +136,26 @@ CK_PR_STORE_S(int, int, "stsw") #undef CK_PR_STORE_S #undef CK_PR_STORE +/* Use the appropriate address space for atomics within the FreeBSD kernel. */ +#if defined(__FreeBSD__) && defined(_KERNEL) +#include +#include +#define CK_PR_INS_CAS "casa" +#define CK_PR_INS_CASX "casxa" +#define CK_PR_INS_SWAP "swapa" +#define CK_PR_ASI_ATOMIC __XSTRING(__ASI_ATOMIC) +#else +#define CK_PR_INS_CAS "cas" +#define CK_PR_INS_CASX "casx" +#define CK_PR_INS_SWAP "swap" +#define CK_PR_ASI_ATOMIC "" +#endif + CK_CC_INLINE static bool ck_pr_cas_64_value(uint64_t *target, uint64_t compare, uint64_t set, uint64_t *value) { - __asm__ __volatile__("casx [%1], %2, %0" + __asm__ __volatile__(CK_PR_INS_CASX " [%1] " CK_PR_ASI_ATOMIC ", %2, %0" : "+&r" (set) : "r" (target), "r" (compare) @@ -154,7 +169,7 @@ CK_CC_INLINE static bool ck_pr_cas_64(uint64_t *target, uint64_t compare, uint64_t set) { - __asm__ __volatile__("casx [%1], %2, %0" + __asm__ __volatile__(CK_PR_INS_CASX " [%1] " CK_PR_ASI_ATOMIC ", %2, %0" : "+&r" (set) : "r" (target), "r" (compare) @@ -181,7 +196,7 @@ ck_pr_cas_ptr_value(void *target, void *compare, void CK_CC_INLINE static bool \ ck_pr_cas_##N##_value(T *target, T compare, T set, T *value) \ { \ - __asm__ __volatile__("cas [%1], %2, %0" \ + __asm__ __volatile__(CK_PR_INS_CAS " [%1] " CK_PR_ASI_ATOMIC ", %2, %0" \ : "+&r" (set) \ : "r" (target), \ "r" (compare) \ @@ -192,7 +207,7 @@ ck_pr_cas_ptr_value(void *target, void *compare, void CK_CC_INLINE static bool \ ck_pr_cas_##N(T *target, T compare, T set) \ { \ - __asm__ __volatile__("cas [%1], %2, %0" \ + __asm__ __volatile__(CK_PR_INS_CAS " [%1] " CK_PR_ASI_ATOMIC ", %2, %0" \ : "+&r" (set) \ : "r" (target), \ "r" (compare) \ @@ -211,7 +226,7 @@ CK_PR_CAS(int, int) ck_pr_fas_##N(T *target, T update) \ { \ \ - __asm__ __volatile__("swap [%1], %0" \ + __asm__ __volatile__(CK_PR_INS_SWAP " [%1] " CK_PR_ASI_ATOMIC ", %0" \ : "+&r" (update) \ : "r" (target) \ : "memory"); \ @@ -223,6 +238,11 @@ CK_PR_FAS(uint, unsigned int) CK_PR_FAS(32, uint32_t) #undef CK_PR_FAS + +#undef CK_PR_INS_CAS +#undef CK_PR_INS_CASX +#undef CK_PR_INS_SWAP +#undef CK_PR_ASI_ATOMIC #endif /* CK_PR_SPARCV9_H */ From owner-svn-src-vendor@freebsd.org Tue Nov 27 12:32:33 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 471EA1149F34; Tue, 27 Nov 2018 12:32:33 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id DDE2877121; Tue, 27 Nov 2018 12:32:32 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id A6C6C1B51B; Tue, 27 Nov 2018 12:32:32 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wARCWW9C007880; Tue, 27 Nov 2018 12:32:32 GMT (envelope-from marius@FreeBSD.org) Received: (from marius@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wARCWWQB007879; Tue, 27 Nov 2018 12:32:32 GMT (envelope-from marius@FreeBSD.org) Message-Id: <201811271232.wARCWWQB007879@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: marius set sender to marius@FreeBSD.org using -f From: Marius Strobl Date: Tue, 27 Nov 2018 12:32:32 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341040 - vendor-sys/ck/20181120 X-SVN-Group: vendor-sys X-SVN-Commit-Author: marius X-SVN-Commit-Paths: vendor-sys/ck/20181120 X-SVN-Commit-Revision: 341040 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: DDE2877121 X-Spamd-Result: default: False [1.43 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_SPAM_LONG(0.42)[0.417,0]; NEURAL_SPAM_SHORT(0.42)[0.416,0]; NEURAL_SPAM_MEDIUM(0.60)[0.595,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Nov 2018 12:32:33 -0000 Author: marius Date: Tue Nov 27 12:32:32 2018 New Revision: 341040 URL: https://svnweb.freebsd.org/changeset/base/341040 Log: Tag the import of CK as of 21d3e319407d19dece16ee317c757ffc54a452bc. Added: vendor-sys/ck/20181120/ - copied from r341039, vendor-sys/ck/dist/ From owner-svn-src-vendor@freebsd.org Sat Dec 1 15:41:35 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 24DF2131A9EB; Sat, 1 Dec 2018 15:41:35 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id BE8F386C78; Sat, 1 Dec 2018 15:41:34 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 8749E19BE5; Sat, 1 Dec 2018 15:41:34 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wB1FfYkx012198; Sat, 1 Dec 2018 15:41:34 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wB1FfYT3012197; Sat, 1 Dec 2018 15:41:34 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201812011541.wB1FfYT3012197@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 1 Dec 2018 15:41:34 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341366 - vendor/llvm/llvm-release_70-r348011 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/llvm/llvm-release_70-r348011 X-SVN-Commit-Revision: 341366 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: BE8F386C78 X-Spamd-Result: default: False [-0.13 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.45)[-0.452,0]; NEURAL_SPAM_LONG(0.28)[0.278,0]; NEURAL_SPAM_MEDIUM(0.04)[0.040,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2018 15:41:35 -0000 Author: dim Date: Sat Dec 1 15:41:34 2018 New Revision: 341366 URL: https://svnweb.freebsd.org/changeset/base/341366 Log: Tag llvm release_70 branch r348011. Added: vendor/llvm/llvm-release_70-r348011/ - copied from r341365, vendor/llvm/dist-release_70/ From owner-svn-src-vendor@freebsd.org Sat Dec 1 15:41:32 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E2F75131A9E4; Sat, 1 Dec 2018 15:41:31 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 9287F86C68; Sat, 1 Dec 2018 15:41:31 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 73EAA19BE1; Sat, 1 Dec 2018 15:41:31 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wB1FfVqO012152; Sat, 1 Dec 2018 15:41:31 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wB1FfPK2012119; Sat, 1 Dec 2018 15:41:25 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201812011541.wB1FfPK2012119@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 1 Dec 2018 15:41:25 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341365 - in vendor/llvm/dist-release_70: include/llvm/MC include/llvm/Support include/llvm/Transforms/Utils lib/CodeGen lib/MC lib/Target/Mips lib/Target/Mips/MCTargetDesc lib/Target/P... X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/llvm/dist-release_70: include/llvm/MC include/llvm/Support include/llvm/Transforms/Utils lib/CodeGen lib/MC lib/Target/Mips lib/Target/Mips/MCTargetDesc lib/Target/PowerPC lib/Transforms/Uti... X-SVN-Commit-Revision: 341365 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 9287F86C68 X-Spamd-Result: default: False [0.31 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.42)[-0.417,0]; NEURAL_SPAM_LONG(0.42)[0.418,0]; NEURAL_SPAM_MEDIUM(0.31)[0.312,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2018 15:41:32 -0000 Author: dim Date: Sat Dec 1 15:41:24 2018 New Revision: 341365 URL: https://svnweb.freebsd.org/changeset/base/341365 Log: Vendor import of llvm release_70 branch r348011: https://llvm.org/svn/llvm-project/llvm/branches/release_70@348011 Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-b-range.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-mtc-mfc.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir vendor/llvm/dist-release_70/test/CodeGen/PowerPC/scalar_vector_test_1.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/scalar_vector_test_2.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/scalar_vector_test_3.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/scalar_vector_test_4.ll vendor/llvm/dist-release_70/test/DebugInfo/Mips/eh_frame.ll vendor/llvm/dist-release_70/test/Transforms/LCSSA/rewrite-existing-dbg-values.ll Modified: vendor/llvm/dist-release_70/include/llvm/MC/MCAsmBackend.h vendor/llvm/dist-release_70/include/llvm/Support/GenericDomTreeConstruction.h vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdater.h vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdaterImpl.h vendor/llvm/dist-release_70/lib/CodeGen/TargetLoweringObjectFileImpl.cpp vendor/llvm/dist-release_70/lib/MC/MCExpr.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h vendor/llvm/dist-release_70/lib/Target/Mips/MicroMips32r6InstrInfo.td vendor/llvm/dist-release_70/lib/Target/Mips/Mips64InstrInfo.td vendor/llvm/dist-release_70/lib/Target/Mips/Mips64r6InstrInfo.td vendor/llvm/dist-release_70/lib/Target/Mips/MipsFastISel.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MipsInstrFPU.td vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEFrameLowering.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEISelDAGToDAG.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEInstrInfo.cpp vendor/llvm/dist-release_70/lib/Target/PowerPC/P9InstrResources.td vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCISelLowering.cpp vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCInstrVSX.td vendor/llvm/dist-release_70/lib/Transforms/Utils/LCSSA.cpp vendor/llvm/dist-release_70/lib/Transforms/Utils/SSAUpdater.cpp vendor/llvm/dist-release_70/test/CodeGen/Mips/longbranch.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/tls.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/build-vector-tests.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/load-v4i8-improved.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/power9-moves-and-splats.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/pr38087.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/qpx-load-splat.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/swaps-le-6.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/vsx_insert_extract_le.ll vendor/llvm/dist-release_70/test/CodeGen/X86/mingw-comdats.ll vendor/llvm/dist-release_70/tools/llvm-exegesis/lib/CMakeLists.txt Modified: vendor/llvm/dist-release_70/include/llvm/MC/MCAsmBackend.h ============================================================================== --- vendor/llvm/dist-release_70/include/llvm/MC/MCAsmBackend.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/include/llvm/MC/MCAsmBackend.h Sat Dec 1 15:41:24 2018 (r341365) @@ -165,6 +165,11 @@ class MCAsmBackend { (public) return 0; } + /// Check whether a given symbol has been flagged with MICROMIPS flag. + virtual bool isMicroMips(const MCSymbol *Sym) const { + return false; + } + /// Handles all target related code padding when starting to write a new /// basic block to an object file. /// Modified: vendor/llvm/dist-release_70/include/llvm/Support/GenericDomTreeConstruction.h ============================================================================== --- vendor/llvm/dist-release_70/include/llvm/Support/GenericDomTreeConstruction.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/include/llvm/Support/GenericDomTreeConstruction.h Sat Dec 1 15:41:24 2018 (r341365) @@ -1186,6 +1186,20 @@ struct SemiNCAInfo { << '\t' << U << "\n"); LLVM_DEBUG(dbgs() << "\n"); + // Recalculate the DominatorTree when the number of updates + // exceeds a threshold, which usually makes direct updating slower than + // recalculation. We select this threshold proportional to the + // size of the DominatorTree. The constant is selected + // by choosing the one with an acceptable performance on some real-world + // inputs. + + // Make unittests of the incremental algorithm work + if (DT.DomTreeNodes.size() <= 100) { + if (NumLegalized > DT.DomTreeNodes.size()) + CalculateFromScratch(DT, &BUI); + } else if (NumLegalized > DT.DomTreeNodes.size() / 40) + CalculateFromScratch(DT, &BUI); + // If the DominatorTree was recalculated at some point, stop the batch // updates. Full recalculations ignore batch updates and look at the actual // CFG. Modified: vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdater.h ============================================================================== --- vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdater.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdater.h Sat Dec 1 15:41:24 2018 (r341365) @@ -76,6 +76,10 @@ class SSAUpdater { (public) /// block. bool HasValueForBlock(BasicBlock *BB) const; + /// Return the value for the specified block if the SSAUpdater has one, + /// otherwise return nullptr. + Value *FindValueForBlock(BasicBlock *BB) const; + /// Construct SSA form, materializing a value that is live at the end /// of the specified block. Value *GetValueAtEndOfBlock(BasicBlock *BB); Modified: vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdaterImpl.h ============================================================================== --- vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdaterImpl.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdaterImpl.h Sat Dec 1 15:41:24 2018 (r341365) @@ -357,10 +357,9 @@ class SSAUpdaterImpl { (public) BBInfo *Info = *I; if (Info->DefBB != Info) { - // Record the available value at join nodes to speed up subsequent - // uses of this SSAUpdater for the same value. - if (Info->NumPreds > 1) - (*AvailableVals)[Info->BB] = Info->DefBB->AvailableVal; + // Record the available value to speed up subsequent uses of this + // SSAUpdater for the same value. + (*AvailableVals)[Info->BB] = Info->DefBB->AvailableVal; continue; } Modified: vendor/llvm/dist-release_70/lib/CodeGen/TargetLoweringObjectFileImpl.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -1156,10 +1156,11 @@ MCSection *TargetLoweringObjectFileCOFF::SelectSection MCSymbol *Sym = TM.getSymbol(ComdatGV); StringRef COMDATSymName = Sym->getName(); - // Append "$symbol" to the section name when targetting mingw. The ld.bfd + // Append "$symbol" to the section name *before* IR-level mangling is + // applied when targetting mingw. This is what GCC does, and the ld.bfd // COFF linker will not properly handle comdats otherwise. if (getTargetTriple().isWindowsGNUEnvironment()) - raw_svector_ostream(Name) << '$' << COMDATSymName; + raw_svector_ostream(Name) << '$' << ComdatGV->getName(); return getContext().getCOFFSection(Name, Characteristics, Kind, COMDATSymName, Selection, UniqueID); Modified: vendor/llvm/dist-release_70/lib/MC/MCExpr.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/MC/MCExpr.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/MC/MCExpr.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -524,6 +524,11 @@ static void AttemptToFoldSymbolOffsetDifference( if (Asm->isThumbFunc(&SA)) Addend |= 1; + // If symbol is labeled as micromips, we set low-bit to ensure + // correct offset in .gcc_except_table + if (Asm->getBackend().isMicroMips(&SA)) + Addend |= 1; + // Clear the symbol expr pointers to indicate we have folded these // operands. A = B = nullptr; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -25,6 +25,7 @@ #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCTargetOptions.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/ErrorHandling.h" @@ -566,6 +567,14 @@ bool MipsAsmBackend::shouldForceRelocation(const MCAss case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: return true; } +} + +bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const { + if (const auto *ElfSym = dyn_cast(Sym)) { + if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS) + return true; + } + return false; } MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Sat Dec 1 15:41:24 2018 (r341365) @@ -25,6 +25,7 @@ class MCAssembler; struct MCFixupKindInfo; class MCObjectWriter; class MCRegisterInfo; +class MCSymbolELF; class Target; class MipsAsmBackend : public MCAsmBackend { @@ -90,6 +91,7 @@ class MipsAsmBackend : public MCAsmBackend { (public) bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override; + bool isMicroMips(const MCSymbol *Sym) const override; }; // class MipsAsmBackend } // namespace Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -15,6 +15,7 @@ #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSymbolELF.h" @@ -51,6 +52,22 @@ void MipsELFStreamer::EmitInstruction(const MCInst &In } createPendingLabelRelocs(); +} + +void MipsELFStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { + Frame.Begin = getContext().createTempSymbol(); + MCELFStreamer::EmitLabel(Frame.Begin); +} + +MCSymbol *MipsELFStreamer::EmitCFILabel() { + MCSymbol *Label = getContext().createTempSymbol("cfi", true); + MCELFStreamer::EmitLabel(Label); + return Label; +} + +void MipsELFStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { + Frame.End = getContext().createTempSymbol(); + MCELFStreamer::EmitLabel(Frame.End); } void MipsELFStreamer::createPendingLabelRelocs() { Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h Sat Dec 1 15:41:24 2018 (r341365) @@ -26,6 +26,7 @@ class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCSubtargetInfo; +struct MCDwarfFrameInfo; class MipsELFStreamer : public MCELFStreamer { SmallVector, 8> MipsOptionRecords; @@ -59,6 +60,12 @@ class MipsELFStreamer : public MCELFStreamer { (public /// directives are emitted. void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override; void EmitIntValue(uint64_t Value, unsigned Size) override; + + // Overriding these functions allows us to avoid recording of these labels + // in EmitLabel and later marking them as microMIPS. + void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; + void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; + MCSymbol *EmitCFILabel() override; /// Emits all the option records stored up until the point it's called. void EmitMipsOptionRecords(); Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MicroMips32r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MicroMips32r6InstrInfo.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MicroMips32r6InstrInfo.td Sat Dec 1 15:41:24 2018 (r341365) @@ -1733,7 +1733,7 @@ defm S_MMR6 : Cmp_Pats, ISA_MICRO defm D_MMR6 : Cmp_Pats, ISA_MICROMIPS32R6; def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6; -def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1 ZERO))>, ISA_MICROMIPS32R6; +def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6; def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/Mips64InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/Mips64InstrInfo.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/Mips64InstrInfo.td Sat Dec 1 15:41:24 2018 (r341365) @@ -838,7 +838,7 @@ def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$ (SUBu GPR32:$src, GPR32:$src2), sub_32)>; def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), - (MUL GPR32:$src, GPR32:$src2), sub_32)>; + (MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS3_NOT_32R6_64R6; def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (PseudoMFHI ACC64:$src), sub_32)>; @@ -1139,3 +1139,6 @@ def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs) "sltu\t$rs, $rt, $imm">, GPR_64; def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm)>, GPR_64; + +def : MipsInstAlias<"rdhwr $rt, $rs", + (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/Mips64r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/Mips64r6InstrInfo.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/Mips64r6InstrInfo.td Sat Dec 1 15:41:24 2018 (r341365) @@ -301,6 +301,9 @@ def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i // Patterns used for matching away redundant sign extensions. // MIPS32 arithmetic instructions sign extend their result implicitly. +def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MUL_R6 GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; def : MipsPat<(i64 (sext (i32 (sdiv GPR32:$src, GPR32:$src2)))), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (DIV GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsFastISel.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsFastISel.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsFastISel.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -953,6 +953,11 @@ bool MipsFastISel::selectBranch(const Instruction *I) MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; // For now, just try the simplest case where it's fed by a compare. if (const CmpInst *CI = dyn_cast(BI->getCondition())) { + MVT CIMVT = + TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT(); + if (CIMVT == MVT::i1) + return false; + unsigned CondReg = getRegForValue(CI); BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ)) .addReg(CondReg) Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsInstrFPU.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsInstrFPU.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsInstrFPU.td Sat Dec 1 15:41:24 2018 (r341365) @@ -485,14 +485,14 @@ let AdditionalPredicates = [NotInMicroMips] in { def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>, ISA_MIPS1; - def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, - bitconvert>, MFC1_FM<0>, ISA_MIPS1; + def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, + bitconvert>, MFC1_FM<0>, ISA_MIPS1; def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, ISA_MIPS1, FGR_64 { let DecoderNamespace = "MipsFP64"; } - def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, - bitconvert>, MFC1_FM<4>, ISA_MIPS1; + def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, + bitconvert>, MFC1_FM<4>, ISA_MIPS1; def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, ISA_MIPS1, FGR_64 { let DecoderNamespace = "MipsFP64"; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEFrameLowering.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEFrameLowering.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEFrameLowering.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -299,8 +299,12 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBloc // register). Unfortunately, we have to make this decision before register // allocation so for now we use a spill/reload sequence for all // double-precision values in regardless of being an odd/even register. - if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || - (FP64 && !Subtarget.useOddSPReg())) { + // + // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as + // implicit operand, so other passes (like ShrinkWrapping) are aware that + // stack is used. + if (I->getNumOperands() == 4 && I->getOperand(3).isReg() + && I->getOperand(3).getReg() == Mips::SP) { unsigned DstReg = I->getOperand(0).getReg(); unsigned LoReg = I->getOperand(1).getReg(); unsigned HiReg = I->getOperand(2).getReg(); @@ -360,9 +364,12 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasi // register). Unfortunately, we have to make this decision before register // allocation so for now we use a spill/reload sequence for all // double-precision values in regardless of being an odd/even register. - - if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || - (FP64 && !Subtarget.useOddSPReg())) { + // + // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as + // implicit operand, so other passes (like ShrinkWrapping) are aware that + // stack is used. + if (I->getNumOperands() == 4 && I->getOperand(3).isReg() + && I->getOperand(3).getReg() == Mips::SP) { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = Op1.getReg(); unsigned N = Op2.getImm(); Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEISelDAGToDAG.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -238,6 +238,18 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(Mach case Mips::WRDSP: addDSPCtrlRegOperands(true, MI, MF); break; + case Mips::BuildPairF64_64: + case Mips::ExtractElementF64_64: + if (!Subtarget->useOddSPReg()) { + MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true)); + break; + } + // fallthrough + case Mips::BuildPairF64: + case Mips::ExtractElementF64: + if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1()) + MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true)); + break; default: replaceUsesWithZeroReg(MRI, MI); } Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEInstrInfo.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEInstrInfo.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEInstrInfo.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -25,9 +25,14 @@ using namespace llvm; +static unsigned getUnconditionalBranch(const MipsSubtarget &STI) { + if (STI.inMicroMipsMode()) + return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; + return STI.isPositionIndependent() ? Mips::B : Mips::J; +} + MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) - : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), - RI() {} + : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {} const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { return RI; @@ -643,7 +648,7 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || - Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || + Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || Modified: vendor/llvm/dist-release_70/lib/Target/PowerPC/P9InstrResources.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/PowerPC/P9InstrResources.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/PowerPC/P9InstrResources.td Sat Dec 1 15:41:24 2018 (r341365) @@ -592,6 +592,7 @@ def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP XXPERM, XXPERMR, XXSLDWI, + XXSLDWIs, XXSPLTIB, XXSPLTW, XXSPLTWs, Modified: vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCISelLowering.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCISelLowering.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -8454,17 +8454,6 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue if (V2.isUndef() && PPC::isSplatShuffleMask(SVOp, 4)) { int SplatIdx = PPC::getVSPLTImmediate(SVOp, 4, DAG); - // If the source for the shuffle is a scalar_to_vector that came from a - // 32-bit load, it will have used LXVWSX so we don't need to splat again. - if (Subtarget.hasP9Vector() && - ((isLittleEndian && SplatIdx == 3) || - (!isLittleEndian && SplatIdx == 0))) { - SDValue Src = V1.getOperand(0); - if (Src.getOpcode() == ISD::SCALAR_TO_VECTOR && - Src.getOperand(0).getOpcode() == ISD::LOAD && - Src.getOperand(0).hasOneUse()) - return V1; - } SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv, DAG.getConstant(SplatIdx, dl, MVT::i32)); Modified: vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCInstrVSX.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCInstrVSX.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCInstrVSX.td Sat Dec 1 15:41:24 2018 (r341365) @@ -877,6 +877,12 @@ let Uses = [RM] in { "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB, imm32SExt16:$SHW))]>; + + let isCodeGenOnly = 1 in + def XXSLDWIs : XX3Form_2s<60, 2, + (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$SHW), + "xxsldwi $XT, $XA, $XA, $SHW", IIC_VecPerm, []>; + def XXSPLTW : XX2Form_2<60, 164, (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM), "xxspltw $XT, $XB, $UIM", IIC_VecPerm, @@ -886,6 +892,7 @@ let Uses = [RM] in { def XXSPLTWs : XX2Form_2<60, 164, (outs vsrc:$XT), (ins vfrc:$XB, u2imm:$UIM), "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>; + } // hasSideEffects } // UseVSXReg = 1 @@ -1466,8 +1473,6 @@ let AddedComplexity = 400 in { // Prefer VSX patterns (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 1)))))), (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; } - def : Pat<(v4i32 (scalar_to_vector ScalarLoads.Li32)), - (v4i32 (XXSPLTWs (LIWAX xoaddr:$src), 1))>; // Instructions for converting float to i64 feeding a store. let Predicates = [NoP9Vector] in { @@ -3050,14 +3055,48 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] (STXVX $rS, xoaddr:$dst)>; def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst), (STXVX $rS, xoaddr:$dst)>; - def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), - (v4i32 (LXVWSX xoaddr:$src))>; - def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), - (v4f32 (LXVWSX xoaddr:$src))>; - def : Pat<(v4f32 (scalar_to_vector - (f32 (fpround (f64 (extloadf32 xoaddr:$src)))))), - (v4f32 (LXVWSX xoaddr:$src))>; + let AddedComplexity = 400 in { + // LIWAX - This instruction is used for sign extending i32 -> i64. + // LIWZX - This instruction will be emitted for i32, f32, and when + // zero-extending i32 to i64 (zext i32 -> i64). + let Predicates = [IsLittleEndian] in { + + def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC), 2))>; + + def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>; + + def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), + (v4i32 (XXPERMDIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>; + + def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), + (v4f32 (XXPERMDIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>; + } + + let Predicates = [IsBigEndian] in { + def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC))>; + + def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC))>; + + def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), + (v4i32 (XXSLDWIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>; + + def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), + (v4f32 (XXSLDWIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>; + } + + } + // Build vectors from i8 loads def : Pat<(v16i8 (scalar_to_vector ScalarLoads.Li8)), (v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>; @@ -3218,6 +3257,39 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))), (f32 (DFLOADf32 ixaddr:$src))>; + + let AddedComplexity = 400 in { + // The following pseudoinstructions are used to ensure the utilization + // of all 64 VSX registers. + let Predicates = [IsLittleEndian, HasP9Vector] in { + def : Pat<(v2i64 (scalar_to_vector (i64 (load ixaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC), 2))>; + def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC), 2))>; + + def : Pat<(v2f64 (scalar_to_vector (f64 (load ixaddr:$src)))), + (v2f64 (XXPERMDIs + (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC), 2))>; + def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddr:$src)))), + (v2f64 (XXPERMDIs + (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC), 2))>; + } + + let Predicates = [IsBigEndian, HasP9Vector] in { + def : Pat<(v2i64 (scalar_to_vector (i64 (load ixaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC))>; + def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC))>; + + def : Pat<(v2f64 (scalar_to_vector (f64 (load ixaddr:$src)))), + (v2f64 (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC))>; + def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddr:$src)))), + (v2f64 (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC))>; + } + } + let Predicates = [IsBigEndian, HasP9Vector] in { // (Un)Signed DWord vector extract -> QP @@ -3932,3 +4004,4 @@ let AddedComplexity = 400 in { (v4i32 (VEXTSH2W $A))>; } } + Modified: vendor/llvm/dist-release_70/lib/Transforms/Utils/LCSSA.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Transforms/Utils/LCSSA.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Transforms/Utils/LCSSA.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -41,6 +41,7 @@ #include "llvm/IR/Dominators.h" #include "llvm/IR/Function.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/PredIteratorCache.h" #include "llvm/Pass.h" #include "llvm/Transforms/Utils.h" @@ -199,6 +200,21 @@ bool llvm::formLCSSAForInstructions(SmallVectorImpl DbgValues; + llvm::findDbgValues(DbgValues, I); + + // Update pre-existing debug value uses that reside outside the loop. + auto &Ctx = I->getContext(); + for (auto DVI : DbgValues) { + BasicBlock *UserBB = DVI->getParent(); + if (InstBB == UserBB || L->contains(UserBB)) + continue; + // We currently only handle debug values residing in blocks where we have + // inserted a PHI instruction. + if (Value *V = SSAUpdate.FindValueForBlock(UserBB)) + DVI->setOperand(0, MetadataAsValue::get(Ctx, ValueAsMetadata::get(V))); } // SSAUpdater might have inserted phi-nodes inside other loops. We'll need Modified: vendor/llvm/dist-release_70/lib/Transforms/Utils/SSAUpdater.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Transforms/Utils/SSAUpdater.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Transforms/Utils/SSAUpdater.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -64,6 +64,11 @@ bool SSAUpdater::HasValueForBlock(BasicBlock *BB) cons return getAvailableVals(AV).count(BB); } +Value *SSAUpdater::FindValueForBlock(BasicBlock *BB) const { + AvailableValsTy::iterator AVI = getAvailableVals(AV).find(BB); + return (AVI != getAvailableVals(AV).end()) ? AVI->second : nullptr; +} + void SSAUpdater::AddAvailableValue(BasicBlock *BB, Value *V) { assert(ProtoType && "Need to initialize SSAUpdater"); assert(ProtoType == V->getType() && Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,189 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ +; RUN: < %s -verify-machineinstrs | FileCheck %s + +define void @testeq(i32, i32) { +; CHECK-LABEL: testeq: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: beq $[[REG0]], $[[REG1]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp eq i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testne(i32, i32) { +; CHECK-LABEL: testne: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: bne $[[REG0]], $[[REG1]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp ne i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testugt(i32, i32) { +; CHECK-LABEL: testugt: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] +; CHECK: bnez $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp ugt i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testuge(i32, i32) { +; CHECK-LABEL: testuge: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] +; CHECK: beqz $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp uge i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testult(i32, i32) { +; CHECK-LABEL: testult: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] +; CHECK: bnez $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp ult i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testule(i32, i32) { +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] +; CHECK: beqz $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp ule i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testsgt(i32, i32) { +; CHECK-LABEL: testsgt: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: negu $[[REG0]], $[[REG0]] +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: negu $[[REG1]], $[[REG1]] +; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] +; CHECK: bnez $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp sgt i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testsge(i32, i32) { +; CHECK-LABEL: testsge: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: negu $[[REG0]], $[[REG0]] +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: negu $[[REG1]], $[[REG1]] +; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] +; CHECK: beqz $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp sge i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testslt(i32, i32) { +; CHECK-LABEL: testslt: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: negu $[[REG0]], $[[REG0]] +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: negu $[[REG1]], $[[REG1]] +; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] +; CHECK: bnez $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp slt i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testsle(i32, i32) { +; CHECK-LABEL: testsle: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: negu $[[REG0]], $[[REG0]] +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: negu $[[REG1]], $[[REG1]] +; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] +; CHECK: beqz $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp sle i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +declare void @llvm.trap() Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,32 @@ +; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ +; RUN: -mcpu=mips32 -mattr=+fpxx \ +; RUN: -stop-after=expand-isel-pseudos | \ +; RUN: FileCheck %s -check-prefix=FPXX-IMPLICIT-SP + +; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ +; RUN: -mcpu=mips32r6 -mattr=+fp64,+nooddspreg \ +; RUN: -stop-after=expand-isel-pseudos | \ +; RUN: FileCheck %s -check-prefix=FP64-IMPLICIT-SP + +; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ +; RUN: -mcpu=mips32r2 -mattr=+fpxx \ +; RUN: -stop-after=expand-isel-pseudos | \ +; RUN: FileCheck %s -check-prefix=NO-IMPLICIT-SP + +define double @foo2(i32 signext %v1, double %d1) { +entry: +; FPXX-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp +; FPXX-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1, implicit $sp +; FP64-IMPLICIT-SP: BuildPairF64_64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp +; FP64-IMPLICIT-SP: ExtractElementF64_64 killed %{{[0-9]+}}, 1, implicit $sp +; NO-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}} +; NO-IMPLICIT-SP-NOT: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp +; NO-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1 +; NO-IMPLICIT-SP-NOT: ExtractElementF64 killed %{{[0-9]+}}, 1, implicit $sp + %conv = fptrunc double %d1 to float + %0 = tail call float @llvm.copysign.f32(float 1.000000e+00, float %conv) + %conv1 = fpext float %0 to double + ret double %conv1 +} + +declare float @llvm.copysign.f32(float, float) Modified: vendor/llvm/dist-release_70/test/CodeGen/Mips/longbranch.ll ============================================================================== --- vendor/llvm/dist-release_70/test/CodeGen/Mips/longbranch.ll Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/longbranch.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -231,16 +231,13 @@ define void @test1(i32 signext %s) { ; MICROMIPSSTATIC: # %bb.0: # %entry ; MICROMIPSSTATIC-NEXT: bnezc $4, $BB0_2 ; MICROMIPSSTATIC-NEXT: # %bb.1: # %entry -; MICROMIPSSTATIC-NEXT: j $BB0_4 -; MICROMIPSSTATIC-NEXT: nop -; MICROMIPSSTATIC-NEXT: $BB0_2: # %entry ; MICROMIPSSTATIC-NEXT: j $BB0_3 ; MICROMIPSSTATIC-NEXT: nop -; MICROMIPSSTATIC-NEXT: $BB0_3: # %then +; MICROMIPSSTATIC-NEXT: $BB0_2: # %then ; MICROMIPSSTATIC-NEXT: lui $1, %hi(x) ; MICROMIPSSTATIC-NEXT: li16 $2, 1 ; MICROMIPSSTATIC-NEXT: sw $2, %lo(x)($1) -; MICROMIPSSTATIC-NEXT: $BB0_4: # %end +; MICROMIPSSTATIC-NEXT: $BB0_3: # %end ; MICROMIPSSTATIC-NEXT: jrc $ra ; ; MICROMIPSR6STATIC-LABEL: test1: Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-b-range.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-b-range.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,98 @@ +; RUN: llc -march=mips -relocation-model=pic -mattr=+micromips \ +; RUN: -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s + +; CHECK-LABEL: foo: +; CHECK-NEXT: 0: 41 a2 00 00 lui $2, 0 +; CHECK-NEXT: 4: 30 42 00 00 addiu $2, $2, 0 +; CHECK-NEXT: 8: 03 22 11 50 addu $2, $2, $25 +; CHECK-NEXT: c: fc 42 00 00 lw $2, 0($2) +; CHECK-NEXT: 10: 69 20 lw16 $2, 0($2) +; CHECK-NEXT: 12: 40 c2 00 14 bgtz $2, 44 +; CHECK-NEXT: 16: 00 00 00 00 nop +; CHECK-NEXT: 1a: 33 bd ff f8 addiu $sp, $sp, -8 +; CHECK-NEXT: 1e: fb fd 00 00 sw $ra, 0($sp) +; CHECK-NEXT: 22: 41 a1 00 01 lui $1, 1 +; CHECK-NEXT: 26: 40 60 00 02 bal 8 +; CHECK-NEXT: 2a: 30 21 04 68 addiu $1, $1, 1128 +; CHECK-NEXT: 2e: 00 3f 09 50 addu $1, $ra, $1 +; CHECK-NEXT: 32: ff fd 00 00 lw $ra, 0($sp) +; CHECK-NEXT: 36: 00 01 0f 3c jr $1 +; CHECK-NEXT: 3a: 33 bd 00 08 addiu $sp, $sp, 8 +; CHECK-NEXT: 3e: 94 00 00 02 b 8 +; CHECK-NEXT: 42: 00 00 00 00 nop +; CHECK-NEXT: 46: 30 20 4e 1f addiu $1, $zero, 19999 +; CHECK-NEXT: 4a: b4 22 00 14 bne $2, $1, 44 +; CHECK-NEXT: 4e: 00 00 00 00 nop +; CHECK-NEXT: 52: 33 bd ff f8 addiu $sp, $sp, -8 +; CHECK-NEXT: 56: fb fd 00 00 sw $ra, 0($sp) +; CHECK-NEXT: 5a: 41 a1 00 01 lui $1, 1 +; CHECK-NEXT: 5e: 40 60 00 02 bal 8 +; CHECK-NEXT: 62: 30 21 04 5c addiu $1, $1, 1116 +; CHECK-NEXT: 66: 00 3f 09 50 addu $1, $ra, $1 +; CHECK-NEXT: 6a: ff fd 00 00 lw $ra, 0($sp) +; CHECK-NEXT: 6e: 00 01 0f 3c jr $1 +; CHECK-NEXT: 72: 33 bd 00 08 addiu $sp, $sp, 8 +; CHECK-NEXT: 76: 30 20 27 0f addiu $1, $zero, 9999 +; CHECK-NEXT: 7a: 94 22 00 14 beq $2, $1, 44 +; CHECK-NEXT: 7e: 00 00 00 00 nop +; CHECK-NEXT: 82: 33 bd ff f8 addiu $sp, $sp, -8 +; CHECK-NEXT: 86: fb fd 00 00 sw $ra, 0($sp) +; CHECK-NEXT: 8a: 41 a1 00 01 lui $1, 1 +; CHECK-NEXT: 8e: 40 60 00 02 bal 8 +; CHECK-NEXT: 92: 30 21 04 2c addiu $1, $1, 1068 +; CHECK-NEXT: 96: 00 3f 09 50 addu $1, $ra, $1 +; CHECK-NEXT: 9a: ff fd 00 00 lw $ra, 0($sp) +; CHECK-NEXT: 9e: 00 01 0f 3c jr $1 +; CHECK-NEXT: a2: 33 bd 00 08 addiu $sp, $sp, 8 + +; CHECK: 10466: 00 00 00 00 nop +; CHECK-NEXT: 1046a: 94 00 00 02 b 8 +; CHECK-NEXT: 1046e: 00 00 00 00 nop +; CHECK-NEXT: 10472: 33 bd ff f8 addiu $sp, $sp, -8 +; CHECK-NEXT: 10476: fb fd 00 00 sw $ra, 0($sp) +; CHECK-NEXT: 1047a: 41 a1 00 01 lui $1, 1 +; CHECK-NEXT: 1047e: 40 60 00 02 bal 8 +; CHECK-NEXT: 10482: 30 21 04 00 addiu $1, $1, 1024 +; CHECK-NEXT: 10486: 00 3f 09 50 addu $1, $ra, $1 +; CHECK-NEXT: 1048a: ff fd 00 00 lw $ra, 0($sp) +; CHECK-NEXT: 1048e: 00 01 0f 3c jr $1 +; CHECK-NEXT: 10492: 33 bd 00 08 addiu $sp, $sp, 8 +; CHECK-NEXT: 10496: 94 00 00 02 b 8 + +@x = external global i32, align 4 + +define void @foo() { + %1 = load i32, i32* @x, align 4 + %2 = icmp sgt i32 %1, 0 + br i1 %2, label %la, label %lf + +la: + switch i32 %1, label %le [ + i32 9999, label %lb + i32 19999, label %lc + ] + +lb: + tail call void asm sideeffect ".space 0", ""() + br label %le + +lc: + tail call void asm sideeffect ".space 0", ""() + br label %le + +le: + tail call void asm sideeffect ".space 66500", ""() + br label %lg + +lf: + tail call void asm sideeffect ".space 0", ""() + br label %lg + +lg: + tail call void asm sideeffect ".space 0", ""() + br label %li + +li: + tail call void asm sideeffect ".space 0", ""() + ret void +} Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,37 @@ +; RUN: llc -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -O3 -filetype=obj < %s | llvm-objdump -s -j .gcc_except_table - | FileCheck %s + +; CHECK: Contents of section .gcc_except_table: +; CHECK-NEXT: 0000 ff9b1501 0c011100 00110e1f 011f1800 +; CHECK-NEXT: 0010 00010000 00000000 + +@_ZTIi = external constant i8* + +define dso_local i32 @main() local_unnamed_addr norecurse personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +entry: + %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind + %0 = bitcast i8* %exception.i to i32* + store i32 5, i32* %0, align 16 + invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn + to label %.noexc unwind label %return + +.noexc: + unreachable + +return: + %1 = landingpad { i8*, i32 } + catch i8* null + %2 = extractvalue { i8*, i32 } %1, 0 + %3 = tail call i8* @__cxa_begin_catch(i8* %2) nounwind + tail call void @__cxa_end_catch() + ret i32 0 +} + +declare i32 @__gxx_personality_v0(...) + +declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr + +declare void @__cxa_end_catch() local_unnamed_addr + +declare i8* @__cxa_allocate_exception(i32) local_unnamed_addr + +declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-mtc-mfc.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-mtc-mfc.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -show-mc-encoding < %s | FileCheck --check-prefix=MM2 %s +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \ +; RUN: -show-mc-encoding < %s | FileCheck --check-prefix=MM6 %s + +define double @foo(double %a, double %b) { +; MM2-LABEL: foo: +; MM2: # %bb.0: # %entry +; MM2-NEXT: mov.d $f0, $f12 # encoding: [0x54,0x0c,0x20,0x7b] +; MM2-NEXT: mtc1 $zero, $f2 # encoding: [0x54,0x02,0x28,0x3b] +; MM2-NEXT: mthc1 $zero, $f2 # encoding: [0x54,0x02,0x38,0x3b] +; MM2-NEXT: c.ule.d $f12, $f2 # encoding: [0x54,0x4c,0x05,0xfc] +; MM2-NEXT: bc1t $BB0_2 # encoding: [0x43,0xa0,A,A] +; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_PC16_S1 +; MM2-NEXT: nop # encoding: [0x00,0x00,0x00,0x00] +; MM2-NEXT: # %bb.1: # %entry +; MM2-NEXT: j $BB0_2 # encoding: [0b110101AA,A,A,A] +; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_26_S1 +; MM2-NEXT: nop # encoding: [0x00,0x00,0x00,0x00] +; MM2-NEXT: $BB0_2: # %return +; MM2-NEXT: jrc $ra # encoding: [0x45,0xbf] +; +; MM6-LABEL: foo: +; MM6: # %bb.0: # %entry +; MM6-NEXT: mov.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x06] +; MM6-NEXT: mtc1 $zero, $f1 # encoding: [0x54,0x01,0x28,0x3b] +; MM6-NEXT: mthc1 $zero, $f1 # encoding: [0x54,0x01,0x38,0x3b] +; MM6-NEXT: cmp.ule.d $f1, $f12, $f1 # encoding: [0x54,0x2c,0x09,0xd5] +; MM6-NEXT: mfc1 $2, $f1 # encoding: [0x54,0x41,0x20,0x3b] +; MM6-NEXT: andi16 $2, $2, 1 # encoding: [0x2d,0x21] +; MM6-NEXT: jrc $ra # encoding: [0x45,0xbf] +entry: + %cmp = fcmp ogt double %a, 0.000000e+00 + br i1 %cmp, label %if.end, label %if.else + +if.else: + br label %return + +if.end: + %mul = fmul double %a, 2.000000e+00 + br label %return + +return: + ret double %a +} *** DIFF OUTPUT TRUNCATED AT 1000 LINES *** From owner-svn-src-vendor@freebsd.org Sat Dec 1 15:41:58 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 9B078131AB48; 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Sat, 1 Dec 2018 15:41:54 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201812011541.wB1Ffsqv012411@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 1 Dec 2018 15:41:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341370 - vendor/libc++/libc++-release_70-r348011 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/libc++/libc++-release_70-r348011 X-SVN-Commit-Revision: 341370 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 7EBB286E96 X-Spamd-Result: default: False [-0.13 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.45)[-0.452,0]; NEURAL_SPAM_LONG(0.28)[0.278,0]; NEURAL_SPAM_MEDIUM(0.04)[0.040,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2018 15:41:58 -0000 Author: dim Date: Sat Dec 1 15:41:54 2018 New Revision: 341370 URL: https://svnweb.freebsd.org/changeset/base/341370 Log: Tag libc++ release_70 branch r348011. Added: vendor/libc++/libc++-release_70-r348011/ - copied from r341369, vendor/libc++/dist-release_70/ From owner-svn-src-vendor@freebsd.org Sat Dec 1 15:41:58 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 7F9C8131AB47; Sat, 1 Dec 2018 15:41:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4A6C486E8C; Sat, 1 Dec 2018 15:41:55 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 7919B19C00; Sat, 1 Dec 2018 15:41:51 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wB1FfpqK012363; Sat, 1 Dec 2018 15:41:51 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wB1FfpHo012362; Sat, 1 Dec 2018 15:41:51 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201812011541.wB1FfpHo012362@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 1 Dec 2018 15:41:51 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341369 - vendor/compiler-rt/compiler-rt-release_70-r348011 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/compiler-rt/compiler-rt-release_70-r348011 X-SVN-Commit-Revision: 341369 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 4A6C486E8C X-Spamd-Result: default: False [-0.13 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.45)[-0.452,0]; NEURAL_SPAM_LONG(0.28)[0.278,0]; NEURAL_SPAM_MEDIUM(0.04)[0.040,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2018 15:41:58 -0000 Author: dim Date: Sat Dec 1 15:41:51 2018 New Revision: 341369 URL: https://svnweb.freebsd.org/changeset/base/341369 Log: Tag compiler-rt release_70 branch r348011. Added: vendor/compiler-rt/compiler-rt-release_70-r348011/ - copied from r341368, vendor/compiler-rt/dist-release_70/ From owner-svn-src-vendor@freebsd.org Sat Dec 1 15:41:55 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 51A56131AB3D; Sat, 1 Dec 2018 15:41:55 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 3487586D93; Sat, 1 Dec 2018 15:41:46 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 7F35D19BF2; Sat, 1 Dec 2018 15:41:45 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wB1FfjPr012269; Sat, 1 Dec 2018 15:41:45 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wB1FfegM012247; Sat, 1 Dec 2018 15:41:40 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201812011541.wB1FfegM012247@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 1 Dec 2018 15:41:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341367 - in vendor/clang/dist-release_70: include/clang/Basic lib/CodeGen lib/Driver/ToolChains/Arch lib/Headers lib/Sema lib/Serialization test/CodeGen test/CoverageMapping test/Drive... X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/clang/dist-release_70: include/clang/Basic lib/CodeGen lib/Driver/ToolChains/Arch lib/Headers lib/Sema lib/Serialization test/CodeGen test/CoverageMapping test/Driver test/Frontend test/Sema... X-SVN-Commit-Revision: 341367 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 3487586D93 X-Spamd-Result: default: False [0.31 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.42)[-0.417,0]; NEURAL_SPAM_LONG(0.42)[0.418,0]; NEURAL_SPAM_MEDIUM(0.31)[0.312,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2018 15:41:55 -0000 Author: dim Date: Sat Dec 1 15:41:40 2018 New Revision: 341367 URL: https://svnweb.freebsd.org/changeset/base/341367 Log: Vendor import of clang release_70 branch r348011: https://llvm.org/svn/llvm-project/cfe/branches/release_70@348011 Added: vendor/clang/dist-release_70/test/SemaOpenCL/extension-begin.h (contents, props changed) Modified: vendor/clang/dist-release_70/include/clang/Basic/AttrDocs.td vendor/clang/dist-release_70/include/clang/Basic/DiagnosticFrontendKinds.td vendor/clang/dist-release_70/include/clang/Basic/DiagnosticSemaKinds.td vendor/clang/dist-release_70/lib/CodeGen/CodeGenModule.cpp vendor/clang/dist-release_70/lib/CodeGen/CoverageMappingGen.cpp vendor/clang/dist-release_70/lib/Driver/ToolChains/Arch/PPC.cpp vendor/clang/dist-release_70/lib/Driver/ToolChains/Arch/PPC.h vendor/clang/dist-release_70/lib/Headers/altivec.h vendor/clang/dist-release_70/lib/Sema/SemaInit.cpp vendor/clang/dist-release_70/lib/Serialization/ASTWriter.cpp vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-altivec.c vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-quadword.c vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-vsx.c vendor/clang/dist-release_70/test/CoverageMapping/macros.c vendor/clang/dist-release_70/test/Driver/openbsd.c vendor/clang/dist-release_70/test/Frontend/warning-stdlibcxx-darwin.cpp vendor/clang/dist-release_70/test/Sema/attr-ifunc.c vendor/clang/dist-release_70/test/SemaCXX/sourceranges.cpp vendor/clang/dist-release_70/test/SemaOpenCL/extension-begin.cl vendor/clang/dist-release_70/tools/scan-build/bin/scan-build Modified: vendor/clang/dist-release_70/include/clang/Basic/AttrDocs.td ============================================================================== --- vendor/clang/dist-release_70/include/clang/Basic/AttrDocs.td Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/include/clang/Basic/AttrDocs.td Sat Dec 1 15:41:40 2018 (r341367) @@ -3364,7 +3364,7 @@ def IFuncDocs : Documentation { let Content = [{ ``__attribute__((ifunc("resolver")))`` is used to mark that the address of a declaration should be resolved at runtime by calling a resolver function. -The symbol name of the resolver function is given in quotes. A function with this name (after mangling) must be defined in the current translation unit; it may be ``static``. The resolver function should take no arguments and return a pointer. +The symbol name of the resolver function is given in quotes. A function with this name (after mangling) must be defined in the current translation unit; it may be ``static``. The resolver function should return a pointer. The ``ifunc`` attribute may only be used on a function declaration. A function declaration with an ``ifunc`` attribute is considered to be a definition of the declared entity. The entity must not have weak linkage; for example, in C++, it cannot be applied to a declaration if a definition at that location would be considered inline. Modified: vendor/clang/dist-release_70/include/clang/Basic/DiagnosticFrontendKinds.td ============================================================================== --- vendor/clang/dist-release_70/include/clang/Basic/DiagnosticFrontendKinds.td Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/include/clang/Basic/DiagnosticFrontendKinds.td Sat Dec 1 15:41:40 2018 (r341367) @@ -238,7 +238,7 @@ def warn_option_invalid_ocl_version : Warning< "OpenCL version %0 does not support the option '%1'">, InGroup; def warn_stdlibcxx_not_found : Warning< - "include path for stdlibc++ headers not found; pass '-std=libc++' on the " + "include path for stdlibc++ headers not found; pass '-stdlib=libc++' on the " "command line to use the libc++ standard library instead">, InGroup>; } Modified: vendor/clang/dist-release_70/include/clang/Basic/DiagnosticSemaKinds.td ============================================================================== --- vendor/clang/dist-release_70/include/clang/Basic/DiagnosticSemaKinds.td Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/include/clang/Basic/DiagnosticSemaKinds.td Sat Dec 1 15:41:40 2018 (r341367) @@ -2857,8 +2857,6 @@ def err_cyclic_alias : Error< "%select{alias|ifunc}0 definition is part of a cycle">; def err_ifunc_resolver_return : Error< "ifunc resolver function must return a pointer">; -def err_ifunc_resolver_params : Error< - "ifunc resolver function must have no parameters">; def warn_attribute_wrong_decl_type_str : Warning< "%0 attribute only applies to %1">, InGroup; def err_attribute_wrong_decl_type_str : Error< Modified: vendor/clang/dist-release_70/lib/CodeGen/CodeGenModule.cpp ============================================================================== --- vendor/clang/dist-release_70/lib/CodeGen/CodeGenModule.cpp Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/lib/CodeGen/CodeGenModule.cpp Sat Dec 1 15:41:40 2018 (r341367) @@ -320,8 +320,6 @@ void CodeGenModule::checkAliases() { assert(FTy); if (!FTy->getReturnType()->isPointerTy()) Diags.Report(Location, diag::err_ifunc_resolver_return); - if (FTy->getNumParams()) - Diags.Report(Location, diag::err_ifunc_resolver_params); } llvm::Constant *Aliasee = Alias->getIndirectSymbol(); Modified: vendor/clang/dist-release_70/lib/CodeGen/CoverageMappingGen.cpp ============================================================================== --- vendor/clang/dist-release_70/lib/CodeGen/CoverageMappingGen.cpp Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/lib/CodeGen/CoverageMappingGen.cpp Sat Dec 1 15:41:40 2018 (r341367) @@ -553,6 +553,15 @@ struct CounterCoverageMappingBuilder completeDeferred(Count, DeferredEndLoc); } + size_t locationDepth(SourceLocation Loc) { + size_t Depth = 0; + while (Loc.isValid()) { + Loc = getIncludeOrExpansionLoc(Loc); + Depth++; + } + return Depth; + } + /// Pop regions from the stack into the function's list of regions. /// /// Adds all regions from \c ParentIndex to the top of the stack to the @@ -567,19 +576,41 @@ struct CounterCoverageMappingBuilder SourceLocation EndLoc = Region.hasEndLoc() ? Region.getEndLoc() : RegionStack[ParentIndex].getEndLoc(); + size_t StartDepth = locationDepth(StartLoc); + size_t EndDepth = locationDepth(EndLoc); while (!SM.isWrittenInSameFile(StartLoc, EndLoc)) { - // The region ends in a nested file or macro expansion. Create a - // separate region for each expansion. - SourceLocation NestedLoc = getStartOfFileOrMacro(EndLoc); - assert(SM.isWrittenInSameFile(NestedLoc, EndLoc)); + bool UnnestStart = StartDepth >= EndDepth; + bool UnnestEnd = EndDepth >= StartDepth; + if (UnnestEnd) { + // The region ends in a nested file or macro expansion. Create a + // separate region for each expansion. + SourceLocation NestedLoc = getStartOfFileOrMacro(EndLoc); + assert(SM.isWrittenInSameFile(NestedLoc, EndLoc)); - if (!isRegionAlreadyAdded(NestedLoc, EndLoc)) - SourceRegions.emplace_back(Region.getCounter(), NestedLoc, EndLoc); + if (!isRegionAlreadyAdded(NestedLoc, EndLoc)) + SourceRegions.emplace_back(Region.getCounter(), NestedLoc, EndLoc); - EndLoc = getPreciseTokenLocEnd(getIncludeOrExpansionLoc(EndLoc)); - if (EndLoc.isInvalid()) - llvm::report_fatal_error("File exit not handled before popRegions"); + EndLoc = getPreciseTokenLocEnd(getIncludeOrExpansionLoc(EndLoc)); + if (EndLoc.isInvalid()) + llvm::report_fatal_error("File exit not handled before popRegions"); + EndDepth--; + } + if (UnnestStart) { + // The region begins in a nested file or macro expansion. Create a + // separate region for each expansion. + SourceLocation NestedLoc = getEndOfFileOrMacro(StartLoc); + assert(SM.isWrittenInSameFile(StartLoc, NestedLoc)); + + if (!isRegionAlreadyAdded(StartLoc, NestedLoc)) + SourceRegions.emplace_back(Region.getCounter(), StartLoc, NestedLoc); + + StartLoc = getIncludeOrExpansionLoc(StartLoc); + if (StartLoc.isInvalid()) + llvm::report_fatal_error("File exit not handled before popRegions"); + StartDepth--; + } } + Region.setStartLoc(StartLoc); Region.setEndLoc(EndLoc); MostRecentLocation = EndLoc; Modified: vendor/clang/dist-release_70/lib/Driver/ToolChains/Arch/PPC.cpp ============================================================================== --- vendor/clang/dist-release_70/lib/Driver/ToolChains/Arch/PPC.cpp Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/lib/Driver/ToolChains/Arch/PPC.cpp Sat Dec 1 15:41:40 2018 (r341367) @@ -107,15 +107,19 @@ void ppc::getPPCTargetFeatures(const Driver &D, const if (FloatABI == ppc::FloatABI::Soft) Features.push_back("-hard-float"); - ppc::ReadGOTPtrMode ReadGOT = ppc::getPPCReadGOTPtrMode(D, Args); + ppc::ReadGOTPtrMode ReadGOT = ppc::getPPCReadGOTPtrMode(D, Triple, Args); if (ReadGOT == ppc::ReadGOTPtrMode::SecurePlt) Features.push_back("+secure-plt"); } -ppc::ReadGOTPtrMode ppc::getPPCReadGOTPtrMode(const Driver &D, const ArgList &Args) { +ppc::ReadGOTPtrMode ppc::getPPCReadGOTPtrMode(const Driver &D, const llvm::Triple &Triple, + const ArgList &Args) { if (Args.getLastArg(options::OPT_msecure_plt)) return ppc::ReadGOTPtrMode::SecurePlt; - return ppc::ReadGOTPtrMode::Bss; + if (Triple.isOSOpenBSD()) + return ppc::ReadGOTPtrMode::SecurePlt; + else + return ppc::ReadGOTPtrMode::Bss; } ppc::FloatABI ppc::getPPCFloatABI(const Driver &D, const ArgList &Args) { Modified: vendor/clang/dist-release_70/lib/Driver/ToolChains/Arch/PPC.h ============================================================================== --- vendor/clang/dist-release_70/lib/Driver/ToolChains/Arch/PPC.h Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/lib/Driver/ToolChains/Arch/PPC.h Sat Dec 1 15:41:40 2018 (r341367) @@ -38,7 +38,7 @@ FloatABI getPPCFloatABI(const Driver &D, const llvm::o std::string getPPCTargetCPU(const llvm::opt::ArgList &Args); const char *getPPCAsmModeForCPU(StringRef Name); -ReadGOTPtrMode getPPCReadGOTPtrMode(const Driver &D, +ReadGOTPtrMode getPPCReadGOTPtrMode(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args); void getPPCTargetFeatures(const Driver &D, const llvm::Triple &Triple, Modified: vendor/clang/dist-release_70/lib/Headers/altivec.h ============================================================================== --- vendor/clang/dist-release_70/lib/Headers/altivec.h Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/lib/Headers/altivec.h Sat Dec 1 15:41:40 2018 (r341367) @@ -16353,67 +16353,82 @@ vec_revb(vector unsigned __int128 __a) { /* vec_xl */ +typedef vector signed char unaligned_vec_schar __attribute__((aligned(1))); +typedef vector unsigned char unaligned_vec_uchar __attribute__((aligned(1))); +typedef vector signed short unaligned_vec_sshort __attribute__((aligned(1))); +typedef vector unsigned short unaligned_vec_ushort __attribute__((aligned(1))); +typedef vector signed int unaligned_vec_sint __attribute__((aligned(1))); +typedef vector unsigned int unaligned_vec_uint __attribute__((aligned(1))); +typedef vector float unaligned_vec_float __attribute__((aligned(1))); + static inline __ATTRS_o_ai vector signed char vec_xl(signed long long __offset, signed char *__ptr) { - return *(vector signed char *)(__ptr + __offset); + return *(unaligned_vec_schar *)(__ptr + __offset); } static inline __ATTRS_o_ai vector unsigned char vec_xl(signed long long __offset, unsigned char *__ptr) { - return *(vector unsigned char *)(__ptr + __offset); + return *(unaligned_vec_uchar*)(__ptr + __offset); } static inline __ATTRS_o_ai vector signed short vec_xl(signed long long __offset, signed short *__ptr) { - return *(vector signed short *)(__ptr + __offset); + return *(unaligned_vec_sshort *)(__ptr + __offset); } static inline __ATTRS_o_ai vector unsigned short vec_xl(signed long long __offset, unsigned short *__ptr) { - return *(vector unsigned short *)(__ptr + __offset); + return *(unaligned_vec_ushort *)(__ptr + __offset); } static inline __ATTRS_o_ai vector signed int vec_xl(signed long long __offset, signed int *__ptr) { - return *(vector signed int *)(__ptr + __offset); + return *(unaligned_vec_sint *)(__ptr + __offset); } static inline __ATTRS_o_ai vector unsigned int vec_xl(signed long long __offset, unsigned int *__ptr) { - return *(vector unsigned int *)(__ptr + __offset); + return *(unaligned_vec_uint *)(__ptr + __offset); } static inline __ATTRS_o_ai vector float vec_xl(signed long long __offset, float *__ptr) { - return *(vector float *)(__ptr + __offset); + return *(unaligned_vec_float *)(__ptr + __offset); } #ifdef __VSX__ +typedef vector signed long long unaligned_vec_sll __attribute__((aligned(1))); +typedef vector unsigned long long unaligned_vec_ull __attribute__((aligned(1))); +typedef vector double unaligned_vec_double __attribute__((aligned(1))); + static inline __ATTRS_o_ai vector signed long long vec_xl(signed long long __offset, signed long long *__ptr) { - return *(vector signed long long *)(__ptr + __offset); + return *(unaligned_vec_sll *)(__ptr + __offset); } static inline __ATTRS_o_ai vector unsigned long long vec_xl(signed long long __offset, unsigned long long *__ptr) { - return *(vector unsigned long long *)(__ptr + __offset); + return *(unaligned_vec_ull *)(__ptr + __offset); } static inline __ATTRS_o_ai vector double vec_xl(signed long long __offset, double *__ptr) { - return *(vector double *)(__ptr + __offset); + return *(unaligned_vec_double *)(__ptr + __offset); } #endif #if defined(__POWER8_VECTOR__) && defined(__powerpc64__) +typedef vector signed __int128 unaligned_vec_si128 __attribute__((aligned(1))); +typedef vector unsigned __int128 unaligned_vec_ui128 + __attribute__((aligned(1))); static inline __ATTRS_o_ai vector signed __int128 vec_xl(signed long long __offset, signed __int128 *__ptr) { - return *(vector signed __int128 *)(__ptr + __offset); + return *(unaligned_vec_si128 *)(__ptr + __offset); } static inline __ATTRS_o_ai vector unsigned __int128 vec_xl(signed long long __offset, unsigned __int128 *__ptr) { - return *(vector unsigned __int128 *)(__ptr + __offset); + return *(unaligned_vec_ui128 *)(__ptr + __offset); } #endif @@ -16498,62 +16513,62 @@ vec_xl_be(signed long long __offset, unsigned __int12 static inline __ATTRS_o_ai void vec_xst(vector signed char __vec, signed long long __offset, signed char *__ptr) { - *(vector signed char *)(__ptr + __offset) = __vec; + *(unaligned_vec_schar *)(__ptr + __offset) = __vec; } static inline __ATTRS_o_ai void vec_xst(vector unsigned char __vec, signed long long __offset, unsigned char *__ptr) { - *(vector unsigned char *)(__ptr + __offset) = __vec; + *(unaligned_vec_uchar *)(__ptr + __offset) = __vec; } static inline __ATTRS_o_ai void vec_xst(vector signed short __vec, signed long long __offset, signed short *__ptr) { - *(vector signed short *)(__ptr + __offset) = __vec; + *(unaligned_vec_sshort *)(__ptr + __offset) = __vec; } static inline __ATTRS_o_ai void vec_xst(vector unsigned short __vec, signed long long __offset, unsigned short *__ptr) { - *(vector unsigned short *)(__ptr + __offset) = __vec; + *(unaligned_vec_ushort *)(__ptr + __offset) = __vec; } static inline __ATTRS_o_ai void vec_xst(vector signed int __vec, signed long long __offset, signed int *__ptr) { - *(vector signed int *)(__ptr + __offset) = __vec; + *(unaligned_vec_sint *)(__ptr + __offset) = __vec; } static inline __ATTRS_o_ai void vec_xst(vector unsigned int __vec, signed long long __offset, unsigned int *__ptr) { - *(vector unsigned int *)(__ptr + __offset) = __vec; + *(unaligned_vec_uint *)(__ptr + __offset) = __vec; } static inline __ATTRS_o_ai void vec_xst(vector float __vec, signed long long __offset, float *__ptr) { - *(vector float *)(__ptr + __offset) = __vec; + *(unaligned_vec_float *)(__ptr + __offset) = __vec; } #ifdef __VSX__ static inline __ATTRS_o_ai void vec_xst(vector signed long long __vec, signed long long __offset, signed long long *__ptr) { - *(vector signed long long *)(__ptr + __offset) = __vec; + *(unaligned_vec_sll *)(__ptr + __offset) = __vec; } static inline __ATTRS_o_ai void vec_xst(vector unsigned long long __vec, signed long long __offset, unsigned long long *__ptr) { - *(vector unsigned long long *)(__ptr + __offset) = __vec; + *(unaligned_vec_ull *)(__ptr + __offset) = __vec; } static inline __ATTRS_o_ai void vec_xst(vector double __vec, signed long long __offset, double *__ptr) { - *(vector double *)(__ptr + __offset) = __vec; + *(unaligned_vec_double *)(__ptr + __offset) = __vec; } #endif @@ -16561,13 +16576,13 @@ static inline __ATTRS_o_ai void vec_xst(vector double static inline __ATTRS_o_ai void vec_xst(vector signed __int128 __vec, signed long long __offset, signed __int128 *__ptr) { - *(vector signed __int128 *)(__ptr + __offset) = __vec; + *(unaligned_vec_si128 *)(__ptr + __offset) = __vec; } static inline __ATTRS_o_ai void vec_xst(vector unsigned __int128 __vec, signed long long __offset, unsigned __int128 *__ptr) { - *(vector unsigned __int128 *)(__ptr + __offset) = __vec; + *(unaligned_vec_ui128 *)(__ptr + __offset) = __vec; } #endif Modified: vendor/clang/dist-release_70/lib/Sema/SemaInit.cpp ============================================================================== --- vendor/clang/dist-release_70/lib/Sema/SemaInit.cpp Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/lib/Sema/SemaInit.cpp Sat Dec 1 15:41:40 2018 (r341367) @@ -6092,7 +6092,10 @@ PerformConstructorInitialization(Sema &S, TypeSourceInfo *TSInfo = Entity.getTypeSourceInfo(); if (!TSInfo) TSInfo = S.Context.getTrivialTypeSourceInfo(Entity.getType(), Loc); - SourceRange ParenOrBraceRange = Kind.getParenOrBraceRange(); + SourceRange ParenOrBraceRange = + (Kind.getKind() == InitializationKind::IK_DirectList) + ? SourceRange(LBraceLoc, RBraceLoc) + : Kind.getParenOrBraceRange(); if (auto *Shadow = dyn_cast( Step.Function.FoundDecl.getDecl())) { Modified: vendor/clang/dist-release_70/lib/Serialization/ASTWriter.cpp ============================================================================== --- vendor/clang/dist-release_70/lib/Serialization/ASTWriter.cpp Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/lib/Serialization/ASTWriter.cpp Sat Dec 1 15:41:40 2018 (r341367) @@ -5022,12 +5022,15 @@ ASTFileSignature ASTWriter::WriteASTCore(Sema &SemaRef WriteFPPragmaOptions(SemaRef.getFPOptions()); WriteOpenCLExtensions(SemaRef); WriteOpenCLExtensionTypes(SemaRef); - WriteOpenCLExtensionDecls(SemaRef); WriteCUDAPragmas(SemaRef); // If we're emitting a module, write out the submodule information. if (WritingModule) WriteSubmodules(WritingModule); + + // We need to have information about submodules to correctly deserialize + // decls from OpenCLExtensionDecls block + WriteOpenCLExtensionDecls(SemaRef); Stream.EmitRecord(SPECIAL_TYPES, SpecialTypes); Modified: vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-altivec.c ============================================================================== --- vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-altivec.c Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-altivec.c Sat Dec 1 15:41:40 2018 (r341367) @@ -9338,32 +9338,32 @@ void test9() { // CHECK-LABEL: define void @test9 // CHECK-LE-LABEL: define void @test9 res_vsc = vec_xl(param_sll, ¶m_sc); - // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16 + // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 res_vuc = vec_xl(param_sll, ¶m_uc); - // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16 + // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 res_vs = vec_xl(param_sll, ¶m_s); - // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16 + // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 res_vus = vec_xl(param_sll, ¶m_us); - // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16 + // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 res_vi = vec_xl(param_sll, ¶m_i); - // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 16 + // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 res_vui = vec_xl(param_sll, ¶m_ui); - // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 16 + // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 res_vf = vec_xl(param_sll, ¶m_f); - // CHECK: load <4 x float>, <4 x float>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <4 x float>, <4 x float>* %{{[0-9]+}}, align 16 + // CHECK: load <4 x float>, <4 x float>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <4 x float>, <4 x float>* %{{[0-9]+}}, align 1 } /* ------------------------------ vec_xst ----------------------------------- */ @@ -9371,32 +9371,32 @@ void test10() { // CHECK-LABEL: define void @test10 // CHECK-LE-LABEL: define void @test10 vec_xst(vsc, param_sll, ¶m_sc); - // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 16 + // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 vec_xst(vuc, param_sll, ¶m_uc); - // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 16 + // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 vec_xst(vs, param_sll, ¶m_s); - // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 16 + // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 vec_xst(vus, param_sll, ¶m_us); - // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 16 + // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 vec_xst(vi, param_sll, ¶m_i); - // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 16 + // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 vec_xst(vui, param_sll, ¶m_ui); - // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 16 + // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 vec_xst(vf, param_sll, ¶m_f); - // CHECK: store <4 x float> %{{[0-9]+}}, <4 x float>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <4 x float> %{{[0-9]+}}, <4 x float>* %{{[0-9]+}}, align 16 + // CHECK: store <4 x float> %{{[0-9]+}}, <4 x float>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <4 x float> %{{[0-9]+}}, <4 x float>* %{{[0-9]+}}, align 1 } /* ----------------------------- vec_xl_be ---------------------------------- */ @@ -9404,35 +9404,35 @@ void test11() { // CHECK-LABEL: define void @test11 // CHECK-LE-LABEL: define void @test11 res_vsc = vec_xl_be(param_sll, ¶m_sc); - // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16 + // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> res_vuc = vec_xl_be(param_sll, ¶m_uc); - // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16 + // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> res_vs = vec_xl_be(param_sll, ¶m_s); - // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16 + // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> res_vus = vec_xl_be(param_sll, ¶m_us); - // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 16 + // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> res_vi = vec_xl_be(param_sll, ¶m_i); - // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 16 + // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %{{[0-9]+}}) res_vui = vec_xl_be(param_sll, ¶m_ui); - // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 16 + // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %{{[0-9]+}}) res_vf = vec_xl_be(param_sll, ¶m_f); - // CHECK: load <4 x float>, <4 x float>* %{{[0-9]+}}, align 16 + // CHECK: load <4 x float>, <4 x float>* %{{[0-9]+}}, align 1 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %{{[0-9]+}}) } @@ -9441,34 +9441,34 @@ void test12() { // CHECK-LABEL: define void @test12 // CHECK-LE-LABEL: define void @test12 vec_xst_be(vsc, param_sll, ¶m_sc); - // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 16 + // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) vec_xst_be(vuc, param_sll, ¶m_uc); - // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 16 + // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) vec_xst_be(vs, param_sll, ¶m_s); - // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 16 + // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) vec_xst_be(vus, param_sll, ¶m_us); - // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 16 + // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) vec_xst_be(vi, param_sll, ¶m_i); - // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 16 + // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, i8* %{{[0-9]+}}) vec_xst_be(vui, param_sll, ¶m_ui); - // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 16 + // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, i8* %{{[0-9]+}}) vec_xst_be(vf, param_sll, ¶m_f); - // CHECK: store <4 x float> %{{[0-9]+}}, <4 x float>* %{{[0-9]+}}, align 16 + // CHECK: store <4 x float> %{{[0-9]+}}, <4 x float>* %{{[0-9]+}}, align 1 // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, i8* %{{[0-9]+}}) } Modified: vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-quadword.c ============================================================================== --- vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-quadword.c Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-quadword.c Sat Dec 1 15:41:40 2018 (r341367) @@ -205,45 +205,45 @@ void test1() { /* vec_xl */ res_vlll = vec_xl(param_sll, ¶m_lll); - // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16 + // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1 // CHECK-PPC: error: call to 'vec_xl' is ambiguous res_vulll = vec_xl(param_sll, ¶m_ulll); - // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16 + // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1 // CHECK-PPC: error: call to 'vec_xl' is ambiguous /* vec_xst */ vec_xst(vlll, param_sll, ¶m_lll); - // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16 + // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1 // CHECK-PPC: error: call to 'vec_xst' is ambiguous vec_xst(vulll, param_sll, ¶m_ulll); - // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16 + // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1 // CHECK-PPC: error: call to 'vec_xst' is ambiguous /* vec_xl_be */ res_vlll = vec_xl_be(param_sll, ¶m_lll); - // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16 + // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1 // CHECK-PPC: error: call to 'vec_xl' is ambiguous res_vulll = vec_xl_be(param_sll, ¶m_ulll); - // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16 - // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16 + // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1 + // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1 // CHECK-PPC: error: call to 'vec_xl' is ambiguous /* vec_xst_be */ vec_xst_be(vlll, param_sll, ¶m_lll); - // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16 + // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1 // CHECK-PPC: error: call to 'vec_xst' is ambiguous vec_xst_be(vulll, param_sll, ¶m_ulll); - // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16 - // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16 + // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1 + // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1 // CHECK-PPC: error: call to 'vec_xst' is ambiguous } Modified: vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-vsx.c ============================================================================== --- vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-vsx.c Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/test/CodeGen/builtins-ppc-vsx.c Sat Dec 1 15:41:40 2018 (r341367) @@ -1637,51 +1637,51 @@ res_vsll = vec_slo(vsll, vsc); // CHECK-LE: @llvm.ppc.altivec.vsro res_vsll = vec_xl(sll, asll); -// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16 -// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16 +// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 +// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 res_vull = vec_xl(sll, aull); -// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16 -// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16 +// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 +// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 res_vd = vec_xl(sll, ad); -// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16 -// CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16 +// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 1 +// CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 1 vec_xst(vsll, sll, asll); -// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16 -// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16 +// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 +// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 vec_xst(vull, sll, aull); -// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16 -// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16 +// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 +// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 vec_xst(vd, sll, ad); -// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16 -// CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16 +// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 1 +// CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 1 res_vsll = vec_xl_be(sll, asll); -// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16 +// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) res_vull = vec_xl_be(sll, aull); -// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16 +// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) res_vd = vec_xl_be(sll, ad); -// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16 +// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 1 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) vec_xst_be(vsll, sll, asll); -// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16 +// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) vec_xst_be(vull, sll, aull); -// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16 +// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) vec_xst_be(vd, sll, ad); -// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16 +// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 1 // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) res_vf = vec_neg(vf); Modified: vendor/clang/dist-release_70/test/CoverageMapping/macros.c ============================================================================== --- vendor/clang/dist-release_70/test/CoverageMapping/macros.c Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/test/CoverageMapping/macros.c Sat Dec 1 15:41:40 2018 (r341367) @@ -4,6 +4,7 @@ #define MACRO_2 bar() #define MACRO_1 return; MACRO_2 #define MACRO_3 MACRO_2 +#define GOTO goto void bar() {} @@ -55,6 +56,15 @@ void func5() { // CHECK-NEXT: File 0, [[@LINE]]:14 -> } // CHECK-NEXT: Expansion,File 1, 6:17 -> 6:24 = #1 // CHECK-NEXT: File 2, 4:17 -> 4:22 = #1 + +// CHECK-NEXT: func6 +void func6(unsigned count) { // CHECK-NEXT: File 0, [[@LINE]]:28 -> [[@LINE+4]]:2 = #0 +begin: // CHECK-NEXT: File 0, [[@LINE]]:1 -> [[@LINE+3]]:2 = #1 + if (count--) // CHECK-NEXT: File 0, [[@LINE]]:9 -> [[@LINE]]:16 = #1 + GOTO begin; // CHECK-NEXT: File 0, [[@LINE]]:9 -> [[@LINE]]:19 = #2 +} +// CHECK-NEXT: Expansion,File 0, [[@LINE-2]]:9 -> [[@LINE-2]]:13 = #2 +// CHECK-NEXT: File 1, 7:14 -> 7:18 = #2 int main(int argc, const char *argv[]) { func(); Modified: vendor/clang/dist-release_70/test/Driver/openbsd.c ============================================================================== --- vendor/clang/dist-release_70/test/Driver/openbsd.c Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/test/Driver/openbsd.c Sat Dec 1 15:41:40 2018 (r341367) @@ -112,3 +112,8 @@ // RUN: | FileCheck -check-prefix=CHECK-ARM-FLOAT-ABI %s // CHECK-ARM-FLOAT-ABI-NOT: "-target-feature" "+soft-float" // CHECK-ARM-FLOAT-ABI: "-target-feature" "+soft-float-abi" + +// Check PowerPC for Secure PLT +// RUN: %clang -target powerpc-unknown-openbsd -### -c %s 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-POWERPC-SECUREPLT %s +// CHECK-POWERPC-SECUREPLT: "-target-feature" "+secure-plt" Modified: vendor/clang/dist-release_70/test/Frontend/warning-stdlibcxx-darwin.cpp ============================================================================== --- vendor/clang/dist-release_70/test/Frontend/warning-stdlibcxx-darwin.cpp Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/test/Frontend/warning-stdlibcxx-darwin.cpp Sat Dec 1 15:41:40 2018 (r341367) @@ -1,5 +1,5 @@ // RUN: %clang -cc1 -triple arm64-apple-ios6.0.0 -isysroot %S/doesnotexist %s 2>&1 | FileCheck %s // RUN: %clang -cc1 -triple arm64-apple-ios6.0.0 -isysroot %S/doesnotexist -stdlib=libc++ %s -verify -// CHECK: include path for stdlibc++ headers not found; pass '-std=libc++' on the command line to use the libc++ standard library instead +// CHECK: include path for stdlibc++ headers not found; pass '-stdlib=libc++' on the command line to use the libc++ standard library instead // expected-no-diagnostics Modified: vendor/clang/dist-release_70/test/Sema/attr-ifunc.c ============================================================================== --- vendor/clang/dist-release_70/test/Sema/attr-ifunc.c Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/test/Sema/attr-ifunc.c Sat Dec 1 15:41:40 2018 (r341367) @@ -27,10 +27,6 @@ void f4_ifunc() {} void f4() __attribute__((ifunc("f4_ifunc"))); //expected-error@-1 {{ifunc resolver function must return a pointer}} -void* f5_ifunc(int i) { return 0; } -void f5() __attribute__((ifunc("f5_ifunc"))); -//expected-error@-1 {{ifunc resolver function must have no parameters}} - #else void f1a() __asm("f1"); void f1a() {} Modified: vendor/clang/dist-release_70/test/SemaCXX/sourceranges.cpp ============================================================================== --- vendor/clang/dist-release_70/test/SemaCXX/sourceranges.cpp Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/test/SemaCXX/sourceranges.cpp Sat Dec 1 15:41:40 2018 (r341367) @@ -52,6 +52,13 @@ void construct() { // CHECK: CXXConstructExpr {{0x[0-9a-fA-F]+}} 'D' 'void (int){{( __attribute__\(\(thiscall\)\))?}}' } +namespace PR38987 { +struct A { A(); }; +template void f() { T{}; } +template void f(); +// CHECK: CXXTemporaryObjectExpr {{.*}} 'PR38987::A':'PR38987::A' +} + void abort() __attribute__((noreturn)); namespace std { Modified: vendor/clang/dist-release_70/test/SemaOpenCL/extension-begin.cl ============================================================================== --- vendor/clang/dist-release_70/test/SemaOpenCL/extension-begin.cl Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/test/SemaOpenCL/extension-begin.cl Sat Dec 1 15:41:40 2018 (r341367) @@ -1,38 +1,30 @@ // Test this without pch. -// RUN: %clang_cc1 %s -DHEADER -DHEADER_USER -triple spir-unknown-unknown -verify -pedantic -fsyntax-only +// RUN: %clang_cc1 %s -triple spir-unknown-unknown -verify -pedantic -fsyntax-only // Test with pch. -// RUN: %clang_cc1 %s -DHEADER -triple spir-unknown-unknown -emit-pch -o %t -verify -pedantic -// RUN: %clang_cc1 %s -DHEADER_USER -triple spir-unknown-unknown -include-pch %t -fsyntax-only -verify -pedantic +// RUN: %clang_cc1 -x cl %S/extension-begin.h -triple spir-unknown-unknown -emit-pch -o %t.pch -pedantic +// RUN: %clang_cc1 %s -triple spir-unknown-unknown -include-pch %t.pch -DIMPLICIT_INCLUDE -DUSE_PCH -fsyntax-only -verify -pedantic -#if defined(HEADER) && !defined(INCLUDED) -#define INCLUDED +// Test with modules +// RUN: rm -rf %t.modules +// RUN: mkdir -p %t.modules +// +// RUN: %clang_cc1 -cl-std=CL1.2 -DIMPLICIT_INCLUDE -include %S/extension-begin.h -triple spir-unknown-unknown -O0 -emit-llvm -o - -fmodules -fimplicit-module-maps -fmodules-cache-path=%t.modules %s -verify -pedantic +// +// RUN: rm -rf %t.modules +// RUN: mkdir -p %t.modules +// +// RUN: %clang_cc1 -cl-std=CL2.0 -DIMPLICIT_INCLUDE -include %S/extension-begin.h -triple spir-unknown-unknown -O0 -emit-llvm -o - -fmodules -fimplicit-module-maps -fmodules-cache-path=%t.modules %s -verify -pedantic -#pragma OPENCL EXTENSION all : begin // expected-warning {{expected 'disable' - ignoring}} -#pragma OPENCL EXTENSION all : end // expected-warning {{expected 'disable' - ignoring}} +#ifndef IMPLICIT_INCLUDE +#include "extension-begin.h" +#endif // IMPLICIT_INCLUDE +#ifndef USE_PCH +// expected-warning@extension-begin.h:4 {{expected 'disable' - ignoring}} +// expected-warning@extension-begin.h:5 {{expected 'disable' - ignoring}} +// expected-warning@extension-begin.h:21 {{OpenCL extension end directive mismatches begin directive - ignoring}} +#endif // USE_PCH -#pragma OPENCL EXTENSION my_ext : begin - -struct A { - int a; -}; - -typedef struct A TypedefOfA; -typedef const TypedefOfA* PointerOfA; - -void f(void); - -__attribute__((overloadable)) void g(long x); - -#pragma OPENCL EXTENSION my_ext : end -#pragma OPENCL EXTENSION my_ext : end // expected-warning {{OpenCL extension end directive mismatches begin directive - ignoring}} - -__attribute__((overloadable)) void g(void); - -#endif // defined(HEADER) && !defined(INCLUDED) - -#ifdef HEADER_USER - #pragma OPENCL EXTENSION my_ext : enable void test_f1(void) { struct A test_A1; @@ -48,9 +40,7 @@ void test_f2(void) { PointerOfA test_A_pointer; // expected-error {{use of type 'PointerOfA' (aka 'const struct A *') requires my_ext extension to be enabled}} f(); // expected-error {{use of declaration 'f' requires my_ext extension to be enabled}} g(0); // expected-error {{no matching function for call to 'g'}} - // expected-note@-26 {{candidate disabled due to OpenCL extension}} - // expected-note@-22 {{candidate function not viable: requires 0 arguments, but 1 was provided}} + // expected-note@extension-begin.h:18 {{candidate disabled due to OpenCL extension}} + // expected-note@extension-begin.h:23 {{candidate function not viable: requires 0 arguments, but 1 was provided}} } - -#endif // HEADER_USER Added: vendor/clang/dist-release_70/test/SemaOpenCL/extension-begin.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/clang/dist-release_70/test/SemaOpenCL/extension-begin.h Sat Dec 1 15:41:40 2018 (r341367) @@ -0,0 +1,26 @@ +#ifndef INCLUDED +#define INCLUDED + +#pragma OPENCL EXTENSION all : begin +#pragma OPENCL EXTENSION all : end + +#pragma OPENCL EXTENSION my_ext : begin + +struct A { + int a; +}; + +typedef struct A TypedefOfA; +typedef const __private TypedefOfA* PointerOfA; + +void f(void); + +__attribute__((overloadable)) void g(long x); + +#pragma OPENCL EXTENSION my_ext : end +#pragma OPENCL EXTENSION my_ext : end + +__attribute__((overloadable)) void g(void); + +#endif // INCLUDED + Modified: vendor/clang/dist-release_70/tools/scan-build/bin/scan-build ============================================================================== --- vendor/clang/dist-release_70/tools/scan-build/bin/scan-build Sat Dec 1 15:41:34 2018 (r341366) +++ vendor/clang/dist-release_70/tools/scan-build/bin/scan-build Sat Dec 1 15:41:40 2018 (r341367) @@ -1192,7 +1192,7 @@ OPTIONS: By default, the exit status of scan-build is the same as the executed build command. Specifying this option causes the exit status of scan-build to be 1 - if it found potential bugs and 0 otherwise. + if it found potential bugs and the exit status of the build itself otherwise. --use-cc [compiler path] --use-cc=[compiler path] @@ -1878,7 +1878,7 @@ if (defined $Options{OutputFormat}) { if ($Options{ExitStatusFoundBugs}) { exit 1 if ($NumBugs > 0); - exit 0; + exit $ExitStatus; } } } From owner-svn-src-vendor@freebsd.org Sat Dec 1 15:41:59 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1DA44131AB4E; Sat, 1 Dec 2018 15:41:59 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id F0C3086EC7; Sat, 1 Dec 2018 15:41:57 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 8ACBB19C08; Sat, 1 Dec 2018 15:41:57 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wB1Ffvsg012458; Sat, 1 Dec 2018 15:41:57 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wB1FfvDp012457; Sat, 1 Dec 2018 15:41:57 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201812011541.wB1FfvDp012457@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 1 Dec 2018 15:41:57 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341371 - vendor/lld/lld-release_70-r348011 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lld/lld-release_70-r348011 X-SVN-Commit-Revision: 341371 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: F0C3086EC7 X-Spamd-Result: default: False [-0.13 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.45)[-0.452,0]; NEURAL_SPAM_LONG(0.28)[0.278,0]; NEURAL_SPAM_MEDIUM(0.04)[0.040,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2018 15:41:59 -0000 Author: dim Date: Sat Dec 1 15:41:57 2018 New Revision: 341371 URL: https://svnweb.freebsd.org/changeset/base/341371 Log: Tag lld release_70 branch r348011. Added: vendor/lld/lld-release_70-r348011/ - copied from r341370, vendor/lld/dist-release_70/ From owner-svn-src-vendor@freebsd.org Sat Dec 1 15:42:01 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 79CD6131AB65; Sat, 1 Dec 2018 15:42:01 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 142D286F0D; Sat, 1 Dec 2018 15:42:01 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 44D1019C0E; Sat, 1 Dec 2018 15:42:00 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wB1Fg0MX012509; Sat, 1 Dec 2018 15:42:00 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wB1Fg06D012507; Sat, 1 Dec 2018 15:42:00 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201812011542.wB1Fg06D012507@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 1 Dec 2018 15:42:00 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341372 - vendor/lldb/dist-release_70/source/Plugins/SymbolFile/DWARF X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lldb/dist-release_70/source/Plugins/SymbolFile/DWARF X-SVN-Commit-Revision: 341372 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 142D286F0D X-Spamd-Result: default: False [-0.04 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.45)[-0.445,0]; NEURAL_SPAM_LONG(0.31)[0.307,0]; NEURAL_SPAM_MEDIUM(0.10)[0.096,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2018 15:42:01 -0000 Author: dim Date: Sat Dec 1 15:41:59 2018 New Revision: 341372 URL: https://svnweb.freebsd.org/changeset/base/341372 Log: Vendor import of lldb release_70 branch r348011: https://llvm.org/svn/llvm-project/lldb/branches/release_70@348011 Modified: vendor/lldb/dist-release_70/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp Modified: vendor/lldb/dist-release_70/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp ============================================================================== --- vendor/lldb/dist-release_70/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp Sat Dec 1 15:41:57 2018 (r341371) +++ vendor/lldb/dist-release_70/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp Sat Dec 1 15:41:59 2018 (r341372) @@ -261,7 +261,11 @@ void DWARFUnit::ExtractDIEsRWLocked() { } if (!m_die_array.empty()) { - lldbassert(!m_first_die || m_first_die == m_die_array.front()); + if (m_first_die) { + // Only needed for the assertion. + m_first_die.SetEmptyChildren(m_die_array.front().GetEmptyChildren()); + lldbassert(m_first_die == m_die_array.front()); + } m_first_die = m_die_array.front(); } From owner-svn-src-vendor@freebsd.org Sat Dec 1 15:42:07 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id B9885131ABE3; Sat, 1 Dec 2018 15:42:07 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 5496D86FAD; Sat, 1 Dec 2018 15:42:07 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 0A19F19C15; Sat, 1 Dec 2018 15:42:03 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wB1Fg2fc012558; Sat, 1 Dec 2018 15:42:02 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wB1Fg2qt012557; Sat, 1 Dec 2018 15:42:02 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201812011542.wB1Fg2qt012557@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 1 Dec 2018 15:42:02 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341373 - vendor/lldb/lldb-release_70-r348011 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lldb/lldb-release_70-r348011 X-SVN-Commit-Revision: 341373 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 5496D86FAD X-Spamd-Result: default: False [-0.13 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.45)[-0.452,0]; NEURAL_SPAM_LONG(0.28)[0.278,0]; NEURAL_SPAM_MEDIUM(0.04)[0.040,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2018 15:42:07 -0000 Author: dim Date: Sat Dec 1 15:42:02 2018 New Revision: 341373 URL: https://svnweb.freebsd.org/changeset/base/341373 Log: Tag lldb release_70 branch r348011. Added: vendor/lldb/lldb-release_70-r348011/ - copied from r341372, vendor/lldb/dist-release_70/ From owner-svn-src-vendor@freebsd.org Sat Dec 1 15:41:56 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 0F64D131AB40; Sat, 1 Dec 2018 15:41:56 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D7F3B86E5F; Sat, 1 Dec 2018 15:41:53 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 7676B19BF8; Sat, 1 Dec 2018 15:41:48 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wB1FfmBe012317; Sat, 1 Dec 2018 15:41:48 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wB1Ffmw7012316; Sat, 1 Dec 2018 15:41:48 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201812011541.wB1Ffmw7012316@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 1 Dec 2018 15:41:48 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341368 - vendor/clang/clang-release_70-r348011 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/clang/clang-release_70-r348011 X-SVN-Commit-Revision: 341368 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: D7F3B86E5F X-Spamd-Result: default: False [-0.13 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.45)[-0.452,0]; NEURAL_SPAM_LONG(0.28)[0.278,0]; NEURAL_SPAM_MEDIUM(0.04)[0.040,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2018 15:41:56 -0000 Author: dim Date: Sat Dec 1 15:41:48 2018 New Revision: 341368 URL: https://svnweb.freebsd.org/changeset/base/341368 Log: Tag clang release_70 branch r348011. Added: vendor/clang/clang-release_70-r348011/ - copied from r341367, vendor/clang/dist-release_70/