Date: Sun, 10 Nov 2019 02:42:47 +0000 From: bugzilla-noreply@freebsd.org To: bugs@FreeBSD.org Subject: [Bug 233405] sparc64: DWARF unwinder required for GCC 4.2.1 retirement Message-ID: <bug-233405-227-xFz5IBCmeH@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-233405-227@https.bugs.freebsd.org/bugzilla/> References: <bug-233405-227@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D233405 --- Comment #9 from Conrad Meyer <cem@freebsd.org> --- More "necessary but not sufficient" IAS support (needed to compile libc). --- contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (revision 354566) +++ contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (working co= py) @@ -815,7 +815,7 @@ Parser.getTok().getLoc())= ); Parser.Lex(); // Eat the [ - if (Mnemonic =3D=3D "cas" || Mnemonic =3D=3D "casx" || Mnemonic =3D=3D= "casa") { + if (Mnemonic =3D=3D "cas" || Mnemonic =3D=3D "casx" || Mnemonic =3D=3D= "casa" || Mnemonic =3D=3D "casxa") { SMLoc S =3D Parser.getTok().getLoc(); if (getLexer().getKind() !=3D AsmToken::Percent) return MatchOperand_NoMatch; @@ -1014,7 +1014,22 @@ return true; } - // %fprs is an alias of %asr6. + // %asrN aliases. + if (name.equals("ccr")) { + RegNo =3D ASRRegs[2]; + RegKind =3D SparcOperand::rk_Special; + return true; + } + if (name.equals("asi")) { + RegNo =3D ASRRegs[3]; + RegKind =3D SparcOperand::rk_Special; + return true; + } + if (name.equals("pc")) { + RegNo =3D ASRRegs[5]; + RegKind =3D SparcOperand::rk_Special; + return true; + } if (name.equals("fprs")) { RegNo =3D ASRRegs[6]; RegKind =3D SparcOperand::rk_Special; --- contrib/llvm/lib/Target/Sparc/SparcInstr64Bit.td (revision 354566) +++ contrib/llvm/lib/Target/Sparc/SparcInstr64Bit.td (working copy) @@ -495,6 +495,15 @@ } // Predicates =3D [Is64Bit], Constraints =3D ... +// CASX with explicit ASI; ASM-only, LLVM doesn't grok ASIs, etc, etc. +let Predicates =3D [Is64Bit], Constraints =3D "$swap =3D $rd" in { + def CASXArr: F3_1_asi<3, 0b111110, + (outs I64Regs:$rd), (ins I64Regs:$rs1, i8imm:$asi, + I64Regs:$rs2, I64Regs:$swap), + "casxa [$rs1] $asi, $rs2, $rd", + []>; +} + let Predicates =3D [Is64Bit] in { def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>; --- contrib/llvm/lib/Target/Sparc/SparcInstrAliases.td (revision 354566) +++ contrib/llvm/lib/Target/Sparc/SparcInstrAliases.td (working copy) @@ -477,6 +477,8 @@ // unimp -> unimp 0 def : InstAlias<"unimp", (UNIMP 0), 0>; +// illtrap -> unimp (same instruction, FreeBSD .S uses illtrap) +def : MnemonicAlias<"illtrap", "unimp">; def : MnemonicAlias<"iflush", "flush">; @@ -492,6 +494,9 @@ def : MnemonicAlias<"stuha", "stha">; def : MnemonicAlias<"stsha", "stha">; +// V8 ST renamed to STW in V9 (equivalent) (also: stuw, stsw, but we don't= use those) +def : MnemonicAlias<"stw", "st">; + def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>; def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>; Still runs into linking issues (using LLD) *very* early on (and ld.bfd segfaults). LLD.SPARC doesn't grok symbolic R_SPARC_64 relocations in shar= ed libraries (used by self-referential __dso_handle pointer in CRT), doesn't g= rok GOT, and doesn't grok TLS relocations. This probably needs someone with an intimate knowledge of at least two out of three of: SPARCV9, LLD, and ELF loader/linker model. (Not to mention: time, and caring about 15-20 year old dead hardware.) --=20 You are receiving this mail because: You are the assignee for the bug.=
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