Date: Fri, 29 Sep 1995 11:33:12 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: andreas@knobel.gun.de (Andreas Klemm) Cc: terry@lambert.org, davidg@root.com, mark@grondar.za, hackers@FreeBSD.ORG Subject: Re: make world on FreeBSD-stable impossible. cc1: ... signal 11 Message-ID: <199509291833.LAA15118@phaeton.artisoft.com> In-Reply-To: <199509290635.HAA13907@knobel.gun.de> from "Andreas Klemm" at Sep 29, 95 07:35:26 am
next in thread | previous in thread | raw e-mail | index | archive | help
> Ok, the CPU works perfectly with 75 MHz, It made 2 make worlds and > now I was supping -current the whole night long without problems. > Can I assume, that the CPU should be completely damaged at any > frequency, when I had overheated it ??? No; overheat != cook. > So that it's more likely, that the L2 burst cache is buggy ??? Unless it's a remarked P75 (as has been suggested) and you are screwed. One way to check this *might* be go for clocking it as a P66. If it's the cache, then the memory clock rate went from 33 to 25 when you went to 75, so going to 66 will boost it back to 33 assuming you had a P100. A P90 runs at 90, so you are on the order of 3 times faster. You may be able to clock it as a native 50 or native 60 (was there a native 66, non-doubled?) and start pushing it. Basically, if the cache isn't ~15ns, it won't handle 90MHz. I guess the question is whether the chip can handle this. There's some docs somewhere on a german site that supposedly tell you the contents of Appendix H. The last time I looked, they included the clock multiplier control register, and that may be needed (unless it's an outside pin control -- guess it depends on the MB design). If it doesn't work at 66, you are guaranteed bad cache chips that can't go at 33, but if it works, you still can't tell the difference between overheating or having been sold a P75 with the printing changed. > At what speed is the cache driven ?? Same as CPU speed ? Or has > is the same base frequency as the oscillator (50,60,66 MHz) ??? > I think base*something (1.5,2.0,...). L2 cache should be aternal memory bus speed. Another reason to stay away from clock multiplied chips: L2 cache efficiency goes down expotentially. > The problem is, that a friend of mine has the problem, what to > give back to his distributor, we don't want to have much trouble > with his dealer .... > > Are there test programs available for the 2nd level cache .... > Perhaps souns silly since this is not the kind of memory, > one has directly access to ... But perhaps someone has a good > idea, how to find out precisely, what's damaged and > what not. Not very complex tests. Better tests would require hardware dependencies. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199509291833.LAA15118>