Date: Tue, 14 Jul 2015 15:26:15 +0000 (UTC) From: Warren Block <wblock@FreeBSD.org> To: doc-committers@freebsd.org, svn-doc-all@freebsd.org, svn-doc-head@freebsd.org Subject: svn commit: r46970 - head/en_US.ISO8859-1/htdocs/news/status Message-ID: <201507141526.t6EFQFco064263@repo.freebsd.org>
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Author: wblock Date: Tue Jul 14 15:26:14 2015 New Revision: 46970 URL: https://svnweb.freebsd.org/changeset/doc/46970 Log: Add Konstantin Belousov <kostikbel@gmail.com>'s PCID report. Modified: head/en_US.ISO8859-1/htdocs/news/status/report-2015-04-2015-06.xml Modified: head/en_US.ISO8859-1/htdocs/news/status/report-2015-04-2015-06.xml ============================================================================== --- head/en_US.ISO8859-1/htdocs/news/status/report-2015-04-2015-06.xml Tue Jul 14 15:08:58 2015 (r46969) +++ head/en_US.ISO8859-1/htdocs/news/status/report-2015-04-2015-06.xml Tue Jul 14 15:26:14 2015 (r46970) @@ -1053,4 +1053,62 @@ The FreeBSD Foundation </sponsor> </project> + + <project cat='kern'> + <title>Rewritten PCID Support</title> + + <contact> + <person> + <name> + <given>Konstantin</given> + <common>Belousov</common> + </name> + <email>kib@FreeBSD.org</email> + </person> + </contact> + + <body> + <p>Process-Context Identifiers (PCIDs) is a feature of the TLB + on Intel processors, existing since the Sandy Bridge + micro-architecture introduction. It allows the TLB to + simultaneously cache translation information for several + address spaces, and gives an opportunity for the operating + system context switch code to avoid flushing the TLB on the + process switch. Each cached translation is tagged with some + context identifier, and at context switch time, the operating + system instructs the processor which context is becoming + active. The feature slightly reduces context switch time by + avoiding flush, and more importantly, it reduces the warm-up + period for the thread after a context switch.</p> + + <p>&os; already used PCID, but the existing implementation + had several shortcomings. The <tt>amd64</tt> pmap (the + machine-dependent portion of the virtual memory subsystem) + maintained a bitmap of all CPUs which ever loaded a + translation for the given address space, and avoided TLB flush + on the context switch. The bitmap was used to direct + Inter-Processor Interrupts to the marked CPU when the + operating system needed to perform TLB invalidation. The most + important deficiency of the implementation is the increase of + TLB invalidation IPIs since the bitmap could only grow until + full TLB shootdown is performed. It increases the TLB rate, + which negated the positive effects of avoiding TLB flushes on + large machines. Secondarily, the bitmap maintenance in both + the pmap and the context code was quite complicated, leading + to bugs. These issues resulted in the PCID feature being + disabled by default.</p> + + <p>The new PCID implementation uses an algorithm described in + the U. Vahalia book "UNIX Internals: The New Frontiers". The + algorithm is already used, for example, by the MIPS pmap for + assigning the ASIDs to software-managed TLB entries. The pmap + maintains a per-CPU generation count, which is assigned to the + next unused PCID when the context is activated on CPU. TLB + invalidation includes resetting the generation count, which + causes reallocation of PCID when a context switch is + performed. As result, the new implementation issues exactly + the same amount of shootdown IPIs as pmap which does not + utilize PCID.</p> + </body> + </project> </report>
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