From owner-svn-src-all@FreeBSD.ORG Tue Oct 22 21:16:58 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 7A673290; Tue, 22 Oct 2013 21:16:58 +0000 (UTC) (envelope-from brooks@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 5811F296F; Tue, 22 Oct 2013 21:16:58 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r9MLGwpB052460; Tue, 22 Oct 2013 21:16:58 GMT (envelope-from brooks@svn.freebsd.org) Received: (from brooks@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r9MLGvls052455; Tue, 22 Oct 2013 21:16:57 GMT (envelope-from brooks@svn.freebsd.org) Message-Id: <201310222116.r9MLGvls052455@svn.freebsd.org> From: Brooks Davis Date: Tue, 22 Oct 2013 21:16:57 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r256937 - in head/sys: conf mips/mips X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Oct 2013 21:16:58 -0000 Author: brooks Date: Tue Oct 22 21:16:57 2013 New Revision: 256937 URL: http://svnweb.freebsd.org/changeset/base/256937 Log: MFP4: Change 231031 by brooks@brooks_zenith on 2013/07/11 16:22:08 Turn the unused and uncompilable MIPS_DISABLE_L1_CACHE define in cache.c into an option and when set force I- and D-cache line sizes to 0 (the latter part might be better as a tunable). Fix some casts in an #if 0'd bit of code which attempts to disable L1 cache ops when the cache is coherent. Sponsored by: DARPA/AFRL Modified: head/sys/conf/options.mips head/sys/mips/mips/cache.c head/sys/mips/mips/cpu.c Modified: head/sys/conf/options.mips ============================================================================== --- head/sys/conf/options.mips Tue Oct 22 21:13:02 2013 (r256936) +++ head/sys/conf/options.mips Tue Oct 22 21:16:57 2013 (r256937) @@ -71,6 +71,11 @@ TICK_USE_MALTA_RTC opt_global.h MAXMEM opt_global.h # +# Manual override of cache config +# +MIPS_DISABLE_L1_CACHE opt_global.h + +# # Options that control the Cavium Simple Executive. # OCTEON_MODEL opt_cvmx.h Modified: head/sys/mips/mips/cache.c ============================================================================== --- head/sys/mips/mips/cache.c Tue Oct 22 21:13:02 2013 (r256936) +++ head/sys/mips/mips/cache.c Tue Oct 22 21:16:57 2013 (r256937) @@ -116,11 +116,9 @@ mips_config_cache(struct mips_cpuinfo * #ifdef MIPS_DISABLE_L1_CACHE case 0: - mips_cache_ops.mco_icache_sync_all = cache_noop; - mips_cache_ops.mco_icache_sync_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_icache_sync_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_icache_sync_all = (void (*)(void))cache_noop; + mips_cache_ops.mco_icache_sync_range = cache_noop; + mips_cache_ops.mco_icache_sync_range_index = cache_noop; break; #endif default: @@ -193,20 +191,16 @@ mips_config_cache(struct mips_cpuinfo * #endif #ifdef MIPS_DISABLE_L1_CACHE case 0: - mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; - mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_all = + mips_cache_ops.mco_intern_pdcache_wbinv_all = + (void (*)(void))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_inv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_intern_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; + cache_noop; + mips_cache_ops.mco_pdcache_inv_range = cache_noop; + mips_cache_ops.mco_pdcache_wb_range = cache_noop; + mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; break; #endif default: @@ -222,26 +216,22 @@ mips_config_cache(struct mips_cpuinfo * #ifdef CACHE_DEBUG printf(" Dcache is coherent\n"); #endif - mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_inv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_all = + (void (*)(void))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; + mips_cache_ops.mco_pdcache_inv_range = cache_noop; + mips_cache_ops.mco_pdcache_wb_range = cache_noop; } if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) { #ifdef CACHE_DEBUG printf(" Icache is coherent against Dcache\n"); #endif mips_cache_ops.mco_intern_pdcache_wbinv_all = - cache_noop; + (void (*)(void))cache_noop; mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_intern_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; + cache_noop; + mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; } #endif Modified: head/sys/mips/mips/cpu.c ============================================================================== --- head/sys/mips/mips/cpu.c Tue Oct 22 21:13:02 2013 (r256936) +++ head/sys/mips/mips/cpu.c Tue Oct 22 21:16:57 2013 (r256937) @@ -128,6 +128,9 @@ mips_get_identity(struct mips_cpuinfo *c #endif /* L1 instruction cache. */ +#ifdef MIPS_DISABLE_L1_CACHE + cpuinfo->l1.ic_linesize = 0; +#else tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; if (tmp != 0) { cpuinfo->l1.ic_linesize = 1 << (tmp + 1); @@ -135,8 +138,12 @@ mips_get_identity(struct mips_cpuinfo *c cpuinfo->l1.ic_nsets = 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); } +#endif /* L1 data cache. */ +#ifdef MIPS_DISABLE_L1_CACHE + cpuinfo->l1.dc_linesize = 0; +#else #ifndef CPU_CNMIPS tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; if (tmp != 0) { @@ -173,6 +180,7 @@ mips_get_identity(struct mips_cpuinfo *c /* All Octeon models use 128 byte line size. */ cpuinfo->l1.dc_linesize = 128; #endif +#endif cpuinfo->l1.ic_size = cpuinfo->l1.ic_linesize * cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways;