From owner-freebsd-current@FreeBSD.ORG Fri Jun 16 11:39:20 2006 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id CFE4116A479; Fri, 16 Jun 2006 11:39:20 +0000 (UTC) (envelope-from avg@icyb.net.ua) Received: from citadel.icyb.net.ua (citadel.icyb.net.ua [212.40.38.140]) by mx1.FreeBSD.org (Postfix) with ESMTP id A611043D45; Fri, 16 Jun 2006 11:39:19 +0000 (GMT) (envelope-from avg@icyb.net.ua) Received: from [212.40.38.87] (oddity-e.topspin.kiev.ua [212.40.38.87]) by citadel.icyb.net.ua (8.8.8p3/ICyb-2.3exp) with ESMTP id OAA17074; Fri, 16 Jun 2006 14:39:17 +0300 (EEST) (envelope-from avg@icyb.net.ua) Message-ID: <44929864.4080207@icyb.net.ua> Date: Fri, 16 Jun 2006 14:39:16 +0300 From: Andriy Gapon User-Agent: Thunderbird 1.5.0.4 (X11/20060615) MIME-Version: 1.0 To: John Baldwin References: <1148837064.00534930.1148826605@10.7.7.3> <447C1BBD.5020004@icyb.net.ua> <447D0B5C.3020901@root.org> <200606011504.31635.jhb@freebsd.org> In-Reply-To: <200606011504.31635.jhb@freebsd.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: freebsd-current@freebsd.org, Nate Lawson Subject: Re: Freeze due to performance_cx_lowest=LOW X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jun 2006 11:39:20 -0000 on 01/06/2006 22:04 John Baldwin said the following: > On Tuesday 30 May 2006 23:19, Nate Lawson wrote: >> Andriy Gapon wrote: >>> on 29/05/2006 23:10 Nate Lawson said the following: >>>> disable apic (hint.apic.0.disabled="1"). I isolated this a little while >>>> ago to the change to enable LAPIC timer. However, there is currently no >>>> easy way to disable the LAPIC timer with APIC enabled so you have to >>>> disable APIC. jhb@ and I have been discussing how to do this better but >>>> no easy answers apparently. >>> I am not sure what I am talking about, but is it potentially possible to >>> drive timer system by more than one clock, actively using the most >>> precise of them at any particular moment ? So that if LAPIC timer stops >>> i8254 can be used instead. >> That requires mixed mode delivery -- i8254 on legacy PIC irq and APIC >> mode for other interrupts. jhb@ just killed this and isn't eager to add >> it back. I'll let him explain if he has more to add. > > Namely that it is unreliable and expressly forbidden by the ACPI spec. > Maybe I will say something too ignorant for this list, but is it possible to drive hardclock with two interrupts (I haven't thought yet how, though) and use RTC as the second interrupt source ? I think that RTC/IRQ8 (usually) doesn't have problems associated with 8254 timer/IRQ0 and can be used without mixed mode. -- Andriy Gapon