From nobody Thu Mar 12 15:29:09 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4fWs3b5MHfz6VWML for ; Thu, 12 Mar 2026 15:29:15 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R12" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4fWs3b1nn7z4Gf2 for ; Thu, 12 Mar 2026 15:29:15 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1773329355; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=L38Wy93RcfBsBd58RVYg8ObO2kKhED6wrhJoxDQkMqk=; b=ctSTVod9Z/hSbQezvnLzKsKcZhW11deVlUNjal1hvkH72OucCc3JT6VOREVk+wgZ1JNi87 t8bgVZ5cAIzCLHTZYt74XJt18vuJimjqLQXQ9CAOQej+ZOehrhXomX1yAWCBWjItmGN/TT kW7bFcWW2CiY5VZB6W7esExWIC37rCBLP3vdElmP/rypgU8wFznYP8W6YhxApiT5N94o0x 5C1ta+N3SVWT2XVTePuyDAsxAItzwEXJjV7T5ydBIK1A+D+HIi5Zt1OT65sbQhfp6CpcPE DlXnyEsATpSD9tGO0RtE42mzdVq1IUSZLpuPB7EOqEf2juQ5B5JJGnYXck3B8Q== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1773329355; a=rsa-sha256; cv=none; b=QzTN2MWFWCwUvnEXw7vZyBPc4MKrgE7Htl6Q0dSbNHBZE8xGk7G5pjzbEpc30rQg+NVIca lSd5U9itm0DNQ3IfsfQPy7UmX1x1k1m+AFbZfW4ewuKq3c8762YISAM0l771GcG1U085qc EdGF5hVqgUtBBsePe+rX/Cvvuvbel7a0jFWfHqZHce/Dxbzz93gcomQm6aE6WZJKWmUsxs GPWvP20GHw0cC7i3v4SPA4vk4e3hbRNMiwO/gy2gRUWg6XsYyLMsw8FRoTQZQYnBoG2F2E U1dzXIKJSuUJ99JYaPjy3UEtXR0Yu3du7X8girdJfHSemW43D4nKw+07g1fyJg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1773329355; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=L38Wy93RcfBsBd58RVYg8ObO2kKhED6wrhJoxDQkMqk=; b=gsT12Z6sCem0XzZM+YDPhe9fnG6KHSoJI+HcRCLdIsubuGQ8sxEgrkNxURRnxeNKDVm4X8 pXc0d/5LbGAORgdD4cRKzriTbU4fW5TQ2LjuijFz3s2cfjU8znUkpqVTHig+Ku5FIEYNoY c/4ZO2LLbkKeGC4syXR00C+VcpfQs99XOPtzEHlt2GVWknRGts7tGQ9RWoLEQfPIBM/wIl ts79tECLFvsX8khZZ6w0cQeyv1uWlo2kUpr1mOLYpfg8IOaAxJ3MES9YE0IwzjQIr1HUPl qAqbUw1sixl/KnNqmioNMbCJ5BDJEwaweCQaBjKgavjUO4dXPYcVvfjW5oePIw== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4fWs3b0ntbzrPW for ; Thu, 12 Mar 2026 15:29:15 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 3cf06 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Thu, 12 Mar 2026 15:29:09 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Cc: Paulo Fragoso From: Mitchell Horne Subject: git: ce9aff829e02 - main - hwpmc_amd: fix amd_get_msr() MSR offset for newer counter bases List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: ce9aff829e02c9a21c04eae77a45f2193d1ed5a1 Auto-Submitted: auto-generated Date: Thu, 12 Mar 2026 15:29:09 +0000 Message-Id: <69b2dbc5.3cf06.4ef36fc5@gitrepo.freebsd.org> The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=ce9aff829e02c9a21c04eae77a45f2193d1ed5a1 commit ce9aff829e02c9a21c04eae77a45f2193d1ed5a1 Author: Paulo Fragoso AuthorDate: 2026-03-12 15:21:33 +0000 Commit: Mitchell Horne CommitDate: 2026-03-12 15:29:04 +0000 hwpmc_amd: fix amd_get_msr() MSR offset for newer counter bases The previous code subtracted AMD_PMC_PERFCTR_0 (0xC0010004) from all perfctr MSR addresses to compute a relative offset. This is incorrect for counters using AMD_PMC_CORE_BASE (0xC0010200), AMD_PMC_L3_BASE (0xC0010230), and AMD_PMC_DF_BASE (0xC0010240), producing wrong offsets. Fix by promoting amd_core_npmcs, amd_l3_npmcs, and amd_df_npmcs to static module-level variables and computing the correct flat RDPMC index per AMD BKDG 24594 page 440: ECX 0-5: Core counters 0-5 ECX 6-9: DF counters 0-3 ECX 10-15: L3 Cache counters 0-5 ECX 16-27: DF counters 4-15 ECX > 27: Reserved, returns EINVAL Reviewed by: Ali Mashtizadeh , mhorne Sponsored by: NLINK (https://nlink.com.br), Recife, Brazil Fixes: 37bba2ad92d8 ("hwpmc_amd: Add support for additional counters") Differential Revision: https://reviews.freebsd.org/D55607 --- sys/dev/hwpmc/hwpmc_amd.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/sys/dev/hwpmc/hwpmc_amd.c b/sys/dev/hwpmc/hwpmc_amd.c index cf44f9362a72..c27d93995d59 100644 --- a/sys/dev/hwpmc/hwpmc_amd.c +++ b/sys/dev/hwpmc/hwpmc_amd.c @@ -60,8 +60,8 @@ struct amd_descr { }; static int amd_npmcs; +static int amd_core_npmcs, amd_l3_npmcs, amd_df_npmcs; static struct amd_descr amd_pmcdesc[AMD_NPMCS_MAX]; - struct amd_event_code_map { enum pmc_event pe_ev; /* enum value */ uint16_t pe_code; /* encoded event mask */ @@ -664,10 +664,41 @@ amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) static int amd_get_msr(int ri, uint32_t *msr) { + int df_idx; + KASSERT(ri >= 0 && ri < amd_npmcs, ("[amd,%d] ri %d out of range", __LINE__, ri)); - *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; + /* + * Map counter row index to RDPMC ECX value. + * + * AMD BKDG 24594 rev 3.37, page 440, + * "RDPMC Read Performance-Monitoring Counter": + * ECX 0-5: Core counters 0-5 + * ECX 6-9: DF/Northbridge counters 0-3 + * ECX 10-15: L3 Cache counters 0-5 + * ECX 16-27: DF/Northbridge counters 4-15 + * + * AMD PPR 57930-A0 section 2.1.9, + * "Register Sharing" for DF counter details. + */ + if (ri < amd_core_npmcs) { + /* ECX 0-5: Core counters */ + *msr = ri; + } else if (ri < amd_core_npmcs + amd_l3_npmcs) { + /* ECX 10-15: L3 Cache counters */ + *msr = 10 + (ri - amd_core_npmcs); + } else { + /* ECX 6-9: DF counters 0-3 + * ECX 16-27: DF counters 4-15 */ + df_idx = ri - amd_core_npmcs - amd_l3_npmcs; + if (df_idx < 4) + *msr = 6 + df_idx; + else if (df_idx < 16) + *msr = 16 + (df_idx - 4); + else + return (EINVAL); + } return (0); } @@ -767,7 +798,6 @@ pmc_amd_initialize(void) enum pmc_cputype cputype; int error, i, ncpus, nclasses; int family, model, stepping; - int amd_core_npmcs, amd_l3_npmcs, amd_df_npmcs; struct amd_descr *d; /*