From owner-svn-src-head@freebsd.org Tue Jun 19 16:14:24 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 65376102414A; Tue, 19 Jun 2018 16:14:24 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 12FC968F0C; Tue, 19 Jun 2018 16:14:24 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id E865415E09; Tue, 19 Jun 2018 16:14:23 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5JGENbQ073554; Tue, 19 Jun 2018 16:14:23 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5JGENxd073551; Tue, 19 Jun 2018 16:14:23 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201806191614.w5JGENxd073551@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Tue, 19 Jun 2018 16:14:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r335373 - in head/sys: arm/arm arm64/arm64 X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: in head/sys: arm/arm arm64/arm64 X-SVN-Commit-Revision: 335373 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jun 2018 16:14:24 -0000 Author: andrew Date: Tue Jun 19 16:14:23 2018 New Revision: 335373 URL: https://svnweb.freebsd.org/changeset/base/335373 Log: Move common GIC interrupt numbers to the common header. These are the same across the GICv2 and GICv3 drivers so we only need a single copy of them. Sponsored by: Turing Robotic Industries Modified: head/sys/arm/arm/gic.h head/sys/arm/arm/gic_common.h head/sys/arm64/arm64/gic_v3_reg.h Modified: head/sys/arm/arm/gic.h ============================================================================== --- head/sys/arm/arm/gic.h Tue Jun 19 15:55:21 2018 (r335372) +++ head/sys/arm/arm/gic.h Tue Jun 19 16:14:23 2018 (r335373) @@ -39,12 +39,6 @@ #ifndef _ARM_GIC_H_ #define _ARM_GIC_H_ -#define GIC_FIRST_SGI 0 /* Irqs 0-15 are SGIs/IPIs. */ -#define GIC_LAST_SGI 15 -#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */ -#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ -#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ - #ifdef INTRNG struct arm_gic_range { uint64_t bus; Modified: head/sys/arm/arm/gic_common.h ============================================================================== --- head/sys/arm/arm/gic_common.h Tue Jun 19 15:55:21 2018 (r335372) +++ head/sys/arm/arm/gic_common.h Tue Jun 19 16:14:23 2018 (r335373) @@ -44,6 +44,15 @@ __BUS_ACCESSOR(gic, hw_rev, GIC, HW_REV, u_int); __BUS_ACCESSOR(gic, bus, GIC, BUS, u_int); +/* Software Generated Interrupts */ +#define GIC_FIRST_SGI 0 /* Irqs 0-15 are SGIs/IPIs. */ +#define GIC_LAST_SGI 15 +/* Private Peripheral Interrupts */ +#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */ +#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ +/* Shared Peripheral Interrupts */ +#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ + /* Common register values */ #define GICD_CTLR 0x0000 /* v1 ICDDCR */ #define GICD_TYPER 0x0004 /* v1 ICDICTR */ Modified: head/sys/arm64/arm64/gic_v3_reg.h ============================================================================== --- head/sys/arm64/arm64/gic_v3_reg.h Tue Jun 19 15:55:21 2018 (r335372) +++ head/sys/arm64/arm64/gic_v3_reg.h Tue Jun 19 16:14:23 2018 (r335373) @@ -44,14 +44,7 @@ /* Upper value is determined by LPI max priority */ #define GIC_PRIORITY_MIN (0xFCUL) -/* Numbers for software generated interrupts */ -#define GIC_FIRST_SGI (0) -#define GIC_LAST_SGI (15) -/* Numbers for private peripheral interrupts */ -#define GIC_FIRST_PPI (16) -#define GIC_LAST_PPI (31) -/* Numbers for spared peripheral interrupts */ -#define GIC_FIRST_SPI (32) +/* Numbers for shared peripheral interrupts */ #define GIC_LAST_SPI (1019) /* Numbers for local peripheral interrupts */ #define GIC_FIRST_LPI (8192)