From owner-svn-src-head@FreeBSD.ORG Fri Nov 19 15:00:21 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6CB34106564A; Fri, 19 Nov 2010 15:00:21 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 4199E8FC12; Fri, 19 Nov 2010 15:00:21 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id oAJF0LQ5077796; Fri, 19 Nov 2010 15:00:21 GMT (envelope-from avg@svn.freebsd.org) Received: (from avg@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id oAJF0L7w077792; Fri, 19 Nov 2010 15:00:21 GMT (envelope-from avg@svn.freebsd.org) Message-Id: <201011191500.oAJF0L7w077792@svn.freebsd.org> From: Andriy Gapon Date: Fri, 19 Nov 2010 15:00:21 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r215523 - in head/sys: amd64/include i386/i386 i386/include X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Nov 2010 15:00:21 -0000 Author: avg Date: Fri Nov 19 15:00:20 2010 New Revision: 215523 URL: http://svn.freebsd.org/changeset/base/215523 Log: specialreg.h: add AMD-specific "Hardware Configuration Register" MSR It seems that this MSR has been available in a range of AMD processors families for quite a while now. Note1: not all AMD MSRs that are found in amd64 specialreg.h are also in the i386 version. Note2: perhaps some additional name component is needed to distinguish AMD-specific MSRs. MFC after: 5 days Modified: head/sys/amd64/include/specialreg.h head/sys/i386/i386/initcpu.c head/sys/i386/include/specialreg.h Modified: head/sys/amd64/include/specialreg.h ============================================================================== --- head/sys/amd64/include/specialreg.h Fri Nov 19 14:46:17 2010 (r215522) +++ head/sys/amd64/include/specialreg.h Fri Nov 19 15:00:20 2010 (r215523) @@ -504,6 +504,7 @@ #define MSR_PERFCTR2 0xc0010006 #define MSR_PERFCTR3 0xc0010007 #define MSR_SYSCFG 0xc0010010 +#define MSR_HWCR 0xc0010015 #define MSR_IORRBASE0 0xc0010016 #define MSR_IORRMASK0 0xc0010017 #define MSR_IORRBASE1 0xc0010018 Modified: head/sys/i386/i386/initcpu.c ============================================================================== --- head/sys/i386/i386/initcpu.c Fri Nov 19 14:46:17 2010 (r215522) +++ head/sys/i386/i386/initcpu.c Fri Nov 19 15:00:20 2010 (r215523) @@ -672,7 +672,7 @@ initializecpu(void) (cpu_id & ~0xf) == 0x670 || (cpu_id & ~0xf) == 0x680)) { u_int regs[4]; - wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000); + wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); do_cpuid(1, regs); cpu_feature = regs[3]; } Modified: head/sys/i386/include/specialreg.h ============================================================================== --- head/sys/i386/include/specialreg.h Fri Nov 19 14:46:17 2010 (r215522) +++ head/sys/i386/include/specialreg.h Fri Nov 19 15:00:20 2010 (r215523) @@ -554,7 +554,8 @@ #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ /* AMD64 MSR's */ -#define MSR_EFER 0xc0000080 /* extended features */ +#define MSR_EFER 0xc0000080 /* extended features */ +#define MSR_HWCR 0xc0010015 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ #define MSR_MC0_CTL_MASK 0xc0010044