Date: Sun, 13 Apr 1997 09:05:16 +0930 (CST) From: Michael Smith <msmith@atrad.adelaide.edu.au> To: terry@lambert.org (Terry Lambert) Cc: thorpej@nas.nasa.gov, langfod@dihelix.com, ejs@bfd.com, hasty@rah.star-gate.com, steve@visint.co.uk, louie@transsys.com, michaelh@cet.co.jp, avalon@coombs.anu.edu.au, terry@lambert.org, hackers@freebsd.org Subject: Re: 430TX ? Message-ID: <199704122335.JAA16806@genesis.atrad.adelaide.edu.au> In-Reply-To: <199704121845.LAA15464@phaeton.artisoft.com> from Terry Lambert at "Apr 12, 97 11:45:20 am"
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Terry Lambert stands accused of saying: > > > > ...1-2M is a small cache, IMO. We have an Alpha with a 4M cache, and are > > getting some with 16M cache.. > > The real pain is that no one seems to be doing anything about getting > SRAM density up... the only benefit DRAM has over SRAM is its density... > everything else favors SRAM. a) bollocks. SRAM density is moving along quite nicely, and it's becoming much more cost-effective. We're down from $200 for a 512x16 stick to about $60 for two 512Kx8 parts, and we expect to be paying under $10 each for them with the next generation of parts due soon. b) DRAM has the massive advantage that a DRAM memory cell is _very_ small. SRAM does not have this advantage. > Terry Lambert -- ]] Mike Smith, Software Engineer msmith@gsoft.com.au [[ ]] Genesis Software genesis@gsoft.com.au [[ ]] High-speed data acquisition and (GSM mobile) 0411-222-496 [[ ]] realtime instrument control. (ph) +61-8-8267-3493 [[ ]] Unix hardware collector. "Where are your PEZ?" The Tick [[
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