From owner-svn-src-head@freebsd.org Tue Dec 20 22:08:38 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 10278C768B8; Tue, 20 Dec 2016 22:08:38 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id BAAC3B76; Tue, 20 Dec 2016 22:08:37 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uBKM8ata090814; Tue, 20 Dec 2016 22:08:36 GMT (envelope-from cem@FreeBSD.org) Received: (from cem@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uBKM8aH9090812; Tue, 20 Dec 2016 22:08:36 GMT (envelope-from cem@FreeBSD.org) Message-Id: <201612202208.uBKM8aH9090812@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cem set sender to cem@FreeBSD.org using -f From: "Conrad E. Meyer" Date: Tue, 20 Dec 2016 22:08:36 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r310340 - in head/sys/dev: ichiic sdhci X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Dec 2016 22:08:38 -0000 Author: cem Date: Tue Dec 20 22:08:36 2016 New Revision: 310340 URL: https://svnweb.freebsd.org/changeset/base/310340 Log: Add Braswell PCI IDs for Intel Cherryview Submitted by: Johannes Lundberg Reviewed by: jhb Differential Revision: https://reviews.freebsd.org/D8861 Modified: head/sys/dev/ichiic/ig4_pci.c head/sys/dev/sdhci/sdhci_pci.c Modified: head/sys/dev/ichiic/ig4_pci.c ============================================================================== --- head/sys/dev/ichiic/ig4_pci.c Tue Dec 20 21:58:43 2016 (r310339) +++ head/sys/dev/ichiic/ig4_pci.c Tue Dec 20 22:08:36 2016 (r310340) @@ -68,6 +68,12 @@ static int ig4iic_pci_detach(device_t de #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 +#define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 +#define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 +#define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 +#define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 +#define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 +#define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 static int ig4iic_pci_probe(device_t dev) @@ -79,6 +85,24 @@ ig4iic_pci_probe(device_t dev) case PCI_CHIP_LYNXPT_LP_I2C_2: device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-2"); break; + case PCI_CHIP_BRASWELL_I2C_1: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 1"); + break; + case PCI_CHIP_BRASWELL_I2C_2: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 2"); + break; + case PCI_CHIP_BRASWELL_I2C_3: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 3"); + break; + case PCI_CHIP_BRASWELL_I2C_5: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 5"); + break; + case PCI_CHIP_BRASWELL_I2C_6: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 6"); + break; + case PCI_CHIP_BRASWELL_I2C_7: + device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 7"); + break; default: return (ENXIO); } Modified: head/sys/dev/sdhci/sdhci_pci.c ============================================================================== --- head/sys/dev/sdhci/sdhci_pci.c Tue Dec 20 21:58:43 2016 (r310339) +++ head/sys/dev/sdhci/sdhci_pci.c Tue Dec 20 22:08:36 2016 (r310340) @@ -107,6 +107,8 @@ static const struct sdhci_device { SDHCI_QUIRK_RESET_AFTER_REQUEST }, { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, + { 0x22948086, 0xffff, "Braswell Storage Cluster Control MMC Port", + 0 }, { 0, 0xffff, NULL, 0 } };