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From: Scott Long <scottl@FreeBSD.org>
Date: Sat, 2 Aug 2008 13:04:26 +0000 (UTC)
To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org
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Subject: cvs commit: src/sys/dev/ciss ciss.c cissreg.h
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scottl      2008-08-02 13:04:26 UTC

  FreeBSD src repository

  Modified files:
    sys/dev/ciss         ciss.c cissreg.h 
  Log:
  SVN rev 181177 on 2008-08-02 13:04:26Z by scottl
  
  Correctly set the interrupt enable and disable bits.  The previous
  code interfered with Performant mode and legacy interrupts.  Also
  remove a register read operation on the Simplq code that was
  effectively a time-wasting no-op.
  
  Revision  Changes    Path
  1.91      +0 -4      src/sys/dev/ciss/ciss.c
  1.18      +11 -11    src/sys/dev/ciss/cissreg.h