From owner-svn-src-head@FreeBSD.ORG Fri May 27 23:18:41 2011 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id DA3FD106564A; Fri, 27 May 2011 23:18:41 +0000 (UTC) (envelope-from marcel@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id B121A8FC08; Fri, 27 May 2011 23:18:41 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p4RNIfWf057178; Fri, 27 May 2011 23:18:41 GMT (envelope-from marcel@svn.freebsd.org) Received: (from marcel@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p4RNIfeb057176; Fri, 27 May 2011 23:18:41 GMT (envelope-from marcel@svn.freebsd.org) Message-Id: <201105272318.p4RNIfeb057176@svn.freebsd.org> From: Marcel Moolenaar Date: Fri, 27 May 2011 23:18:41 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r222392 - head/sys/powerpc/booke X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 May 2011 23:18:42 -0000 Author: marcel Date: Fri May 27 23:18:41 2011 New Revision: 222392 URL: http://svn.freebsd.org/changeset/base/222392 Log: o The P1020(E) & P2020(E) also have two cores. This conditional has a tendency to grow unwieldy so we may want to revisit this in due time. o Simplify the CPU reset function by writing to the reset control register irrespective of whether the CPU has one and automatically falling back to the debug control register if we didn't reset the CPU. The side-effect is that we now properly reset future processors without first having to add the system version to the list. Modified: head/sys/powerpc/booke/platform_bare.c Modified: head/sys/powerpc/booke/platform_bare.c ============================================================================== --- head/sys/powerpc/booke/platform_bare.c Fri May 27 23:09:12 2011 (r222391) +++ head/sys/powerpc/booke/platform_bare.c Fri May 27 23:18:41 2011 (r222392) @@ -104,7 +104,10 @@ bare_probe(platform_t plat) int i, law_max, tgt; ver = SVR_VER(mfspr(SPR_SVR)); - if (ver == SVR_MPC8572E || ver == SVR_MPC8572) + + if (ver == SVR_MPC8572E || ver == SVR_MPC8572 || + ver == SVR_P1020E || ver == SVR_P1020 || + ver == SVR_P2020E || ver == SVR_P2020) maxcpu = 2; else maxcpu = 1; @@ -280,24 +283,23 @@ bare_smp_start_cpu(platform_t plat, stru static void e500_reset(platform_t plat) { - uint32_t ver = SVR_VER(mfspr(SPR_SVR)); - if (ver == SVR_MPC8572E || ver == SVR_MPC8572 || - ver == SVR_MPC8548E || ver == SVR_MPC8548) - /* Systems with dedicated reset register */ - ccsr_write4(OCP85XX_RSTCR, 2); - else { - /* Clear DBCR0, disables debug interrupts and events. */ - mtspr(SPR_DBCR0, 0); - __asm __volatile("isync"); - - /* Enable Debug Interrupts in MSR. */ - mtmsr(mfmsr() | PSL_DE); - - /* Enable debug interrupts and issue reset. */ - mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | - DBCR0_RST_SYSTEM); - } + /* + * Try the dedicated reset register first. + * If the SoC doesn't have one, we'll fall + * back to using the debug control register. + */ + ccsr_write4(OCP85XX_RSTCR, 2); + + /* Clear DBCR0, disables debug interrupts and events. */ + mtspr(SPR_DBCR0, 0); + __asm __volatile("isync"); + + /* Enable Debug Interrupts in MSR. */ + mtmsr(mfmsr() | PSL_DE); + + /* Enable debug interrupts and issue reset. */ + mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); printf("Reset failed...\n"); while (1);