From owner-freebsd-questions@freebsd.org Sun Aug 30 14:35:18 2020 Return-Path: Delivered-To: freebsd-questions@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id C92FF3BCFD2 for ; Sun, 30 Aug 2020 14:35:18 +0000 (UTC) (envelope-from galtsev@kicp.uchicago.edu) Received: from kicp.uchicago.edu (kicp.uchicago.edu [128.135.20.70]) by mx1.freebsd.org (Postfix) with ESMTP id 4BfbTf07HQz42GY for ; Sun, 30 Aug 2020 14:35:17 +0000 (UTC) (envelope-from galtsev@kicp.uchicago.edu) Received: from [192.168.43.231] (unknown [172.58.140.126]) (Authenticated sender: galtsev) by kicp.uchicago.edu (Postfix) with ESMTPSA id 27C724E6B8; Sun, 30 Aug 2020 09:35:17 -0500 (CDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.120.23.2.1\)) Subject: Re: (very OT) Ideal partition schemes (history of partitioning) From: Valeri Galtsev In-Reply-To: Date: Sun, 30 Aug 2020 09:35:15 -0500 Cc: User Questions Content-Transfer-Encoding: quoted-printable Message-Id: References: <20200829154417.8dd5f83d.freebsd@edvax.de> To: Doug Hardie X-Mailer: Apple Mail (2.3608.120.23.2.1) X-Rspamd-Queue-Id: 4BfbTf07HQz42GY X-Spamd-Bar: +++++ Authentication-Results: mx1.freebsd.org; dkim=none; dmarc=fail reason="No valid SPF, No valid DKIM" header.from=uchicago.edu (policy=none); spf=none (mx1.freebsd.org: domain of galtsev@kicp.uchicago.edu has no SPF policy when checking 128.135.20.70) smtp.mailfrom=galtsev@kicp.uchicago.edu X-Spamd-Result: default: False [5.15 / 15.00]; RCVD_VIA_SMTP_AUTH(0.00)[]; ARC_NA(0.00)[]; RECEIVED_SPAMHAUS_XBL(5.00)[172.58.140.126:received]; MID_RHS_MATCH_FROM(0.00)[]; FROM_HAS_DN(0.00)[]; MV_CASE(0.50)[]; GREYLIST(0.00)[pass,meta]; MIME_GOOD(-0.10)[text/plain]; NEURAL_SPAM_SHORT(0.27)[0.273]; NEURAL_HAM_LONG(-0.22)[-0.216]; RECEIVED_SPAMHAUS_PBL(0.00)[172.58.140.126:received]; TO_MATCH_ENVRCPT_SOME(0.00)[]; TO_DN_ALL(0.00)[]; RCPT_COUNT_TWO(0.00)[2]; NEURAL_HAM_MEDIUM(-0.51)[-0.507]; R_SPF_NA(0.00)[no SPF record]; RCVD_NO_TLS_LAST(0.10)[]; FROM_EQ_ENVFROM(0.00)[]; R_DKIM_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:160, ipnet:128.135.0.0/16, country:US]; RCVD_COUNT_TWO(0.00)[2]; MAILMAN_DEST(0.00)[freebsd-questions]; DMARC_POLICY_SOFTFAIL(0.10)[uchicago.edu : No valid SPF, No valid DKIM,none] X-BeenThere: freebsd-questions@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: User questions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 30 Aug 2020 14:35:18 -0000 > On Aug 29, 2020, at 10:00 PM, Valeri Galtsev = wrote: >=20 >=20 >=20 > My time to confess: I=E2=80=99m 63, not much older than you. What I = described was in Russia, which was several (or multiple) years behind = the rest of the World. Most of technology was a =E2=80=9Creplica=E2=80=9D = what West had designed, developed, invented. To justify the word = =E2=80=9Cmost=E2=80=9D (not all) in previous phrase, I just have to give = example of what was created in Russia, not replicated from =E2=80=9Cbehind= the border=E2=80=9D development. That was BESM-6 (abbreviation from = =E2=80=9CFast Electronic Computing Machine=E2=80=9D in Russian) The = uniqueness of design I haven=E2=80=99t seen in other computers was: the = machine level command system was 3-address one. Namely, each machine = level command had 4 fields: >=20 > 1. command > 2. address of first operand > 3. address of second operand > 4. address where to put the result >=20 > Here someone should correct me if there is, or rather was, machine = like that, as my knowledge of what existed back then is definitely = restricted. >=20 > Three address system of machine level commands is wasteful on storage, = say, compared to wide spread 2 field commands (command + address of = operand). However, everything written and compiled with/for that system = of machine level commands is much cleaner, I almost said bug free. Take, = say, operation: add what is in storage address A to what is in storage = address B and put it into storage address C. BESM-6 has one machine = level command to do that. With single address command system this is = done by sequence of three commands: >=20 > 1. put what is in storage address A to addition register > 2. add what is in storage address B to what is in addition register > 3. save addition register to address C >=20 > All three commands must always be together, in that sequence, no = matter what optimization etc. to program is being done. Assembly code is = way less transparent in this case compared to 3 address command system, = and to write assembler and compiler to be clean, =E2=80=9Cbug free=E2=80=9D= , is way simpler task for 3 operand command system. And programming in = assembly language is way simpler. >=20 > I really hope, someone mentions other machines with 3 address command = system, I really would like to know if the existed. Except BESM-6 which = was built of bipolar transistor blocks, and it predecessor BESM-4 build = on vacuum tubes. >=20 > Valeri >=20 > On Aug 30, 2020, at 1:43 AM, Doug Hardie wrote: >=20 >=20 > -- Doug >=20 >> On 29 August 2020, at 20:00, Valeri Galtsev = wrote: >>=20 >>=20 >>=20 >>=20 >> I really hope, someone mentions other machines with 3 address command = system, I really would like to know if the existed. Except BESM-6 which = was built of bipolar transistor blocks, and it predecessor BESM-4 build = on vacuum tubes. >>=20 >=20 > According to Wikipedia: >=20 > Due to the large number of bits needed to encode the three registers = of a 3-operand instruction, RISC architectures that have 16-bit = instructions are invariably 2-operand designs, such as the Atmel AVR, TI = MSP430, and some versions of ARM Thumb. RISC architectures that have = 32-bit instructions are usually 3-operand designs, such as the ARM, = AVR32, MIPS, Power ISA, and SPARC architectures. >=20 > I have no experience with any of those. >=20 Thank you, Doug. You induced my refreshing of memory, and also showed = that I didn=E2=80=99t describe clear enough that BESM-6 instruction set. = I have my post above for convenience. That BESM-6 machine has = instruction set with three operands, and all of three operands can be = addresses in memory. But in general 3 operand instruction set can have = only one or two operands as memory addresses, the rest can be registers. = I looked on wikipedia (I assume, the following is what you referred to): https://en.wikipedia.org/wiki/Instruction_set_architecture and of all 3-oprand instruction sets it was only one: CISC by IBM that = affors all three operands be adresses in memory (alas, reference to it = given on wikipedia doesn=E2=80=99t seem to exist). Of cource, having an advantage of being really clear and transparent = with, very simple assembly code etc, 3-operand with all 3 operands as = memory addresses machine instruction set has obvious disadvanate: it = needs a lot of memory for program. Another aspect that was of interest for me was: that BESM-6 was purely = Russian design (as opposed to multitude =E2=80=9Creplicated=E2=80=9D = designs developed by Western world Russia had). I checked all 3 operand = instruction sets, and all of them are of later development. BESM-6 (the = latest of BESM-1,=E2=80=A6 series, the oldest dated 1952) was of as = early as 1968. And it survived in production for over 20 years. The 3 = operand instruction sets from that wikipedia page are: ARM - 1985 TI MSP430 -200x (later than 2000) ARV32 - 2017 MIPS - 1985 Power ISA - 2006 SPARC - 1986 IBM CISC - 2000 (the only one with 3 addresses as operands) I know from friends who worked in that institution that produced BESM-6 = that that was unique design of their institution development. I am just = trying to satisfy my own curiosity, whether their machine istruction set = with all three operands (two operands and result actually) addressed in = memory, thus producing machine code with single machine command per each = operation no matter what it is, if that was the first machine = instruction set of that sort. I know that the fact that I can not find = earlier analogues doesn=E2=80=99t mean they didn=E2=80=99t exist. So, if = anybody knows examples of machine instruction set with 3 operands all 3 = as memory addresses, used/developed ealier than 1968, I would really = appreciate if you let me know. I=E2=80=99m just curious. Thanks. Valeri > -- Doug >=20