From owner-freebsd-current@FreeBSD.ORG Thu Dec 14 20:56:26 2006 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id E5EA316A548 for ; Thu, 14 Dec 2006 20:56:26 +0000 (UTC) (envelope-from lars@heidieker.de) Received: from wp045.webpack.hosteurope.de (wp045.webpack.hosteurope.de [80.237.132.52]) by mx1.FreeBSD.org (Postfix) with ESMTP id E1DB543DE8 for ; Thu, 14 Dec 2006 20:53:45 +0000 (GMT) (envelope-from lars@heidieker.de) Received: by wp045.webpack.hosteurope.de running Exim 4.43 using esmtpa from dyn-62-56-103-239.dslaccess.co.uk ([62.56.103.239] helo=[192.168.42.9]); authenticated id 1Guxbs-0004yk-6W; Thu, 14 Dec 2006 21:55:20 +0100 In-Reply-To: <20061214193021.GA89046@cons.org> References: <20061214193021.GA89046@cons.org> Mime-Version: 1.0 (Apple Message framework v752.2) Content-Type: text/plain; charset=ISO-8859-1; delsp=yes; format=flowed Message-Id: <606F3A60-8DFB-4564-A27E-F0E4F08AD29F@heidieker.de> Content-Transfer-Encoding: quoted-printable From: Lars Heidieker Date: Thu, 14 Dec 2006 20:55:18 +0000 To: Martin Cracauer X-Pgp-Agent: GPGMail 1.1.2 (Tiger) X-Mailer: Apple Mail (2.752.2) Cc: freebsd-current@freebsd.org Subject: Re: Page table walk on TLB miss X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Dec 2006 20:56:27 -0000 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 14 Dec 2006, at 19:30, Martin Cracauer wrote: > Can somebody explain how the MMU walks the page table in RAM when > there is a TLB miss and where the FreeBSD code is that sets up the > tables? > > Is there actual OS code involved in the walking or does the OS just > set up the code and the MMU walks on it's own? > > Mostly interested in AMD64. > > In case of i386/amd64 the mmu walks the pagetables on it's on =20 (hardware page table walk). The walking is done with physical addresses starting at the physical =20 address stored in the cr3 register of the cpu. Yes other cpus do this completely different UltraSPARC eg has a =20 Software Table walk the cpu traps simply on aTSB miss and the rest is up to the OS. - -- Viele Gr=FC=DFe, Lars Heidieker lars@heidieker.de http://paradoxon.info - ------------------------------------ Mystische Erkl=E4rungen. Die mystischen Erkl=E4rungen gelten f=FCr tief; die Wahrheit ist, dass sie noch nicht einmal oberfl=E4chlich sind. -- Friedrich Nietzsche -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (Darwin) iD8DBQFFgbo2cxuYqjT7GRYRAg0TAKCSr/jIUkS/Q2+bfst8LDbGEuZy7wCfVvkT OEJyC8xTCdfoOr1sfeYVEMk=3D =3D5TQh -----END PGP SIGNATURE-----