From owner-svn-src-head@FreeBSD.ORG Fri Jan 9 10:45:05 2009 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 998BB106567C; Fri, 9 Jan 2009 10:45:04 +0000 (UTC) (envelope-from raj@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id D1A1F8FC19; Fri, 9 Jan 2009 10:45:04 +0000 (UTC) (envelope-from raj@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n09Aj4lE054121; Fri, 9 Jan 2009 10:45:04 GMT (envelope-from raj@svn.freebsd.org) Received: (from raj@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n09Aj4Nt054117; Fri, 9 Jan 2009 10:45:04 GMT (envelope-from raj@svn.freebsd.org) Message-Id: <200901091045.n09Aj4Nt054117@svn.freebsd.org> From: Rafal Jaworowski Date: Fri, 9 Jan 2009 10:45:04 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r186933 - in head/sys/arm: arm include X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Jan 2009 10:45:06 -0000 Author: raj Date: Fri Jan 9 10:45:04 2009 New Revision: 186933 URL: http://svn.freebsd.org/changeset/base/186933 Log: Fix confusing naming of Marvell ARM CPU specific routines. - The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon. - Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does not require dedicated routines. This will be accompanied by a file rename commit. Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/arm/cpufunc_asm_feroceon.S head/sys/arm/arm/elf_trampoline.c head/sys/arm/include/cpufunc.h Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Fri Jan 9 10:20:51 2009 (r186932) +++ head/sys/arm/arm/cpufunc.c Fri Jan 9 10:45:04 2009 (r186933) @@ -358,7 +358,7 @@ struct cpu_functions armv5_ec_cpufuncs = }; -struct cpu_functions feroceon_cpufuncs = { +struct cpu_functions sheeva_cpufuncs = { /* CPU functions */ cpufunc_id, /* id */ @@ -368,7 +368,7 @@ struct cpu_functions feroceon_cpufuncs = cpufunc_control, /* control */ cpufunc_domains, /* Domain */ - feroceon_setttb, /* Setttb */ + sheeva_setttb, /* Setttb */ cpufunc_faultstatus, /* Faultstatus */ cpufunc_faultaddress, /* Faultaddress */ @@ -387,17 +387,17 @@ struct cpu_functions feroceon_cpufuncs = armv5_ec_icache_sync_range, /* icache_sync_range */ armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */ - feroceon_dcache_wbinv_range, /* dcache_wbinv_range */ - feroceon_dcache_inv_range, /* dcache_inv_range */ - feroceon_dcache_wb_range, /* dcache_wb_range */ + sheeva_dcache_wbinv_range, /* dcache_wbinv_range */ + sheeva_dcache_inv_range, /* dcache_inv_range */ + sheeva_dcache_wb_range, /* dcache_wb_range */ armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */ - feroceon_idcache_wbinv_range, /* idcache_wbinv_all */ + sheeva_idcache_wbinv_range, /* idcache_wbinv_all */ - feroceon_l2cache_wbinv_all, /* l2cache_wbinv_all */ - feroceon_l2cache_wbinv_range, /* l2cache_wbinv_range */ - feroceon_l2cache_inv_range, /* l2cache_inv_range */ - feroceon_l2cache_wb_range, /* l2cache_wb_range */ + sheeva_l2cache_wbinv_all, /* l2cache_wbinv_all */ + sheeva_l2cache_wbinv_range, /* l2cache_wbinv_range */ + sheeva_l2cache_inv_range, /* l2cache_inv_range */ + sheeva_l2cache_wb_range, /* l2cache_wb_range */ /* Other functions */ @@ -1000,7 +1000,7 @@ set_cpufuncs() cputype == CPU_ID_MV88FR571_VD || cputype == CPU_ID_MV88FR571_41) { - cpufuncs = feroceon_cpufuncs; + cpufuncs = sheeva_cpufuncs; /* * Workaround for Marvell MV78100 CPU: Cache prefetch * mechanism may affect the cache coherency validity, @@ -1011,12 +1011,12 @@ set_cpufuncs() */ if (cputype == CPU_ID_MV88FR571_VD || cputype == CPU_ID_MV88FR571_41) { - feroceon_control_ext(0xffffffff, + sheeva_control_ext(0xffffffff, FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN | FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN | FC_L2_PREF_DIS); } else { - feroceon_control_ext(0xffffffff, + sheeva_control_ext(0xffffffff, FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN | FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN); } Modified: head/sys/arm/arm/cpufunc_asm_feroceon.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_feroceon.S Fri Jan 9 10:20:51 2009 (r186932) +++ head/sys/arm/arm/cpufunc_asm_feroceon.S Fri Jan 9 10:45:04 2009 (r186933) @@ -34,12 +34,12 @@ __FBSDID("$FreeBSD$"); #include -.Lferoceon_cache_line_size: +.Lsheeva_cache_line_size: .word _C_LABEL(arm_pdcache_line_size) -.Lferoceon_asm_page_mask: +.Lsheeva_asm_page_mask: .word _C_LABEL(PAGE_MASK) -ENTRY(feroceon_setttb) +ENTRY(sheeva_setttb) /* Disable irqs */ mrs r2, cpsr orr r3, r2, #I32_bit | F32_bit @@ -63,11 +63,11 @@ ENTRY(feroceon_setttb) mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ RET -ENTRY(feroceon_dcache_wbinv_range) +ENTRY(sheeva_dcache_wbinv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ - ldr ip, .Lferoceon_cache_line_size + ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip @@ -76,7 +76,7 @@ ENTRY(feroceon_dcache_wbinv_range) bics r1, r1, ip bics r0, r0, ip - ldr ip, .Lferoceon_asm_page_mask + ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 @@ -105,11 +105,11 @@ ENTRY(feroceon_dcache_wbinv_range) ldr lr, [sp], #4 RET -ENTRY(feroceon_idcache_wbinv_range) +ENTRY(sheeva_idcache_wbinv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ - ldr ip, .Lferoceon_cache_line_size + ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip @@ -118,7 +118,7 @@ ENTRY(feroceon_idcache_wbinv_range) bics r1, r1, ip bics r0, r0, ip - ldr ip, .Lferoceon_asm_page_mask + ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 @@ -136,7 +136,7 @@ ENTRY(feroceon_idcache_wbinv_range) msr cpsr_c, lr /* Invalidate and clean icache line by line */ - ldr r3, .Lferoceon_cache_line_size + ldr r3, .Lsheeva_cache_line_size ldr r3, [r3] 2: mcr p15, 0, r0, c7, c5, 1 @@ -156,11 +156,11 @@ ENTRY(feroceon_idcache_wbinv_range) ldr lr, [sp], #4 RET -ENTRY(feroceon_dcache_inv_range) +ENTRY(sheeva_dcache_inv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ - ldr ip, .Lferoceon_cache_line_size + ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip @@ -169,7 +169,7 @@ ENTRY(feroceon_dcache_inv_range) bics r1, r1, ip bics r0, r0, ip - ldr ip, .Lferoceon_asm_page_mask + ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 @@ -198,11 +198,11 @@ ENTRY(feroceon_dcache_inv_range) ldr lr, [sp], #4 RET -ENTRY(feroceon_dcache_wb_range) +ENTRY(sheeva_dcache_wb_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ - ldr ip, .Lferoceon_cache_line_size + ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip @@ -211,7 +211,7 @@ ENTRY(feroceon_dcache_wb_range) bics r1, r1, ip bics r0, r0, ip - ldr ip, .Lferoceon_asm_page_mask + ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 @@ -240,11 +240,11 @@ ENTRY(feroceon_dcache_wb_range) ldr lr, [sp], #4 RET -ENTRY(feroceon_l2cache_wbinv_range) +ENTRY(sheeva_l2cache_wbinv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ - ldr ip, .Lferoceon_cache_line_size + ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip @@ -253,7 +253,7 @@ ENTRY(feroceon_l2cache_wbinv_range) bics r1, r1, ip bics r0, r0, ip - ldr ip, .Lferoceon_asm_page_mask + ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 @@ -284,11 +284,11 @@ ENTRY(feroceon_l2cache_wbinv_range) ldr lr, [sp], #4 RET -ENTRY(feroceon_l2cache_inv_range) +ENTRY(sheeva_l2cache_inv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ - ldr ip, .Lferoceon_cache_line_size + ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip @@ -297,7 +297,7 @@ ENTRY(feroceon_l2cache_inv_range) bics r1, r1, ip bics r0, r0, ip - ldr ip, .Lferoceon_asm_page_mask + ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 @@ -326,11 +326,11 @@ ENTRY(feroceon_l2cache_inv_range) ldr lr, [sp], #4 RET -ENTRY(feroceon_l2cache_wb_range) +ENTRY(sheeva_l2cache_wb_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ - ldr ip, .Lferoceon_cache_line_size + ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip @@ -339,7 +339,7 @@ ENTRY(feroceon_l2cache_wb_range) bics r1, r1, ip bics r0, r0, ip - ldr ip, .Lferoceon_asm_page_mask + ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 @@ -368,14 +368,14 @@ ENTRY(feroceon_l2cache_wb_range) ldr lr, [sp], #4 RET -ENTRY(feroceon_l2cache_wbinv_all) +ENTRY(sheeva_l2cache_wbinv_all) mov r0, #0 mcr p15, 1, r0, c15, c9, 0 /* Clean L2 */ mcr p15, 1, r0, c15, c11, 0 /* Invalidate L2 */ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET -ENTRY(feroceon_control_ext) +ENTRY(sheeva_control_ext) mrc p15, 1, r3, c15, c1, 0 /* Read the control register */ bic r2, r3, r0 /* Clear bits */ eor r2, r2, r1 /* XOR bits */ Modified: head/sys/arm/arm/elf_trampoline.c ============================================================================== --- head/sys/arm/arm/elf_trampoline.c Fri Jan 9 10:20:51 2009 (r186932) +++ head/sys/arm/arm/elf_trampoline.c Fri Jan 9 10:45:04 2009 (r186933) @@ -74,7 +74,7 @@ void __startC(void); #ifdef CPU_XSCALE_81342 #define cpu_l2cache_wbinv_all xscalec3_l2cache_purge #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) -#define cpu_l2cache_wbinv_all feroceon_l2cache_wbinv_all +#define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all #else #define cpu_l2cache_wbinv_all() #endif Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Fri Jan 9 10:20:51 2009 (r186932) +++ head/sys/arm/include/cpufunc.h Fri Jan 9 10:45:04 2009 (r186933) @@ -377,17 +377,17 @@ extern unsigned arm10_dcache_sets_inc; extern unsigned arm10_dcache_index_max; extern unsigned arm10_dcache_index_inc; -u_int feroceon_control_ext (u_int, u_int); -void feroceon_setttb (u_int); -void feroceon_dcache_wbinv_range (vm_offset_t, vm_size_t); -void feroceon_dcache_inv_range (vm_offset_t, vm_size_t); -void feroceon_dcache_wb_range (vm_offset_t, vm_size_t); -void feroceon_idcache_wbinv_range (vm_offset_t, vm_size_t); - -void feroceon_l2cache_wbinv_range (vm_offset_t, vm_size_t); -void feroceon_l2cache_inv_range (vm_offset_t, vm_size_t); -void feroceon_l2cache_wb_range (vm_offset_t, vm_size_t); -void feroceon_l2cache_wbinv_all (void); +u_int sheeva_control_ext (u_int, u_int); +void sheeva_setttb (u_int); +void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); +void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); +void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); +void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); + +void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); +void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); +void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); +void sheeva_l2cache_wbinv_all (void); #endif #ifdef CPU_ARM11