Date: Thu, 5 Mar 2009 10:47:22 +0100 From: "Tassilo Philipp" <tphilipp@potion-studios.com> To: FreeBSD-gnats-submit@FreeBSD.org Subject: ports/132326: New port: devel/psptoolchain-gdb Message-ID: <20090305100342.8D2018FC18@mx1.freebsd.org> Resent-Message-ID: <200903051010.n25AA4bv077579@freefall.freebsd.org>
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>Number: 132326
>Category: ports
>Synopsis: New port: devel/psptoolchain-gdb
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: freebsd-ports-bugs
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: change-request
>Submitter-Id: current-users
>Arrival-Date: Thu Mar 05 10:10:04 UTC 2009
>Closed-Date:
>Last-Modified:
>Originator: Tassilo Philipp
>Release: FreeBSD 7.0-RELEASE amd64
>Organization:
>Environment:
System: FreeBSD amphore.potion-studios.com 7.0-RELEASE FreeBSD 7.0-RELEASE #0: Wed Aug 20 20:52:41 CEST 2008 tphilipp@amphore.potion-studios.com:/usr/obj/usr/src/sys/GENERIC amd64
>Description:
>How-To-Repeat:
>Fix:
--- psptoolchain-gdb.shar begins here ---
# This is a shell archive. Save it in a file, remove anything before
# this line, and then unpack it by entering "sh file". Note, it may
# create directories; files and directories will be owned by you and
# have default permissions.
#
# This archive contains:
#
# psptoolchain-gdb
# psptoolchain-gdb/Makefile
# psptoolchain-gdb/pkg-descr
# psptoolchain-gdb/files
# psptoolchain-gdb/files/patch-bfd-cpu-mips.c
# psptoolchain-gdb/files/patch-config.sub
# psptoolchain-gdb/files/patch-include-bin-bugs.h
# psptoolchain-gdb/files/patch-include-opcode-mips.h
# psptoolchain-gdb/files/patch-opcodes-mips-opc.c
# psptoolchain-gdb/files/patch-bfd-archures.c
# psptoolchain-gdb/files/patch-bfd-bfd-in2.h
# psptoolchain-gdb/files/patch-bfd-elfxx-mips.c
# psptoolchain-gdb/files/patch-gdb-remote.c
# psptoolchain-gdb/files/patch-include-elf-common.h
# psptoolchain-gdb/files/patch-include-elf-mips.h
# psptoolchain-gdb/files/patch-opcodes-mips-dis.c
# psptoolchain-gdb/distinfo
#
echo c - psptoolchain-gdb
mkdir -p psptoolchain-gdb > /dev/null 2>&1
echo x - psptoolchain-gdb/Makefile
sed 's/^X//' >psptoolchain-gdb/Makefile << 'END-of-psptoolchain-gdb/Makefile'
X# New ports collection makefile for: psptoolchain-gdb
X# Date created: 15 February 2009
X# Whom: Tassilo Philipp <tphilipp@potion-studios.com>
X#
X# $FreeBSD$
X#
X
XPORTNAME= gdb
XPORTVERSION= 6.4
XCATEGORIES= devel
XMASTER_SITES= ${MASTER_SITE_GNU}
XMASTER_SITE_SUBDIR= ${PORTNAME}/
XPKGNAMEPREFIX= psptoolchain-
X
XMAINTAINER= tphilipp@potion-studios.com
XCOMMENT= PlayStation Portable development toolchain ${PORTNAME}
X
XBUILD_DEPENDS= ${LOCALBASE}/psp/sdk/lib/libpspsdk.a:${PORTSDIR}/devel/psptoolchain-pspsdk
X
XUSE_BZIP2= yes
XUSE_GMAKE= yes
X
XHAS_CONFIGURE= yes
XCONFIGURE_ARGS?= --prefix=${PREFIX} --target="psp" --disable-nls
X
XMAN1= psp-gdb.1 \
X psp-gdbtui.1 \
X psp-run.1
XINFO= annotate \
X gdb \
X gdbint \
X stabs
X
XPLIST_FILES= lib/libpsp-sim.a \
X bin/psp-run \
X bin/psp-gdbtui \
X bin/psp-gdb
X
X.include <bsd.port.mk>
END-of-psptoolchain-gdb/Makefile
echo x - psptoolchain-gdb/pkg-descr
sed 's/^X//' >psptoolchain-gdb/pkg-descr << 'END-of-psptoolchain-gdb/pkg-descr'
XThe PlayStation Portable Toolchain is a collection of tools and utilities
Xfor homebrew PSP development.
X
XWWW: http://www.ps2dev.org
END-of-psptoolchain-gdb/pkg-descr
echo c - psptoolchain-gdb/files
mkdir -p psptoolchain-gdb/files > /dev/null 2>&1
echo x - psptoolchain-gdb/files/patch-bfd-cpu-mips.c
sed 's/^X//' >psptoolchain-gdb/files/patch-bfd-cpu-mips.c << 'END-of-psptoolchain-gdb/files/patch-bfd-cpu-mips.c'
X--- bfd/cpu-mips.c.orig 2005-05-04 16:53:06.000000000 +0100
X+++ bfd/cpu-mips.c 2007-02-08 20:06:04.000000000 +0000
X@@ -86,6 +86,7 @@
X I_mipsisa64,
X I_mipsisa64r2,
X I_sb1,
X+ I_allegrex,
X };
X
X #define NN(index) (&arch_info_struct[(index) + 1])
X@@ -118,7 +119,8 @@
X N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
X N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
X N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
X- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
X+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
X+ N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, 0),
X };
X
X /* The default architecture is mips:3000, but with a machine number of
END-of-psptoolchain-gdb/files/patch-bfd-cpu-mips.c
echo x - psptoolchain-gdb/files/patch-config.sub
sed 's/^X//' >psptoolchain-gdb/files/patch-config.sub << 'END-of-psptoolchain-gdb/files/patch-config.sub'
X--- config.sub.orig 2005-07-14 02:24:56.000000000 +0100
X+++ config.sub 2007-02-08 20:06:04.000000000 +0000
X@@ -256,6 +256,7 @@
X | mipsisa64sb1 | mipsisa64sb1el \
X | mipsisa64sr71k | mipsisa64sr71kel \
X | mipstx39 | mipstx39el \
X+ | mipsallegrex | mipsallegrexel \
X | mn10200 | mn10300 \
X | ms1 \
X | msp430 \
X@@ -335,6 +336,7 @@
X | mipsisa64sb1-* | mipsisa64sb1el-* \
X | mipsisa64sr71k-* | mipsisa64sr71kel-* \
X | mipstx39-* | mipstx39el-* \
X+ | mipsallegrex-* | mipsallegrexel-* \
X | mmix-* \
X | ms1-* \
X | msp430-* \
X@@ -678,6 +680,10 @@
X basic_machine=m68k-atari
X os=-mint
X ;;
X+ psp)
X+ basic_machine=mipsallegrexel-psp
X+ os=-elf
X+ ;;
X mips3*-*)
X basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
X ;;
END-of-psptoolchain-gdb/files/patch-config.sub
echo x - psptoolchain-gdb/files/patch-include-bin-bugs.h
sed 's/^X//' >psptoolchain-gdb/files/patch-include-bin-bugs.h << 'END-of-psptoolchain-gdb/files/patch-include-bin-bugs.h'
X--- include/bin-bugs.h.orig 2004-07-23 16:40:19.000000000 +0100
X+++ include/bin-bugs.h 2007-02-08 20:06:04.000000000 +0000
X@@ -1,3 +1,3 @@
X #ifndef REPORT_BUGS_TO
X-#define REPORT_BUGS_TO "<URL:http://www.sourceware.org/bugzilla/>"
X+#define REPORT_BUGS_TO "<URL:http://wiki.pspdev.org/psp:toolchain#bugs>"
X #endif
END-of-psptoolchain-gdb/files/patch-include-bin-bugs.h
echo x - psptoolchain-gdb/files/patch-include-opcode-mips.h
sed 's/^X//' >psptoolchain-gdb/files/patch-include-opcode-mips.h << 'END-of-psptoolchain-gdb/files/patch-include-opcode-mips.h'
X--- include/opcode/mips.h.orig 2005-09-06 19:42:58.000000000 +0100
X+++ include/opcode/mips.h 2007-02-08 20:06:04.000000000 +0000
X@@ -203,6 +203,83 @@
X #define MDMX_FMTSEL_VEC_QH 0x15
X #define MDMX_FMTSEL_VEC_OB 0x16
X
X+#define OP_SH_VFPU_DELTA 0
X+#define OP_MASK_VFPU_DELTA 0xfffc
X+#define OP_SH_VFPU_IMM3 16
X+#define OP_MASK_VFPU_IMM3 0x7
X+#define OP_SH_VFPU_IMM5 16
X+#define OP_MASK_VFPU_IMM5 0x1f
X+#define OP_SH_VFPU_IMM8 16
X+#define OP_MASK_VFPU_IMM8 0xff
X+#define OP_SH_VFPU_CC 18 /* Condition code. */
X+#define OP_MASK_VFPU_CC 0x7
X+#define OP_SH_VFPU_CONST 16
X+#define OP_MASK_VFPU_CONST 0x1f
X+#define OP_SH_VFPU_COND 0 /* Conditional compare. */
X+#define OP_MASK_VFPU_COND 0xf
X+#define OP_SH_VFPU_VMTVC 0
X+#define OP_MASK_VFPU_VMTVC 0xff
X+#define OP_SH_VFPU_VMFVC 8
X+#define OP_MASK_VFPU_VMFVC 0xff
X+#define OP_SH_VFPU_RWB 1
X+#define OP_MASK_VFPU_RWB 0x1
X+#define OP_SH_VFPU_ROT 16 /* Rotators used in vrot. */
X+#define OP_MASK_VFPU_ROT 0x1f
X+#define OP_SH_VFPU_FLOAT16 0
X+#define OP_MASK_VFPU_FLOAT16 0xffff
X+
X+/* VFPU registers. */
X+#define OP_SH_VFPU_VD 0
X+#define OP_MASK_VFPU_VD 0x7f
X+#define OP_SH_VFPU_VS 8
X+#define OP_MASK_VFPU_VS 0x7f
X+#define OP_SH_VFPU_VT 16
X+#define OP_MASK_VFPU_VT 0x7f
X+#define OP_SH_VFPU_VT_LO 16 /* Bits 0-4 of vt. */
X+#define OP_MASK_VFPU_VT_LO 0x1f
X+#define OP_SH_VFPU_VT_HI 5 /* Right-shifted. */
X+#define OP_MASK_VFPU_VT_HI1 0x1 /* Bit 5 of vt. */
X+#define OP_MASK_VFPU_VT_HI2 0x3 /* Bits 5-6 of vt. */
X+/* Special handling of vs in vmmul instructions. */
X+#define VFPU_OP_VT_VS_VD 0xff800000
X+#define VFPU_OPCODE_VMMUL 0xf0000000
X+
X+/* VFPU prefix instruction operands. The *_SH_* values really specify where
X+ the bitfield begins, as VFPU prefix instructions have four operands
X+ encoded within the immediate field. */
X+#define VFPU_SH_PFX_NEG 16
X+#define VFPU_MASK_PFX_NEG 0x1 /* Negation. */
X+#define VFPU_SH_PFX_CST 12
X+#define VFPU_MASK_PFX_CST 0x1 /* Constant. */
X+#define VFPU_SH_PFX_ABS_CSTHI 8
X+#define VFPU_MASK_PFX_ABS_CSTHI 0x1 /* Abs/Constant (bit 2). */
X+#define VFPU_MASK_PFX_SWZ_CSTLO 0x3 /* Swizzle/Constant (bits 0-1). */
X+#define VFPU_SH_PFX_MASK 8
X+#define VFPU_MASK_PFX_MASK 0x1 /* Mask. */
X+#define VFPU_MASK_PFX_SAT 0x3 /* Saturation. */
X+
X+/* Special handling of the vrot instructions. */
X+#define VFPU_MASK_OP_SIZE 0x8080 /* Masks the operand size (pair, triple, quad). */
X+#define VFPU_OP_SIZE_PAIR 0x80
X+#define VFPU_OP_SIZE_TRIPLE 0x8000
X+#define VFPU_OP_SIZE_QUAD 0x8080
X+/* Note that these are within the rotators field, and not the full opcode. */
X+#define VFPU_SH_ROT_HI 2
X+#define VFPU_MASK_ROT_HI 0x3
X+#define VFPU_SH_ROT_LO 0
X+#define VFPU_MASK_ROT_LO 0x3
X+#define VFPU_SH_ROT_NEG 4 /* Negation. */
X+#define VFPU_MASK_ROT_NEG 0x1
X+
X+/* VFPU 16-bit floating-point format. */
X+#define VFPU_FLOAT16_EXP_MAX 0x1f
X+#define VFPU_SH_FLOAT16_SIGN 15
X+#define VFPU_MASK_FLOAT16_SIGN 0x1
X+#define VFPU_SH_FLOAT16_EXP 10
X+#define VFPU_MASK_FLOAT16_EXP 0x1f
X+#define VFPU_SH_FLOAT16_FRAC 0
X+#define VFPU_MASK_FLOAT16_FRAC 0x3ff
X+
X /* This structure holds information for a particular instruction. */
X
X struct mips_opcode
X@@ -290,6 +367,29 @@
X Requires that "+A" or "+E" occur first to set position.
X Enforces: 32 < (pos+size) <= 64.
X
X+ Sony Allegrex VFPU instructions:
X+ "?o"
X+ "?0" - "?3"
X+ "?4" - "?7"
X+ "?a"
X+ "?b"
X+ "?c"
X+ "?e"
X+ "?f"
X+ "?i"
X+ "?q"
X+ "?r"
X+ "?u"
X+ "?w"
X+ "?d"
X+ "?m"
X+ "?n"
X+ "?s"
X+ "?t"
X+ "?v"
X+ "?x"
X+ "?z"
X+
X Floating point instructions:
X "D" 5 bit destination register (OP_*_FD)
X "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
X@@ -500,6 +600,8 @@
X #define INSN_5400 0x01000000
X /* NEC VR5500 instruction. */
X #define INSN_5500 0x02000000
X+/* Sony Allegrex instruction. */
X+#define INSN_ALLEGREX 0x10000000
X /* MT ASE */
X #define INSN_MT 0x04000000
X
X@@ -549,6 +651,7 @@
X #define CPU_MIPS64 64
X #define CPU_MIPS64R2 65
X #define CPU_SB1 12310201 /* octal 'SB', 01. */
X+#define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */
X
X /* Test for membership in an ISA including chip specific ISAs. INSN
X is pointer to an element of the opcode table; ISA is the specified
X@@ -570,6 +673,7 @@
X || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
X || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
X || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
X+ || (cpu == CPU_ALLEGREX && ((insn)->membership & INSN_ALLEGREX) != 0) \
X || 0) /* Please keep this term for easier source merging. */
X
X /* This is a list of macro expanded instructions.
X@@ -685,6 +789,16 @@
X M_LL_AB,
X M_LLD_AB,
X M_LS_A,
X+ M_LVHIP,
X+ M_LVHIS,
X+ M_LVIP,
X+ M_LVIQ,
X+ M_LVIS,
X+ M_LVIT,
X+ M_LVLQ_AB,
X+ M_LVRQ_AB,
X+ M_LVQ_AB,
X+ M_LVQ_AB_2,
X M_LW_A,
X M_LW_AB,
X M_LWC0_A,
X@@ -774,6 +888,10 @@
X M_SUB_I,
X M_SUBU_I,
X M_SUBU_I_2,
X+ M_SVLQ_AB,
X+ M_SVQ_AB,
X+ M_SVRQ_AB,
X+ M_SVS_AB,
X M_TEQ_I,
X M_TGE_I,
X M_TGEU_I,
X@@ -788,14 +906,24 @@
X M_ULH_A,
X M_ULHU,
X M_ULHU_A,
X+ M_ULVQ,
X+ M_ULVQ_AB,
X+ M_ULVS,
X M_ULW,
X M_ULW_A,
X M_USH,
X M_USH_A,
X+ M_USVQ,
X+ M_USVQ_AB,
X+ M_USVS,
X M_USW,
X M_USW_A,
X M_USD,
X M_USD_A,
X+ M_VCMOVP,
X+ M_VCMOVQ,
X+ M_VCMOVS,
X+ M_VCMOVT,
X M_XOR_I,
X M_COP0,
X M_COP1,
END-of-psptoolchain-gdb/files/patch-include-opcode-mips.h
echo x - psptoolchain-gdb/files/patch-opcodes-mips-opc.c
sed 's/^X//' >psptoolchain-gdb/files/patch-opcodes-mips-opc.c << 'END-of-psptoolchain-gdb/files/patch-opcodes-mips-opc.c'
X--- opcodes/mips-opc.c.orig 2005-09-06 19:46:57.000000000 +0100
X+++ opcodes/mips-opc.c 2007-02-08 20:06:04.000000000 +0000
X@@ -109,6 +109,7 @@
X #define N5 (INSN_5400 | INSN_5500)
X #define N54 INSN_5400
X #define N55 INSN_5500
X+#define AL INSN_ALLEGREX
X
X #define G1 (T3 \
X )
X@@ -298,6 +299,7 @@
X {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
X {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
X {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
X+{"break", "B", 0x0000000d, 0xfc00003f, TRAP, 0, I32|AL },
X {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
X {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
X {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
X@@ -459,7 +461,7 @@
X {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
X {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
X {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
X-{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3},
X+{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3|AL},
X {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
X {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
X {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
X@@ -473,7 +475,9 @@
X {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
X {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
X {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
X+{"clo", "d,s", 0x00000017, 0xfc1f07ff, WR_d|RD_s, 0, AL },
X {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
X+{"clz", "d,s", 0x00000016, 0xfc1f07ff, WR_d|RD_s, 0, AL },
X {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
X {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
X {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
X@@ -498,13 +502,15 @@
X {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 },
X {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
X {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
X+{"max", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
X {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
X {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
X {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
X {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
X+{"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
X {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
X {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
X-{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
X+{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL },
X {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
X {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
X /* dctr and dctw are used on the r5000. */
X@@ -593,7 +599,7 @@
X {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
X {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
X {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
X-{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 },
X+{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5|AL },
X {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
X {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
X {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
X@@ -634,10 +640,10 @@
X {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
X {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
X {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
X-{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },
X+{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32|AL },
X {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
X {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
X-{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
X+{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33|AL },
X {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
X {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
X {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
X@@ -646,7 +652,7 @@
X {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
X {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
X {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
X-{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
X+{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33|AL },
X {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
X {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I33 },
X {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */
X@@ -680,18 +686,10 @@
X {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
X {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
X {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
X-{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
X-{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
X-{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
X-{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
X-{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
X-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
X-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
X-{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
X-{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
X-{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
X-{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
X-{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
X+/* ldc1 is at the bottom of the table. */
X+/* ldc2 is at the bottom of the table. */
X+/* ldc3 is at the bottom of the table. */
X+{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3|AL },
X {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
X {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
X {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
X@@ -721,8 +719,7 @@
X {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
X {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
X {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
X-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
X-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
X+/* lwc2 is at the bottom of the table. */
X {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
X {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
X {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
X@@ -755,10 +752,12 @@
X {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 },
X {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 },
X {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
X+{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
X {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55},
X {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
X {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
X {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
X+{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
X {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55},
X {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
X {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
X@@ -799,7 +798,7 @@
X /* mfhc2 is at the bottom of the table. */
X {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
X {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
X-{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
X+{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5|AL },
X {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
X {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
X {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
X@@ -818,7 +817,7 @@
X {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
X {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
X {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 },
X-{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
X+{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32|AL },
X {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
X {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
X {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
X@@ -831,7 +830,7 @@
X {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
X {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
X {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 },
X-{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
X+{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32|AL },
X {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
X {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
X {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
X@@ -848,8 +847,10 @@
X {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 },
X {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 },
X {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
X+{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
X {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
X {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
X+{"msubu", "s,t", 0x0000002f, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
X {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
X {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
X {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
X@@ -864,7 +865,7 @@
X /* mthc2 is at the bottom of the table. */
X {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
X {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
X-{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
X+{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5|AL },
X {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
X {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
X {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
X@@ -1018,13 +1019,13 @@
X {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
X {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
X {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
X-{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33 },
X-{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33 },
X-{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33 },
X-{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33 },
X-{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33 },
X-{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33 },
X-{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33 },
X+{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|AL },
X+{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|AL },
X+{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|AL },
X+{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|AL },
X+{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|AL },
X+{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|AL },
X+{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|AL },
X {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
X {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
X {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
X@@ -1056,24 +1057,17 @@
X {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
X {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 },
X {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 },
X-{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
X-{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
X-{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
X-{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
X-{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
X-{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
X-{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
X-{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
X-{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
X-{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
X-{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
X-{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
X+/* sdc1 is at the bottom of the table. */
X+/* sdc2 is at the bottom of the table. */
X+/* sdc3 is at the bottom of the table. */
X+/* s.d (sdc1 is at the bottom of the table. */
X+{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3|AL },
X {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
X {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
X {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
X {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I4 },
X-{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 },
X-{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
X+{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33|AL },
X+{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33|AL },
X {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
X {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
X {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
X@@ -1165,8 +1159,7 @@
X {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
X {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
X {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
X-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
X-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
X+/* swc2 is at the bottom of the table. */
X {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
X {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
X {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
X@@ -1251,7 +1244,8 @@
X {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
X {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
X {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
X-{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
X+{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33|AL },
X+{"wsbw", "d,t", 0x7c0000e0, 0xffe007ff, WR_d|RD_t, 0, AL },
X {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
X {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
X {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
X@@ -1263,6 +1257,319 @@
X {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
X {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
X
X+/* Sony Allegrex CPU core. */
X+{"bitrev", "d,t", 0x7c000520, 0xffe007ff, WR_d|RD_t, 0, AL },
X+{"mfic", "t,G", 0x70000024, 0xffe007ff, LCD|WR_t|RD_C0, 0, AL },
X+{"mtic", "t,G", 0x70000026, 0xffe007ff, COD|RD_t|WR_C0, 0, AL },
X+
X+/* Sony Allegrex VFPU instructions. */
X+{"bvf", "?c,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, AL },
X+{"bvfl", "?c,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, AL },
X+{"bvt", "?c,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, AL },
X+{"bvtl", "?c,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, AL },
X+{"lv.s", "?m0x,?o(b)", 0xc8000000, 0xfc000000, CLD|RD_s|WR_CC, 0, AL },
X+{"lv.s", "?m0x,A(b)", 0, (int) M_LVQ_AB, INSN_MACRO, 0, AL },
X+{"ulv.s", "?m0x,o(b)", 0, (int) M_ULVS, INSN_MACRO, 0, AL },
X+{"lv.q", "?n3x,?o(b)", 0xd8000000, 0xfc000002, CLD|RD_s|WR_CC, 0, AL },
X+{"lv.q", "?n3x,A(b)", 0, (int) M_LVQ_AB_2, INSN_MACRO, 0, AL },
X+{"ulv.q", "?n3x,?o(b)", 0, (int) M_ULVQ, INSN_MACRO, 0, AL },
X+{"ulv.q", "?n3x,A(b)", 0, (int) M_ULVQ_AB, INSN_MACRO, 0, AL },
X+{"lvi.s", "?t0x,l?y0", 0, (int) M_LVIS, INSN_MACRO, 0, AL },
X+{"lvi.p", "?t1x,?[l?y0,l?y1?]", 0, (int) M_LVIP, INSN_MACRO, 0, AL },
X+{"lvi.t", "?t2x,?[l?y0,l?y1,l?y2?]", 0, (int) M_LVIT, INSN_MACRO, 0, AL },
X+{"lvi.q", "?t3x,?[l?y0,l?y1,l?y2,l?y3?]", 0, (int) M_LVIQ, INSN_MACRO, 0, AL },
X+{"lvhi.s", "?t0x,?[?u?y0,?u?y1?]", 0, (int) M_LVHIS, INSN_MACRO, 0, AL },
X+{"lvhi.p", "?t1x,?[?u?y0,?u?y1,?u?y2,?u?y3?]", 0, (int) M_LVHIP, INSN_MACRO, 0, AL },
X+{"sv.s", "?m0x,?o(b)", 0xe8000000, 0xfc000000, SM|RD_s|RD_C2, 0, AL },
X+{"sv.s", "?m0x,A(b)", 0, (int) M_SVS_AB, INSN_MACRO, 0, AL },
X+{"usv.s", "?m0x,o(b)", 0, (int) M_USVS, INSN_MACRO, 0, AL },
X+{"sv.q", "?n3x,?o(b)", 0xf8000000, 0xfc000002, SM|RD_s|RD_C2, 0, AL },
X+{"sv.q", "?n3x,?o(b),?z", 0xf8000000, 0xfc000000, SM|RD_s|RD_C2, 0, AL },
X+{"sv.q", "?n3x,A(b)", 0, (int) M_SVQ_AB, INSN_MACRO, 0, AL },
X+{"sv.q", "?n3x,A(b),?z", 0, (int) M_SVQ_AB, INSN_MACRO, 0, AL },
X+{"sv.q", "?n3x,A,?z", 0, (int) M_SVQ_AB, INSN_MACRO, 0, AL },
X+{"usv.q", "?n3x,?o(b)", 0, (int) M_USVQ, INSN_MACRO, 0, AL },
X+{"usv.q", "?n3x,A(b)", 0, (int) M_USVQ_AB, INSN_MACRO, 0, AL },
X+{"vwb.q", "?n3x,?o(b)", 0xf8000002, 0xfc000002, SM|RD_s|RD_C2, 0, AL },
X+{"lvl.q", "?n3x,?o(b)", 0xd4000000, 0xfc000002, CLD|RD_s|WR_CC, 0, AL },
X+{"lvl.q", "?n3x,A(b)", 0, (int) M_LVLQ_AB, INSN_MACRO, 0, AL },
X+{"lvr.q", "?n3x,?o(b)", 0xd4000002, 0xfc000002, CLD|RD_s|WR_CC, 0, AL },
X+{"lvr.q", "?n3x,A(b)", 0, (int) M_LVRQ_AB, INSN_MACRO, 0, AL },
X+{"svl.q", "?n3x,?o(b)", 0xf4000000, 0xfc000002, SM|RD_s|RD_C2, 0, AL },
X+{"svl.q", "?n3x,A(b)", 0, (int) M_SVLQ_AB, INSN_MACRO, 0, AL },
X+{"svr.q", "?n3x,?o(b)", 0xf4000002, 0xfc000002, SM|RD_s|RD_C2, 0, AL },
X+{"svr.q", "?n3x,A(b)", 0, (int) M_SVRQ_AB, INSN_MACRO, 0, AL },
X+{"mtv", "t,?d0z", 0x48e00000, 0xffe0ff80, LCD|WR_t|WR_C2, 0, AL },
X+{"mfv", "t,?d0z", 0x48600000, 0xffe0ff80, COD|RD_t|WR_CC|RD_C2, 0, AL },
X+{"mtvc", "t,?q", 0x48e00000, 0xffe0ff00, LCD|WR_t|WR_C2, 0, AL },
X+{"mfvc", "t,?q", 0x48600000, 0xffe0ff00, COD|RD_t|WR_CC|RD_C2, 0, AL },
X+{"vmtvc", "?q,?s0y", 0xd0510000, 0xffff8000, WR_C2, 0, AL },
X+{"vmfvc", "?d0z,?r", 0xd0500000, 0xffff0080, RD_C2, 0, AL },
X+{"vadd.q", "?d3d,?s3s,?t3t", 0x60008080, 0xff808080, RD_C2, 0, AL },
X+{"vsub.q", "?d3d,?s3s,?t3t", 0x60808080, 0xff808080, RD_C2, 0, AL },
X+{"vdiv.q", "?x3z,?s3y,?t3x", 0x63808080, 0xff808080, RD_C2, 0, AL },
X+{"vmul.q", "?d3d,?s3s,?t3t", 0x64008080, 0xff808080, RD_C2, 0, AL },
X+{"vdot.q", "?d0d,?s3s,?t3t", 0x64808080, 0xff808080, RD_C2, 0, AL },
X+{"vscl.q", "?d3d,?s3s,?t0x", 0x65008080, 0xff808080, RD_C2, 0, AL },
X+{"vhdp.q", "?d0d,?s3y,?t3t", 0x66008080, 0xff808080, RD_C2, 0, AL },
X+{"vcmp.q", "?f2,?s3s,?t3t", 0x6c008080, 0xff8080f0, RD_C2, 0, AL },
X+{"vcmp.q", "?f1,?s3s", 0x6c008080, 0xffff80f0, RD_C2, 0, AL },
X+{"vcmp.q", "?f0", 0x6c008080, 0xfffffff0, RD_C2, 0, AL },
X+{"vmin.q", "?d3d,?s3s,?t3t", 0x6d008080, 0xff808080, RD_C2, 0, AL },
X+{"vmax.q", "?d3d,?s3s,?t3t", 0x6d808080, 0xff808080, RD_C2, 0, AL },
X+{"vsgn.q", "?d3d,?s3s", 0xd04a8080, 0xffff8080, RD_C2, 0, AL },
X+{"vcst.q", "?d3d,?a", 0xd0608080, 0xffe0ff80, RD_C2, 0, AL },
X+{"vscmp.q", "?d3d,?s3s,?t3t", 0x6e808080, 0xff808080, RD_C2, 0, AL },
X+{"vsge.q", "?d3d,?s3s,?t3t", 0x6f008080, 0xff808080, RD_C2, 0, AL },
X+{"vslt.q", "?d3d,?s3s,?t3t", 0x6f808080, 0xff808080, RD_C2, 0, AL },
X+{"vi2uc.q", "?d0m,?s3w", 0xd03c8080, 0xffff8080, RD_C2, 0, AL },
X+{"vi2c.q", "?d0m,?s3w", 0xd03d8080, 0xffff8080, RD_C2, 0, AL },
X+{"vi2us.q", "?d1m,?s3w", 0xd03e8080, 0xffff8080, RD_C2, 0, AL },
X+{"vi2s.q", "?d1m,?s3w", 0xd03f8080, 0xffff8080, RD_C2, 0, AL },
X+{"vmov.q", "?d3d,?s3s", 0xd0008080, 0xffff8080, RD_C2, 0, AL },
X+{"vabs.q", "?d3d,?s3w", 0xd0018080, 0xffff8080, RD_C2, 0, AL },
X+{"vneg.q", "?d3d,?s3w", 0xd0028080, 0xffff8080, RD_C2, 0, AL },
X+{"vidt.q", "?d3d", 0xd0038080, 0xffffff80, RD_C2, 0, AL },
X+{"vsat0.q", "?d3z,?s3s", 0xd0048080, 0xffff8080, RD_C2, 0, AL },
X+{"vsat1.q", "?d3z,?s3s", 0xd0058080, 0xffff8080, RD_C2, 0, AL },
X+{"vzero.q", "?d3d", 0xd0068080, 0xffffff80, RD_C2, 0, AL },
X+{"vone.q", "?d3d", 0xd0078080, 0xffffff80, RD_C2, 0, AL },
X+{"vrcp.q", "?x3z,?s3y", 0xd0108080, 0xffff8080, RD_C2, 0, AL },
X+{"vrsq.q", "?x3z,?s3y", 0xd0118080, 0xffff8080, RD_C2, 0, AL },
X+{"vsin.q", "?x3z,?s3y", 0xd0128080, 0xffff8080, RD_C2, 0, AL },
X+{"vcos.q", "?x3z,?s3y", 0xd0138080, 0xffff8080, RD_C2, 0, AL },
X+{"vexp2.q", "?x3z,?s3y", 0xd0148080, 0xffff8080, RD_C2, 0, AL },
X+{"vlog2.q", "?x3z,?s3y", 0xd0158080, 0xffff8080, RD_C2, 0, AL },
X+{"vsqrt.q", "?x3z,?s3y", 0xd0168080, 0xffff8080, RD_C2, 0, AL },
X+{"vasin.q", "?x3z,?s3y", 0xd0178080, 0xffff8080, RD_C2, 0, AL },
X+{"vnrcp.q", "?x3z,?s3y", 0xd0188080, 0xffff8080, RD_C2, 0, AL },
X+{"vnsin.q", "?x3z,?s3y", 0xd01a8080, 0xffff8080, RD_C2, 0, AL },
X+{"vrexp2.q", "?x3z,?s3y", 0xd01c8080, 0xffff8080, RD_C2, 0, AL },
X+{"vrndi.q", "?d3z", 0xd0218080, 0xffffff80, RD_C2, 0, AL },
X+{"vrndf1.q", "?d3z", 0xd0228080, 0xffffff80, RD_C2, 0, AL },
X+{"vrndf2.q", "?d3z", 0xd0238080, 0xffffff80, RD_C2, 0, AL },
X+{"vf2h.q", "?d1m,?s3s", 0xd0328080, 0xffff8080, RD_C2, 0, AL },
X+{"vsrt1.q", "?d3d,?s3s", 0xd0408080, 0xffff8080, RD_C2, 0, AL },
X+{"vsrt2.q", "?d3d,?s3s", 0xd0418080, 0xffff8080, RD_C2, 0, AL },
X+{"vsrt3.q", "?d3d,?s3s", 0xd0488080, 0xffff8080, RD_C2, 0, AL },
X+{"vsrt4.q", "?d3d,?s3s", 0xd0498080, 0xffff8080, RD_C2, 0, AL },
X+{"vbfy1.q", "?d3d,?s3s", 0xd0428080, 0xffff8080, RD_C2, 0, AL },
X+{"vbfy2.q", "?d3d,?s3s", 0xd0438080, 0xffff8080, RD_C2, 0, AL },
X+{"vocp.q", "?d3d,?s3y", 0xd0448080, 0xffff8080, RD_C2, 0, AL },
X+{"vfad.q", "?d0d,?s3s", 0xd0468080, 0xffff8080, RD_C2, 0, AL },
X+{"vavg.q", "?d0d,?s3s", 0xd0478080, 0xffff8080, RD_C2, 0, AL },
X+{"vf2in.q", "?d3m,?s3s,?b", 0xd2008080, 0xffe08080, RD_C2, 0, AL },
X+{"vf2iz.q", "?d3m,?s3s,?b", 0xd2208080, 0xffe08080, RD_C2, 0, AL },
X+{"vf2iu.q", "?d3m,?s3s,?b", 0xd2408080, 0xffe08080, RD_C2, 0, AL },
X+{"vf2id.q", "?d3m,?s3s,?b", 0xd2608080, 0xffe08080, RD_C2, 0, AL },
X+{"vi2f.q", "?d3d,?s3w,?b", 0xd2808080, 0xffe08080, RD_C2, 0, AL },
X+{"vcmov.q", "?d3d,?s3s,?e", 0, (int) M_VCMOVQ, INSN_MACRO, 0, AL },
X+{"vcmovt.q", "?d3d,?s3s,?e", 0xd2a08080, 0xfff88080, RD_C2, 0, AL },
X+{"vcmovf.q", "?d3d,?s3s,?e", 0xd2a88080, 0xfff88080, RD_C2, 0, AL },
X+{"vmmul.q", "?v7z,?s7y,?t7x", 0xf0008080, 0xff808080, RD_C2, 0, AL },
X+{"vtfm4.q", "?v3z,?s7y,?t3x", 0xf1808080, 0xff808080, RD_C2, 0, AL },
X+{"vhtfm4.q", "?v3z,?s7y,?t3x", 0xf1808000, 0xff808080, RD_C2, 0, AL },
X+{"vmscl.q", "?x7z,?s7y,?t0x", 0xf2008080, 0xff808080, RD_C2, 0, AL },
X+{"vqmul.q", "?v3z,?s3y,?t3x", 0xf2808080, 0xff808080, RD_C2, 0, AL },
X+{"vmmov.q", "?x7z,?s7y", 0xf3808080, 0xffff8080, RD_C2, 0, AL },
X+{"vmidt.q", "?d7z", 0xf3838080, 0xffffff80, RD_C2, 0, AL },
X+{"vmzero.q", "?d7z", 0xf3868080, 0xffffff80, RD_C2, 0, AL },
X+{"vmone.q", "?d7z", 0xf3878080, 0xffffff80, RD_C2, 0, AL },
X+{"vrot.q", "?x3z,?s0y,?w", 0xf3a08080, 0xffe08080, RD_C2, 0, AL },
X+{"vt4444.q", "?d1z,?s3w", 0xd0598080, 0xffff8080, RD_C2, 0, AL },
X+{"vt5551.q", "?d1z,?s3w", 0xd05a8080, 0xffff8080, RD_C2, 0, AL },
X+{"vt5650.q", "?d1z,?s3w", 0xd05b8080, 0xffff8080, RD_C2, 0, AL },
X+{"vadd.t", "?d2d,?s2s,?t2t", 0x60008000, 0xff808080, RD_C2, 0, AL },
X+{"vsub.t", "?d2d,?s2s,?t2t", 0x60808000, 0xff808080, RD_C2, 0, AL },
X+{"vdiv.t", "?x2z,?s2y,?t2x", 0x63808000, 0xff808080, RD_C2, 0, AL },
X+{"vmul.t", "?d2d,?s2s,?t2t", 0x64008000, 0xff808080, RD_C2, 0, AL },
X+{"vdot.t", "?d0d,?s2s,?t2t", 0x64808000, 0xff808080, RD_C2, 0, AL },
X+{"vscl.t", "?d2d,?s2s,?t0x", 0x65008000, 0xff808080, RD_C2, 0, AL },
X+{"vhdp.t", "?d0d,?s2y,?t2t", 0x66008000, 0xff808080, RD_C2, 0, AL },
X+{"vcrs.t", "?d2d,?s2y,?t2x", 0x66808000, 0xff808080, RD_C2, 0, AL },
X+{"vcmp.t", "?f2,?s2s,?t2t", 0x6c008000, 0xff8080f0, RD_C2, 0, AL },
X+{"vcmp.t", "?f1,?s2s", 0x6c008000, 0xffff80f0, RD_C2, 0, AL },
X+{"vcmp.t", "?f0", 0x6c008000, 0xfffffff0, RD_C2, 0, AL },
X+{"vmin.t", "?d2d,?s2s,?t2t", 0x6d008000, 0xff808080, RD_C2, 0, AL },
X+{"vmax.t", "?d2d,?s2s,?t2t", 0x6d808000, 0xff808080, RD_C2, 0, AL },
X+{"vsgn.t", "?d2d,?s2s", 0xd04a8000, 0xffff8080, RD_C2, 0, AL },
X+{"vcst.t", "?d2d,?a", 0xd0608000, 0xffe0ff80, RD_C2, 0, AL },
X+{"vscmp.t", "?d2d,?s2s,?t2t", 0x6e808000, 0xff808080, RD_C2, 0, AL },
X+{"vsge.t", "?d2d,?s2s,?t2t", 0x6f008000, 0xff808080, RD_C2, 0, AL },
X+{"vslt.t", "?d2d,?s2s,?t2t", 0x6f808000, 0xff808080, RD_C2, 0, AL },
X+{"vmov.t", "?d2d,?s2s", 0xd0008000, 0xffff8080, RD_C2, 0, AL },
X+{"vabs.t", "?d2d,?s2w", 0xd0018000, 0xffff8080, RD_C2, 0, AL },
X+{"vneg.t", "?d2d,?s2w", 0xd0028000, 0xffff8080, RD_C2, 0, AL },
X+{"vsat0.t", "?d2z,?s2s", 0xd0048000, 0xffff8080, RD_C2, 0, AL },
X+{"vsat1.t", "?d2z,?s2s", 0xd0058000, 0xffff8080, RD_C2, 0, AL },
X+{"vzero.t", "?d2d", 0xd0068000, 0xffffff80, RD_C2, 0, AL },
X+{"vone.t", "?d2d", 0xd0078000, 0xffffff80, RD_C2, 0, AL },
X+{"vrcp.t", "?x2z,?s2y", 0xd0108000, 0xffff8080, RD_C2, 0, AL },
X+{"vrsq.t", "?x2z,?s2y", 0xd0118000, 0xffff8080, RD_C2, 0, AL },
X+{"vsin.t", "?x2z,?s2y", 0xd0128000, 0xffff8080, RD_C2, 0, AL },
X+{"vcos.t", "?x2z,?s2y", 0xd0138000, 0xffff8080, RD_C2, 0, AL },
X+{"vexp2.t", "?x2z,?s2y", 0xd0148000, 0xffff8080, RD_C2, 0, AL },
X+{"vlog2.t", "?x2z,?s2y", 0xd0158000, 0xffff8080, RD_C2, 0, AL },
X+{"vsqrt.t", "?x2z,?s2y", 0xd0168000, 0xffff8080, RD_C2, 0, AL },
X+{"vasin.t", "?x2z,?s2y", 0xd0178000, 0xffff8080, RD_C2, 0, AL },
X+{"vnrcp.t", "?x2z,?s2y", 0xd0188000, 0xffff8080, RD_C2, 0, AL },
X+{"vnsin.t", "?x2z,?s2y", 0xd01a8000, 0xffff8080, RD_C2, 0, AL },
X+{"vrexp2.t", "?x2z,?s2y", 0xd01c8000, 0xffff8080, RD_C2, 0, AL },
X+{"vrndi.t", "?d2z", 0xd0218000, 0xffffff80, RD_C2, 0, AL },
X+{"vrndf1.t", "?d2z", 0xd0228000, 0xffffff80, RD_C2, 0, AL },
X+{"vrndf2.t", "?d2z", 0xd0238000, 0xffffff80, RD_C2, 0, AL },
X+{"vocp.t", "?d2d,?s2y", 0xd0448000, 0xffff8080, RD_C2, 0, AL },
X+{"vfad.t", "?d0d,?s2s", 0xd0468000, 0xffff8080, RD_C2, 0, AL },
X+{"vavg.t", "?d0d,?s2s", 0xd0478000, 0xffff8080, RD_C2, 0, AL },
X+{"vf2in.t", "?d2m,?s2s,?b", 0xd2008000, 0xffe08080, RD_C2, 0, AL },
X+{"vf2iz.t", "?d2m,?s2s,?b", 0xd2208000, 0xffe08080, RD_C2, 0, AL },
X+{"vf2iu.t", "?d2m,?s2s,?b", 0xd2408000, 0xffe08080, RD_C2, 0, AL },
X+{"vf2id.t", "?d2m,?s2s,?b", 0xd2608000, 0xffe08080, RD_C2, 0, AL },
X+{"vi2f.t", "?d2d,?s2w,?b", 0xd2808000, 0xffe08080, RD_C2, 0, AL },
X+{"vcmov.t", "?d2d,?s2s,?e", 0, (int) M_VCMOVT, INSN_MACRO, 0, AL },
X+{"vcmovt.t", "?d2d,?s2s,?e", 0xd2a08000, 0xfff88080, RD_C2, 0, AL },
X+{"vcmovf.t", "?d2d,?s2s,?e", 0xd2a88000, 0xfff88080, RD_C2, 0, AL },
X+{"vmmul.t", "?v6z,?s6y,?t6x", 0xf0008000, 0xff808080, RD_C2, 0, AL },
X+{"vtfm3.t", "?v2z,?s6y,?t2x", 0xf1008000, 0xff808080, RD_C2, 0, AL },
X+{"vhtfm3.t", "?v2z,?s6y,?t2x", 0xf1000080, 0xff808080, RD_C2, 0, AL },
X+{"vmscl.t", "?x6z,?s6y,?t0x", 0xf2008000, 0xff808080, RD_C2, 0, AL },
X+{"vmmov.t", "?x6z,?s6y", 0xf3808000, 0xffff8080, RD_C2, 0, AL },
X+{"vmidt.t", "?d6z", 0xf3838000, 0xffffff80, RD_C2, 0, AL },
X+{"vmzero.t", "?d6z", 0xf3868000, 0xffffff80, RD_C2, 0, AL },
X+{"vmone.t", "?d6z", 0xf3878000, 0xffffff80, RD_C2, 0, AL },
X+{"vrot.t", "?x2z,?s0y,?w", 0xf3a08000, 0xffe08080, RD_C2, 0, AL },
X+{"vcrsp.t", "?d2z,?s2y,?t2x", 0xf2808000, 0xff808080, RD_C2, 0, AL },
X+{"vadd.p", "?d1d,?s1s,?t1t", 0x60000080, 0xff808080, RD_C2, 0, AL },
X+{"vsub.p", "?d1d,?s1s,?t1t", 0x60800080, 0xff808080, RD_C2, 0, AL },
X+{"vdiv.p", "?x1z,?s1y,?t1x", 0x63800080, 0xff808080, RD_C2, 0, AL },
X+{"vmul.p", "?d1d,?s1s,?t1t", 0x64000080, 0xff808080, RD_C2, 0, AL },
X+{"vdot.p", "?d0d,?s1s,?t1t", 0x64800080, 0xff808080, RD_C2, 0, AL },
X+{"vscl.p", "?d1d,?s1s,?t0x", 0x65000080, 0xff808080, RD_C2, 0, AL },
X+{"vhdp.p", "?d0d,?s1y,?t1t", 0x66000080, 0xff808080, RD_C2, 0, AL },
X+{"vdet.p", "?d0d,?s1s,?t1x", 0x67000080, 0xff808080, RD_C2, 0, AL },
X+{"vcmp.p", "?f2,?s1s,?t1t", 0x6c000080, 0xff8080f0, RD_C2, 0, AL },
X+{"vcmp.p", "?f1,?s1s", 0x6c000080, 0xffff80f0, RD_C2, 0, AL },
X+{"vcmp.p", "?f0", 0x6c000080, 0xfffffff0, RD_C2, 0, AL },
X+{"vmin.p", "?d1d,?s1s,?t1t", 0x6d000080, 0xff808080, RD_C2, 0, AL },
X+{"vmax.p", "?d1d,?s1s,?t1t", 0x6d800080, 0xff808080, RD_C2, 0, AL },
X+{"vsgn.p", "?d1d,?s1s", 0xd04a0080, 0xffff8080, RD_C2, 0, AL },
X+{"vcst.p", "?d1d,?a", 0xd0600080, 0xffe0ff80, RD_C2, 0, AL },
X+{"vscmp.p", "?d1d,?s1s,?t1t", 0x6e800080, 0xff808080, RD_C2, 0, AL },
X+{"vsge.p", "?d1d,?s1s,?t1t", 0x6f000080, 0xff808080, RD_C2, 0, AL },
X+{"vslt.p", "?d1d,?s1s,?t1t", 0x6f800080, 0xff808080, RD_C2, 0, AL },
X+{"vus2i.p", "?d3m,?s1y", 0xd03a0080, 0xffff8080, RD_C2, 0, AL },
X+{"vs2i.p", "?d3m,?s1y", 0xd03b0080, 0xffff8080, RD_C2, 0, AL },
X+{"vi2us.p", "?d0m,?s1w", 0xd03e0080, 0xffff8080, RD_C2, 0, AL },
X+{"vi2s.p", "?d0m,?s1w", 0xd03f0080, 0xffff8080, RD_C2, 0, AL },
X+{"vmov.p", "?d1d,?s1s", 0xd0000080, 0xffff8080, RD_C2, 0, AL },
X+{"vabs.p", "?d1d,?s1w", 0xd0010080, 0xffff8080, RD_C2, 0, AL },
X+{"vneg.p", "?d1d,?s1w", 0xd0020080, 0xffff8080, RD_C2, 0, AL },
X+{"vidt.p", "?d1d", 0xd0030080, 0xffffff80, RD_C2, 0, AL },
X+{"vsat0.p", "?d1z,?s1s", 0xd0040080, 0xffff8080, RD_C2, 0, AL },
X+{"vsat1.p", "?d1z,?s1s", 0xd0050080, 0xffff8080, RD_C2, 0, AL },
X+{"vzero.p", "?d1d", 0xd0060080, 0xffffff80, RD_C2, 0, AL },
X+{"vone.p", "?d1d", 0xd0070080, 0xffffff80, RD_C2, 0, AL },
X+{"vrcp.p", "?x1z,?s1y", 0xd0100080, 0xffff8080, RD_C2, 0, AL },
X+{"vrsq.p", "?x1z,?s1y", 0xd0110080, 0xffff8080, RD_C2, 0, AL },
X+{"vsin.p", "?x1z,?s1y", 0xd0120080, 0xffff8080, RD_C2, 0, AL },
X+{"vcos.p", "?x1z,?s1y", 0xd0130080, 0xffff8080, RD_C2, 0, AL },
X+{"vexp2.p", "?x1z,?s1y", 0xd0140080, 0xffff8080, RD_C2, 0, AL },
X+{"vlog2.p", "?x1z,?s1y", 0xd0150080, 0xffff8080, RD_C2, 0, AL },
X+{"vsqrt.p", "?x1z,?s1y", 0xd0160080, 0xffff8080, RD_C2, 0, AL },
X+{"vasin.p", "?x1z,?s1y", 0xd0170080, 0xffff8080, RD_C2, 0, AL },
X+{"vnrcp.p", "?x1z,?s1y", 0xd0180080, 0xffff8080, RD_C2, 0, AL },
X+{"vnsin.p", "?x1z,?s1y", 0xd01a0080, 0xffff8080, RD_C2, 0, AL },
X+{"vrexp2.p", "?x1z,?s1y", 0xd01c0080, 0xffff8080, RD_C2, 0, AL },
X+{"vrndi.p", "?d1z", 0xd0210080, 0xffffff80, RD_C2, 0, AL },
X+{"vrndf1.p", "?d1z", 0xd0220080, 0xffffff80, RD_C2, 0, AL },
X+{"vrndf2.p", "?d1z", 0xd0230080, 0xffffff80, RD_C2, 0, AL },
X+{"vf2h.p", "?d0m,?s1s", 0xd0320080, 0xffff8080, RD_C2, 0, AL },
X+{"vh2f.p", "?d3d,?s1y", 0xd0330080, 0xffff8080, RD_C2, 0, AL },
X+{"vbfy1.p", "?d1d,?s1s", 0xd0420080, 0xffff8080, RD_C2, 0, AL },
X+{"vocp.p", "?d1d,?s1y", 0xd0440080, 0xffff8080, RD_C2, 0, AL },
X+{"vsocp.p", "?d3z,?s1y", 0xd0450080, 0xffff8080, RD_C2, 0, AL },
X+{"vfad.p", "?d0d,?s1s", 0xd0460080, 0xffff8080, RD_C2, 0, AL },
X+{"vavg.p", "?d0d,?s1s", 0xd0470080, 0xffff8080, RD_C2, 0, AL },
X+{"vf2in.p", "?d1m,?s1s,?b", 0xd2000080, 0xffe08080, RD_C2, 0, AL },
X+{"vf2iz.p", "?d1m,?s1s,?b", 0xd2200080, 0xffe08080, RD_C2, 0, AL },
X+{"vf2iu.p", "?d1m,?s1s,?b", 0xd2400080, 0xffe08080, RD_C2, 0, AL },
X+{"vf2id.p", "?d1m,?s1s,?b", 0xd2600080, 0xffe08080, RD_C2, 0, AL },
X+{"vi2f.p", "?d1d,?s1w,?b", 0xd2800080, 0xffe08080, RD_C2, 0, AL },
X+{"vcmov.p", "?d1d,?s1s,?e", 0, (int) M_VCMOVP, INSN_MACRO, 0, AL },
X+{"vcmovt.p", "?d1d,?s1s,?e", 0xd2a00080, 0xfff88080, RD_C2, 0, AL },
X+{"vcmovf.p", "?d1d,?s1s,?e", 0xd2a80080, 0xfff88080, RD_C2, 0, AL },
X+{"vmmul.p", "?v5z,?s5y,?t5x", 0xf0000080, 0xff808080, RD_C2, 0, AL },
X+{"vtfm2.p", "?v1z,?s5y,?t1x", 0xf0800080, 0xff808080, RD_C2, 0, AL },
X+{"vhtfm2.p", "?v1z,?s5y,?t1x", 0xf0800000, 0xff808080, RD_C2, 0, AL },
X+{"vmscl.p", "?x5z,?s5y,?t0x", 0xf2000080, 0xff808080, RD_C2, 0, AL },
X+{"vmmov.p", "?x5z,?s5y", 0xf3800080, 0xffff8080, RD_C2, 0, AL },
X+{"vmidt.p", "?d5z", 0xf3830080, 0xffffff80, RD_C2, 0, AL },
X+{"vmzero.p", "?d5z", 0xf3860080, 0xffffff80, RD_C2, 0, AL },
X+{"vmone.p", "?d5z", 0xf3870080, 0xffffff80, RD_C2, 0, AL },
X+{"vrot.p", "?x1z,?s0y,?w", 0xf3a00080, 0xffe08080, RD_C2, 0, AL },
X+{"vadd.s", "?d0d,?s0s,?t0t", 0x60000000, 0xff808080, RD_C2, 0, AL },
X+{"vsub.s", "?d0d,?s0s,?t0t", 0x60800000, 0xff808080, RD_C2, 0, AL },
X+{"vdiv.s", "?x0d,?s0s,?t0t", 0x63800000, 0xff808080, RD_C2, 0, AL },
X+{"vmul.s", "?d0d,?s0s,?t0t", 0x64000000, 0xff808080, RD_C2, 0, AL },
X+{"vcmp.s", "?f2,?s0s,?t0t", 0x6c000000, 0xff8080f0, RD_C2, 0, AL },
X+{"vcmp.s", "?f1,?s0s", 0x6c000000, 0xffff80f0, RD_C2, 0, AL },
X+{"vcmp.s", "?f0", 0x6c000000, 0xfffffff0, RD_C2, 0, AL },
X+{"vmin.s", "?d0d,?s0s,?t0t", 0x6d000000, 0xff808080, RD_C2, 0, AL },
X+{"vmax.s", "?d0d,?s0s,?t0t", 0x6d800000, 0xff808080, RD_C2, 0, AL },
X+{"vsgn.s", "?d0d,?s0s", 0xd04a0000, 0xffff8080, RD_C2, 0, AL },
X+{"vcst.s", "?d0d,?a", 0xd0600000, 0xffe0ff80, RD_C2, 0, AL },
X+{"vscmp.s", "?d0d,?s0s,?t0t", 0x6e800000, 0xff808080, RD_C2, 0, AL },
X+{"vsge.s", "?d0d,?s0s,?t0t", 0x6f000000, 0xff808080, RD_C2, 0, AL },
X+{"vslt.s", "?d0d,?s0s,?t0t", 0x6f800000, 0xff808080, RD_C2, 0, AL },
X+{"vus2i.s", "?d1m,?s0y", 0xd03a0000, 0xffff8080, RD_C2, 0, AL },
X+{"vs2i.s", "?d1m,?s0y", 0xd03b0000, 0xffff8080, RD_C2, 0, AL },
X+{"vmov.s", "?d0d,?s0s", 0xd0000000, 0xffff8080, RD_C2, 0, AL },
X+{"vabs.s", "?d0d,?s0w", 0xd0010000, 0xffff8080, RD_C2, 0, AL },
X+{"vneg.s", "?d0d,?s0w", 0xd0020000, 0xffff8080, RD_C2, 0, AL },
X+{"vsat0.s", "?d0z,?s0s", 0xd0040000, 0xffff8080, RD_C2, 0, AL },
X+{"vsat1.s", "?d0z,?s0s", 0xd0050000, 0xffff8080, RD_C2, 0, AL },
X+{"vzero.s", "?d0d", 0xd0060000, 0xffffff80, RD_C2, 0, AL },
X+{"vone.s", "?d0d", 0xd0070000, 0xffffff80, RD_C2, 0, AL },
X+{"vrcp.s", "?x0d,?s0s", 0xd0100000, 0xffff8080, RD_C2, 0, AL },
X+{"vrsq.s", "?x0d,?s0s", 0xd0110000, 0xffff8080, RD_C2, 0, AL },
X+{"vsin.s", "?x0d,?s0s", 0xd0120000, 0xffff8080, RD_C2, 0, AL },
X+{"vcos.s", "?x0d,?s0s", 0xd0130000, 0xffff8080, RD_C2, 0, AL },
X+{"vexp2.s", "?x0d,?s0s", 0xd0140000, 0xffff8080, RD_C2, 0, AL },
X+{"vlog2.s", "?x0d,?s0s", 0xd0150000, 0xffff8080, RD_C2, 0, AL },
X+{"vsqrt.s", "?x0d,?s0s", 0xd0160000, 0xffff8080, RD_C2, 0, AL },
X+{"vasin.s", "?x0d,?s0s", 0xd0170000, 0xffff8080, RD_C2, 0, AL },
X+{"vnrcp.s", "?x0d,?s0y", 0xd0180000, 0xffff8080, RD_C2, 0, AL },
X+{"vnsin.s", "?x0d,?s0y", 0xd01a0000, 0xffff8080, RD_C2, 0, AL },
X+{"vrexp2.s", "?x0d,?s0y", 0xd01c0000, 0xffff8080, RD_C2, 0, AL },
X+{"vrnds.s", "?s0y", 0xd0200000, 0xffff80ff, RD_C2, 0, AL },
X+{"vrndi.s", "?d0d", 0xd0210000, 0xffffff80, RD_C2, 0, AL },
X+{"vrndf1.s", "?d0d", 0xd0220000, 0xffffff80, RD_C2, 0, AL },
X+{"vrndf2.s", "?d0d", 0xd0230000, 0xffffff80, RD_C2, 0, AL },
X+{"vh2f.s", "?d1d,?s0y", 0xd0330000, 0xffff8080, RD_C2, 0, AL },
X+{"vsbz.s", "?d0d,?s0s", 0xd0360000, 0xffff8080, RD_C2, 0, AL },
X+{"vsbn.s", "?d0d,?s0s,?t0t", 0x61000000, 0xff808080, RD_C2, 0, AL },
X+{"vlgb.s", "?d0d,?s0s", 0xd0370000, 0xffff8080, RD_C2, 0, AL },
X+{"vocp.s", "?d0d,?s0y", 0xd0440000, 0xffff8080, RD_C2, 0, AL },
X+{"vsocp.s", "?d1z,?s0y", 0xd0450000, 0xffff8080, RD_C2, 0, AL },
X+{"vf2in.s", "?d0m,?s0s,?b", 0xd2000000, 0xffe08080, RD_C2, 0, AL },
X+{"vf2iz.s", "?d0m,?s0s,?b", 0xd2200000, 0xffe08080, RD_C2, 0, AL },
X+{"vf2iu.s", "?d0m,?s0s,?b", 0xd2400000, 0xffe08080, RD_C2, 0, AL },
X+{"vf2id.s", "?d0m,?s0s,?b", 0xd2600000, 0xffe08080, RD_C2, 0, AL },
X+{"vi2f.s", "?d0d,?s0w,?b", 0xd2800000, 0xffe08080, RD_C2, 0, AL },
X+{"vcmov.s", "?d0d,?s0s,?e", 0, (int) M_VCMOVS, INSN_MACRO, 0, AL },
X+{"vcmovt.s", "?d0d,?s0s,?e", 0xd2a00000, 0xfff88080, RD_C2, 0, AL },
X+{"vcmovf.s", "?d0d,?s0s,?e", 0xd2a80000, 0xfff88080, RD_C2, 0, AL },
X+{"vwbn.s", "?d0d,?s0s,?i", 0xd3000000, 0xff008080, RD_C2, 0, AL },
X+{"vpfxs", "?0,?1,?2,?3", 0xdc000000, 0xff000000, RD_C2, 0, AL },
X+{"vpfxt", "?0,?1,?2,?3", 0xdd000000, 0xff000000, RD_C2, 0, AL },
X+{"vpfxd", "?4,?5,?6,?7", 0xde000000, 0xff000000, RD_C2, 0, AL },
X+{"viim.s", "?t0d,j", 0xdf000000, 0xff800000, RD_C2, 0, AL },
X+{"vfim.s", "?t0d,?u", 0xdf800000, 0xff800000, RD_C2, 0, AL },
X+{"vnop", "", 0xffff0000, 0xffffffff, RD_C2, 0, AL },
X+{"vflush", "", 0xffff040d, 0xffffffff, RD_C2, 0, AL },
X+{"vsync", "", 0xffff0320, 0xffffffff, RD_C2, 0, AL },
X+{"vsync", "i", 0xffff0000, 0xffff0000, RD_C2, 0, AL },
X+
X /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
X instructions so they are here for the latters to take precedence. */
X {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
X@@ -1282,6 +1589,36 @@
X {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
X {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
X
X+/* Coprocessor 2 load/store operations overlap with the Allegrex VFPU
X+ instructions so they are here for the latters to take precedence. */
X+/* COP1 ldc1 and sdc1 and COP3 ldc3 and sdc3 also overlap with the VFPU. */
X+{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
X+{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
X+{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
X+{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
X+{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
X+{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
X+{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
X+{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
X+{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
X+{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
X+{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
X+{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
X+{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
X+{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
X+{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
X+{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
X+{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
X+{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
X+{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
X+{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
X+{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
X+{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
X+{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
X+{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
X+{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
X+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
X+
X /* No hazard protection on coprocessor instructions--they shouldn't
X change the state of the processor and if they do it's up to the
X user to put in nops as necessary. These are at the end so that the
END-of-psptoolchain-gdb/files/patch-opcodes-mips-opc.c
echo x - psptoolchain-gdb/files/patch-bfd-archures.c
sed 's/^X//' >psptoolchain-gdb/files/patch-bfd-archures.c << 'END-of-psptoolchain-gdb/files/patch-bfd-archures.c'
X--- bfd/archures.c.orig 2005-10-25 18:40:09.000000000 +0100
X+++ bfd/archures.c 2007-02-08 20:06:04.000000000 +0000
X@@ -154,6 +154,7 @@
X .#define bfd_mach_mips16 16
X .#define bfd_mach_mips5 5
X .#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
X+.#define bfd_mach_mips_allegrex 10111431 {* octal 'AL', 31 *}
X .#define bfd_mach_mipsisa32 32
X .#define bfd_mach_mipsisa32r2 33
X .#define bfd_mach_mipsisa64 64
END-of-psptoolchain-gdb/files/patch-bfd-archures.c
echo x - psptoolchain-gdb/files/patch-bfd-bfd-in2.h
sed 's/^X//' >psptoolchain-gdb/files/patch-bfd-bfd-in2.h << 'END-of-psptoolchain-gdb/files/patch-bfd-bfd-in2.h'
X--- bfd/bfd-in2.h.orig 2005-10-25 18:40:09.000000000 +0100
X+++ bfd/bfd-in2.h 2007-02-08 20:06:04.000000000 +0000
X@@ -1742,6 +1742,7 @@
X #define bfd_mach_mips16 16
X #define bfd_mach_mips5 5
X #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
X+#define bfd_mach_mips_allegrex 10111431 /* octal 'AL', 31 */
X #define bfd_mach_mipsisa32 32
X #define bfd_mach_mipsisa32r2 33
X #define bfd_mach_mipsisa64 64
END-of-psptoolchain-gdb/files/patch-bfd-bfd-in2.h
echo x - psptoolchain-gdb/files/patch-bfd-elfxx-mips.c
sed 's/^X//' >psptoolchain-gdb/files/patch-bfd-elfxx-mips.c << 'END-of-psptoolchain-gdb/files/patch-bfd-elfxx-mips.c'
X--- bfd/elfxx-mips.c.orig 2005-10-25 17:19:08.000000000 +0100
X+++ bfd/elfxx-mips.c 2007-02-08 20:06:04.000000000 +0000
X@@ -4666,6 +4666,9 @@
X case E_MIPS_MACH_SB1:
X return bfd_mach_mips_sb1;
X
X+ case E_MIPS_MACH_ALLEGREX:
X+ return bfd_mach_mips_allegrex;
X+
X default:
X switch (flags & EF_MIPS_ARCH)
X {
X@@ -7950,6 +7953,10 @@
X val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
X break;
X
X+ case bfd_mach_mips_allegrex:
X+ val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX;
X+ break;
X+
X case bfd_mach_mipsisa32:
X val = E_MIPS_ARCH_32;
X break;
X@@ -9648,6 +9655,7 @@
X /* MIPS II extensions. */
X { bfd_mach_mips4000, bfd_mach_mips6000 },
X { bfd_mach_mipsisa32, bfd_mach_mips6000 },
X+ { bfd_mach_mips_allegrex, bfd_mach_mips6000 },
X
X /* MIPS I extensions. */
X { bfd_mach_mips6000, bfd_mach_mips3000 },
END-of-psptoolchain-gdb/files/patch-bfd-elfxx-mips.c
echo x - psptoolchain-gdb/files/patch-gdb-remote.c
sed 's/^X//' >psptoolchain-gdb/files/patch-gdb-remote.c << 'END-of-psptoolchain-gdb/files/patch-gdb-remote.c'
X--- gdb/remote.c.orig 2005-07-20 03:56:43.000000000 +0100
X+++ gdb/remote.c 2007-02-08 20:06:12.000000000 +0000
X@@ -1953,6 +1953,7 @@
X int lose;
X CORE_ADDR text_addr, data_addr, bss_addr;
X struct section_offsets *offs;
X+ int i;
X
X putpkt ("qOffsets");
X
X@@ -2014,6 +2015,13 @@
X memcpy (offs, symfile_objfile->section_offsets,
X SIZEOF_N_SECTION_OFFSETS (symfile_objfile->num_sections));
X
X+ /* GDB is stupid, lets fix up all sections to the same address not just a few :P */
X+
X+ for(i = 0; i < symfile_objfile->num_sections; i++)
X+ {
X+ offs->offsets[i] = text_addr;
X+ }
X+#if 0
X offs->offsets[SECT_OFF_TEXT (symfile_objfile)] = text_addr;
X
X /* This is a temporary kludge to force data and bss to use the same offsets
X@@ -2022,6 +2030,7 @@
X
X offs->offsets[SECT_OFF_DATA (symfile_objfile)] = data_addr;
X offs->offsets[SECT_OFF_BSS (symfile_objfile)] = data_addr;
X+#endif
X
X objfile_relocate (symfile_objfile, offs);
X }
END-of-psptoolchain-gdb/files/patch-gdb-remote.c
echo x - psptoolchain-gdb/files/patch-include-elf-common.h
sed 's/^X//' >psptoolchain-gdb/files/patch-include-elf-common.h << 'END-of-psptoolchain-gdb/files/patch-include-elf-common.h'
X--- include/elf/common.h.orig 2005-09-30 16:12:52.000000000 +0100
X+++ include/elf/common.h 2007-02-08 20:06:04.000000000 +0000
X@@ -93,6 +93,7 @@
X #define ET_HIOS 0xFEFF /* Operating system-specific */
X #define ET_LOPROC 0xFF00 /* Processor-specific */
X #define ET_HIPROC 0xFFFF /* Processor-specific */
X+#define ET_PSPEXEC 0xFFA0 /* Sony PSP executable file */
X
X /* Values for e_machine, which identifies the architecture. These numbers
X are officially assigned by registry@caldera.com. See below for a list of
END-of-psptoolchain-gdb/files/patch-include-elf-common.h
echo x - psptoolchain-gdb/files/patch-include-elf-mips.h
sed 's/^X//' >psptoolchain-gdb/files/patch-include-elf-mips.h << 'END-of-psptoolchain-gdb/files/patch-include-elf-mips.h'
X--- include/elf/mips.h.orig 2005-05-10 11:21:10.000000000 +0100
X+++ include/elf/mips.h 2007-02-08 20:06:04.000000000 +0000
X@@ -212,6 +212,7 @@
X #define E_MIPS_MACH_5400 0x00910000
X #define E_MIPS_MACH_5500 0x00980000
X #define E_MIPS_MACH_9000 0x00990000
X+#define E_MIPS_MACH_ALLEGREX 0x00A20000
X
X /* Processor specific section indices. These sections do not actually
X exist. Symbols with a st_shndx field corresponding to one of these
END-of-psptoolchain-gdb/files/patch-include-elf-mips.h
echo x - psptoolchain-gdb/files/patch-opcodes-mips-dis.c
sed 's/^X//' >psptoolchain-gdb/files/patch-opcodes-mips-dis.c << 'END-of-psptoolchain-gdb/files/patch-opcodes-mips-dis.c'
X--- opcodes/mips-dis.c.orig 2005-09-06 19:46:57.000000000 +0100
X+++ opcodes/mips-dis.c 2007-02-08 20:06:04.000000000 +0000
X@@ -133,6 +133,139 @@
X "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
X };
X
X+static const char * const vfpu_sreg_names[128] = {
X+ "S000", "S010", "S020", "S030", "S100", "S110", "S120", "S130",
X+ "S200", "S210", "S220", "S230", "S300", "S310", "S320", "S330",
X+ "S400", "S410", "S420", "S430", "S500", "S510", "S520", "S530",
X+ "S600", "S610", "S620", "S630", "S700", "S710", "S720", "S730",
X+ "S001", "S011", "S021", "S031", "S101", "S111", "S121", "S131",
X+ "S201", "S211", "S221", "S231", "S301", "S311", "S321", "S331",
X+ "S401", "S411", "S421", "S431", "S501", "S511", "S521", "S531",
X+ "S601", "S611", "S621", "S631", "S701", "S711", "S721", "S731",
X+ "S002", "S012", "S022", "S032", "S102", "S112", "S122", "S132",
X+ "S202", "S212", "S222", "S232", "S302", "S312", "S322", "S332",
X+ "S402", "S412", "S422", "S432", "S502", "S512", "S522", "S532",
X+ "S602", "S612", "S622", "S632", "S702", "S712", "S722", "S732",
X+ "S003", "S013", "S023", "S033", "S103", "S113", "S123", "S133",
X+ "S203", "S213", "S223", "S233", "S303", "S313", "S323", "S333",
X+ "S403", "S413", "S423", "S433", "S503", "S513", "S523", "S533",
X+ "S603", "S613", "S623", "S633", "S703", "S713", "S723", "S733"
X+};
X+
X+static const char * const vfpu_vpreg_names[128] = {
X+ "C000", "C010", "C020", "C030", "C100", "C110", "C120", "C130",
X+ "C200", "C210", "C220", "C230", "C300", "C310", "C320", "C330",
X+ "C400", "C410", "C420", "C430", "C500", "C510", "C520", "C530",
X+ "C600", "C610", "C620", "C630", "C700", "C710", "C720", "C730",
X+ "R000", "R001", "R002", "R003", "R100", "R101", "R102", "R103",
X+ "R200", "R201", "R202", "R203", "R300", "R301", "R302", "R303",
X+ "R400", "R401", "R402", "R403", "R500", "R501", "R502", "R503",
X+ "R600", "R601", "R602", "R603", "R700", "R701", "R702", "R703",
X+ "C002", "C012", "C022", "C032", "C102", "C112", "C122", "C132",
X+ "C202", "C212", "C222", "C232", "C302", "C312", "C322", "C332",
X+ "C402", "C412", "C422", "C432", "C502", "C512", "C522", "C532",
X+ "C602", "C612", "C622", "C632", "C702", "C712", "C722", "C732",
X+ "R020", "R021", "R022", "R023", "R120", "R121", "R122", "R123",
X+ "R220", "R221", "R222", "R223", "R320", "R321", "R322", "R323",
X+ "R420", "R421", "R422", "R423", "R520", "R521", "R522", "R523",
X+ "R620", "R621", "R622", "R623", "R720", "R721", "R722", "R723"
X+};
X+
X+static const char * const vfpu_vtreg_names[128] = {
X+ "C000", "C010", "C020", "C030", "C100", "C110", "C120", "C130",
X+ "C200", "C210", "C220", "C230", "C300", "C310", "C320", "C330",
X+ "C400", "C410", "C420", "C430", "C500", "C510", "C520", "C530",
X+ "C600", "C610", "C620", "C630", "C700", "C710", "C720", "C730",
X+ "R000", "R001", "R002", "R003", "R100", "R101", "R102", "R103",
X+ "R200", "R201", "R202", "R203", "R300", "R301", "R302", "R303",
X+ "R400", "R401", "R402", "R403", "R500", "R501", "R502", "R503",
X+ "R600", "R601", "R602", "R603", "R700", "R701", "R702", "R703",
X+ "C001", "C011", "C021", "C031", "C101", "C111", "C121", "C131",
X+ "C201", "C211", "C221", "C231", "C301", "C311", "C321", "C331",
X+ "C401", "C411", "C421", "C431", "C501", "C511", "C521", "C531",
X+ "C601", "C611", "C621", "C631", "C701", "C711", "C721", "C731",
X+ "R010", "R011", "R012", "R013", "R110", "R111", "R112", "R113",
X+ "R210", "R211", "R212", "R213", "R310", "R311", "R312", "R313",
X+ "R410", "R411", "R412", "R413", "R510", "R511", "R512", "R513",
X+ "R610", "R611", "R612", "R613", "R710", "R711", "R712", "R713"
X+};
X+
X+static const char * const vfpu_vqreg_names[128] = {
X+ "C000", "C010", "C020", "C030", "C100", "C110", "C120", "C130",
X+ "C200", "C210", "C220", "C230", "C300", "C310", "C320", "C330",
X+ "C400", "C410", "C420", "C430", "C500", "C510", "C520", "C530",
X+ "C600", "C610", "C620", "C630", "C700", "C710", "C720", "C730",
X+ "R000", "R001", "R002", "R003", "R100", "R101", "R102", "R103",
X+ "R200", "R201", "R202", "R203", "R300", "R301", "R302", "R303",
X+ "R400", "R401", "R402", "R403", "R500", "R501", "R502", "R503",
X+ "R600", "R601", "R602", "R603", "R700", "R701", "R702", "R703",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", ""
X+};
X+
X+static const char * const vfpu_mpreg_names[128] = {
X+ "M000", "", "M020", "", "M100", "", "M120", "",
X+ "M200", "", "M220", "", "M300", "", "M320", "",
X+ "M400", "", "M420", "", "M500", "", "M520", "",
X+ "M600", "", "M620", "", "M700", "", "M720", "",
X+ "E000", "", "E002", "", "E100", "", "E102", "",
X+ "E200", "", "E202", "", "E300", "", "E302", "",
X+ "E400", "", "E402", "", "E500", "", "E502", "",
X+ "E600", "", "E602", "", "E700", "", "E702", "",
X+ "M002", "", "M022", "", "M102", "", "M122", "",
X+ "M202", "", "M222", "", "M302", "", "M322", "",
X+ "M402", "", "M422", "", "M502", "", "M522", "",
X+ "M602", "", "M622", "", "M702", "", "M722", "",
X+ "E020", "", "E022", "", "E120", "", "E122", "",
X+ "E220", "", "E222", "", "E320", "", "E322", "",
X+ "E420", "", "E422", "", "E520", "", "E522", "",
X+ "E620", "", "E622", "", "E720", "", "E722", ""
X+};
X+
X+static const char * const vfpu_mtreg_names[128] = {
X+ "M000", "M010", "", "", "M100", "M110", "", "",
X+ "M200", "M210", "", "", "M300", "M310", "", "",
X+ "M400", "M410", "", "", "M500", "M510", "", "",
X+ "M600", "M610", "", "", "M700", "M710", "", "",
X+ "E000", "E001", "", "", "E100", "E101", "", "",
X+ "E200", "E201", "", "", "E300", "E301", "", "",
X+ "E400", "E401", "", "", "E500", "E501", "", "",
X+ "E600", "E601", "", "", "E700", "E701", "", "",
X+ "M001", "M011", "", "", "M101", "M111", "", "",
X+ "M201", "M211", "", "", "M301", "M311", "", "",
X+ "M401", "M411", "", "", "M501", "M511", "", "",
X+ "M601", "M611", "", "", "M701", "M711", "", "",
X+ "E010", "E011", "", "", "E110", "E111", "", "",
X+ "E210", "E211", "", "", "E310", "E311", "", "",
X+ "E410", "E411", "", "", "E510", "E511", "", "",
X+ "E610", "E611", "", "", "E710", "E711", "", ""
X+};
X+
X+static const char * const vfpu_mqreg_names[128] = {
X+ "M000", "", "", "", "M100", "", "", "",
X+ "M200", "", "", "", "M300", "", "", "",
X+ "M400", "", "", "", "M500", "", "", "",
X+ "M600", "", "", "", "M700", "", "", "",
X+ "E000", "", "", "", "E100", "", "", "",
X+ "E200", "", "", "", "E300", "", "", "",
X+ "E400", "", "", "", "E500", "", "", "",
X+ "E600", "", "", "", "E700", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", "",
X+ "", "", "", "", "", "", "", ""
X+};
X+
X static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
X {
X { 16, 1, "c0_config1" },
X@@ -288,6 +421,55 @@
X "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
X };
X
X+static const char * const vfpu_cond_names[16] = {
X+ "FL", "EQ", "LT", "LE", "TR", "NE", "GE", "GT",
X+ "EZ", "EN", "EI", "ES", "NZ", "NN", "NI", "NS"
X+};
X+
X+static const char * const vfpu_const_names[20] = {
X+ "",
X+ "VFPU_HUGE",
X+ "VFPU_SQRT2",
X+ "VFPU_SQRT1_2",
X+ "VFPU_2_SQRTPI",
X+ "VFPU_2_PI",
X+ "VFPU_1_PI",
X+ "VFPU_PI_4",
X+ "VFPU_PI_2",
X+ "VFPU_PI",
X+ "VFPU_E",
X+ "VFPU_LOG2E",
X+ "VFPU_LOG10E",
X+ "VFPU_LN2",
X+ "VFPU_LN10",
X+ "VFPU_2PI",
X+ "VFPU_PI_6",
X+ "VFPU_LOG10TWO",
X+ "VFPU_LOG2TEN",
X+ "VFPU_SQRT3_2"
X+};
X+
X+#define VFPU_NUM_CONSTANTS \
X+ ((sizeof vfpu_const_names) / (sizeof (vfpu_const_names[0])))
X+const unsigned int vfpu_num_constants = VFPU_NUM_CONSTANTS;
X+
X+static const char * const vfpu_rwb_names[4] = {
X+ "wt", "wb", "", ""
X+};
X+
X+static const char * const pfx_cst_names[8] = {
X+ "0", "1", "2", "1/2", "3", "1/3", "1/4", "1/6"
X+};
X+
X+static const char * const pfx_swz_names[4] = {
X+ "x", "y", "z", "w"
X+};
X+
X+static const char * const pfx_sat_names[4] = {
X+ "", "[0:1]", "", "[-1:1]"
X+};
X+
X+
X struct mips_abi_choice
X {
X const char * name;
X@@ -363,6 +545,8 @@
X mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
X { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
X mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
X+ { "allegrex", 1, bfd_mach_mips_allegrex, CPU_ALLEGREX, ISA_MIPS2,
X+ mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
X
X /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
X Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
X@@ -1147,6 +1331,349 @@
X (l >> OP_SH_FT) & OP_MASK_FT);
X break;
X
X+ case '?':
X+ /* VFPU extensions. */
X+ d++;
X+ switch (*d)
X+ {
X+ case '\0':
X+ /* xgettext:c-format */
X+ (*info->fprintf_func) (info->stream,
X+ _("# internal error, incomplete VFPU extension sequence (?)"));
X+ return;
X+
X+ case 'o':
X+ delta = (l >> OP_SH_VFPU_DELTA) & OP_MASK_VFPU_DELTA;
X+ if (delta & 0x8000)
X+ delta |= ~0xffff;
X+ (*info->fprintf_func) (info->stream, "%d",
X+ delta);
X+ break;
X+
X+ case '0':
X+ case '1':
X+ case '2':
X+ case '3':
X+ {
X+ unsigned int pos = *d, base = '0';
X+ unsigned int negation = (l >> (pos - (base - VFPU_SH_PFX_NEG))) & VFPU_MASK_PFX_NEG;
X+ unsigned int constant = (l >> (pos - (base - VFPU_SH_PFX_CST))) & VFPU_MASK_PFX_CST;
X+ unsigned int abs_consthi =
X+ (l >> (pos - (base - VFPU_SH_PFX_ABS_CSTHI))) & VFPU_MASK_PFX_ABS_CSTHI;
X+ unsigned int swz_constlo = (l >> ((pos - base) * 2)) & VFPU_MASK_PFX_SWZ_CSTLO;
X+
X+ if (negation)
X+ (*info->fprintf_func) (info->stream, "-");
X+ if (constant)
X+ {
X+ (*info->fprintf_func) (info->stream, "%s",
X+ pfx_cst_names[(abs_consthi << 2) | swz_constlo]);
X+ }
X+ else
X+ {
X+ if (abs_consthi)
X+ (*info->fprintf_func) (info->stream, "|%s|",
X+ pfx_swz_names[swz_constlo]);
X+ else
X+ (*info->fprintf_func) (info->stream, "%s",
X+ pfx_swz_names[swz_constlo]);
X+ }
X+ }
X+ break;
X+
X+ case '4':
X+ case '5':
X+ case '6':
X+ case '7':
X+ {
X+ unsigned int pos = *d, base = '4';
X+ unsigned int mask = (l >> (pos - (base - VFPU_MASK_PFX_MASK))) & VFPU_MASK_PFX_MASK;
X+ unsigned int saturation = (l >> ((pos - base) * 2)) & VFPU_MASK_PFX_SAT;
X+
X+ if (mask)
X+ (*info->fprintf_func) (info->stream, "m");
X+ else
X+ (*info->fprintf_func) (info->stream, "%s",
X+ pfx_sat_names[saturation]);
X+ }
X+ break;
X+
X+ case 'a':
X+ {
X+ unsigned int c = (l >> OP_SH_VFPU_CONST) & OP_MASK_VFPU_CONST;
X+ if (c < vfpu_num_constants)
X+ {
X+ (*info->fprintf_func) (info->stream, "%s",
X+ vfpu_const_names[c]);
X+ }
X+ break;
X+ }
X+
X+ case 'b':
X+ /* 5-bit immediate value. */
X+ (*info->fprintf_func) (info->stream, "%ld",
X+ (l >> OP_SH_VFPU_IMM5) & OP_MASK_VFPU_IMM5);
X+ break;
X+
X+ case 'c':
X+ /* VFPU condition code. */
X+ (*info->fprintf_func) (info->stream, "%ld",
X+ (l >> OP_SH_VFPU_CC) & OP_MASK_VFPU_CC);
X+ break;
X+
X+ case 'e':
X+ /* 3-bit immediate value. */
X+ (*info->fprintf_func) (info->stream, "%ld",
X+ (l >> OP_SH_VFPU_IMM3) & OP_MASK_VFPU_IMM3);
X+ break;
X+
X+ case 'f':
X+ /* Conditional compare. */
X+ (*info->fprintf_func) (info->stream, "%s",
X+ vfpu_cond_names[(l >> OP_SH_VFPU_COND) & OP_MASK_VFPU_COND]);
X+ /* Apparently this specifier is unused. */
X+ d++;
X+ break;
X+
X+ case 'i':
X+ /* 8-bit immediate value. */
X+ (*info->fprintf_func) (info->stream, "0x%02lx",
X+ (l >> OP_SH_VFPU_IMM8) & OP_MASK_VFPU_IMM8);
X+ break;
X+
X+ case 'q':
X+ /* VFPU control register (vmtvc). */
X+ (*info->fprintf_func) (info->stream, "$%ld",
X+ (l >> OP_SH_VFPU_VMTVC) & OP_MASK_VFPU_VMTVC);
X+ break;
X+
X+ case 'r':
X+ /* VFPU control register (vmfvc). */
X+ (*info->fprintf_func) (info->stream, "$%ld",
X+ (l >> OP_SH_VFPU_VMFVC) & OP_MASK_VFPU_VMFVC);
X+ break;
X+
X+ case 'u':
X+ /* Convert a VFPU 16-bit floating-point number to IEEE754. */
X+ {
X+ union float2int {
X+ unsigned int i;
X+ float f;
X+ } float2int;
X+ unsigned short float16 = (l >> OP_SH_VFPU_FLOAT16) & OP_MASK_VFPU_FLOAT16;
X+ unsigned int sign = (float16 >> VFPU_SH_FLOAT16_SIGN) & VFPU_MASK_FLOAT16_SIGN;
X+ int exponent = (float16 >> VFPU_SH_FLOAT16_EXP) & VFPU_MASK_FLOAT16_EXP;
X+ unsigned int fraction = float16 & VFPU_MASK_FLOAT16_FRAC;
X+ char signchar = '+' + ((sign == 1) * 2);
X+
X+ if (exponent == VFPU_FLOAT16_EXP_MAX)
X+ {
X+ if (fraction == 0)
X+ (*info->fprintf_func) (info->stream, "%cInf", signchar);
X+ else
X+ (*info->fprintf_func) (info->stream, "%cNaN", signchar);
X+ }
X+ else if (exponent == 0 && fraction == 0)
X+ {
X+ (*info->fprintf_func) (info->stream, "%c0", signchar);
X+ }
X+ else
X+ {
X+ if (exponent == 0)
X+ {
X+ do
X+ {
X+ fraction <<= 1;
X+ exponent--;
X+ }
X+ while (!(fraction & (VFPU_MASK_FLOAT16_FRAC + 1)));
X+
X+ fraction &= VFPU_MASK_FLOAT16_FRAC;
X+ }
X+
X+ /* Convert to 32-bit single-precision IEEE754. */
X+ float2int.i = sign << 31;
X+ float2int.i |= (exponent + 112) << 23;
X+ float2int.i |= fraction << 13;
X+ (*info->fprintf_func) (info->stream, "%g", float2int.f);
X+ }
X+ }
X+ break;
X+
X+ case 'w':
X+ {
X+ const char *elements[4];
X+ unsigned int opcode = l & VFPU_MASK_OP_SIZE;
X+ unsigned int rotators = (l >> OP_SH_VFPU_ROT) & OP_MASK_VFPU_ROT;
X+ unsigned int opsize, rothi, rotlo, negation, i;
X+
X+ /* Determine the operand size so we'll know how many elements to output. */
X+ if (opcode == VFPU_OP_SIZE_PAIR)
X+ opsize = 2;
X+ else if (opcode == VFPU_OP_SIZE_TRIPLE)
X+ opsize = 3;
X+ else
X+ opsize = (opcode == VFPU_OP_SIZE_QUAD) * 4; /* Sanity check. */
X+
X+ rothi = (rotators >> VFPU_SH_ROT_HI) & VFPU_MASK_ROT_HI;
X+ rotlo = (rotators >> VFPU_SH_ROT_LO) & VFPU_MASK_ROT_LO;
X+ negation = (rotators >> VFPU_SH_ROT_NEG) & VFPU_MASK_ROT_NEG;
X+
X+ if (rothi == rotlo)
X+ {
X+ if (negation)
X+ {
X+ elements[0] = "-s";
X+ elements[1] = "-s";
X+ elements[2] = "-s";
X+ elements[3] = "-s";
X+ }
X+ else
X+ {
X+ elements[0] = "s";
X+ elements[1] = "s";
X+ elements[2] = "s";
X+ elements[3] = "s";
X+ }
X+ }
X+ else
X+ {
X+ elements[0] = "0";
X+ elements[1] = "0";
X+ elements[2] = "0";
X+ elements[3] = "0";
X+ }
X+ if (negation)
X+ elements[rothi] = "-s";
X+ else
X+ elements[rothi] = "s";
X+ elements[rotlo] = "c";
X+
X+ (*info->fprintf_func) (info->stream, "[");
X+ i = 0;
X+ for (;;)
X+ {
X+ (*info->fprintf_func) (info->stream, "%s",
X+ elements[i++]);
X+ if (i >= opsize)
X+ break;
X+ (*info->fprintf_func) (info->stream, ",");
X+ }
X+ (*info->fprintf_func) (info->stream, "]");
X+ }
X+ break;
X+
X+ case 'd':
X+ case 'm':
X+ case 'n':
X+ case 's':
X+ case 't':
X+ case 'v':
X+ case 'x':
X+ {
X+ unsigned int vreg = 0;
X+
X+ /* The first char specifies the bitfield that contains the register number. */
X+ switch (*d)
X+ {
X+ case 'd':
X+ case 'v':
X+ case 'x':
X+ vreg = (l >> OP_SH_VFPU_VD) & OP_MASK_VFPU_VD;
X+ break;
X+
X+ case 'm':
X+ /* Combine bits 0-4 of vt with bits 5-6 of vt. */
X+ vreg = ((l >> OP_SH_VFPU_VT_LO) & OP_MASK_VFPU_VT_LO)
X+ | ((l & OP_MASK_VFPU_VT_HI2) << OP_SH_VFPU_VT_HI);
X+ break;
X+
X+ case 'n':
X+ /* Combine bits 0-4 of vt with bit 5 of vt. */
X+ vreg = ((l >> OP_SH_VFPU_VT_LO) & OP_MASK_VFPU_VT_LO)
X+ | ((l & OP_MASK_VFPU_VT_HI1) << OP_SH_VFPU_VT_HI);
X+ break;
X+
X+ case 's':
X+ {
X+ unsigned int temp_vreg = l >> OP_SH_VFPU_VS;
X+
X+ vreg = temp_vreg & OP_MASK_VFPU_VS;
X+ if ((l & VFPU_OP_VT_VS_VD) == VFPU_OPCODE_VMMUL)
X+ {
X+ /* vmmul instructions have the RXC bit (bit 13) inverted. */
X+ if (temp_vreg & 0x20)
X+ vreg = temp_vreg & 0x5f;
X+ else
X+ vreg |= 0x20;
X+ }
X+ }
X+ break;
X+
X+ case 't':
X+ vreg = (l >> OP_SH_VFPU_VT) & OP_MASK_VFPU_VT;
X+ break;
X+ }
X+
X+ /* The next char is the register set vreg comes from. */
X+ d++;
X+ switch (*d)
X+ {
X+ case '0':
X+ (*info->fprintf_func) (info->stream, "%s.s",
X+ vfpu_sreg_names[vreg]);
X+ break;
X+
X+ case '1':
X+ (*info->fprintf_func) (info->stream, "%s.p",
X+ vfpu_vpreg_names[vreg]);
X+ break;
X+
X+ case '2':
X+ (*info->fprintf_func) (info->stream, "%s.t",
X+ vfpu_vtreg_names[vreg]);
X+ break;
X+
X+ case '3':
X+ (*info->fprintf_func) (info->stream, "%s.q",
X+ vfpu_vqreg_names[vreg]);
X+ break;
X+
X+ case '5':
X+ (*info->fprintf_func) (info->stream, "%s.p",
X+ vfpu_mpreg_names[vreg]);
X+ break;
X+
X+ case '6':
X+ (*info->fprintf_func) (info->stream, "%s.t",
X+ vfpu_mtreg_names[vreg]);
X+ break;
X+
X+ case '7':
X+ (*info->fprintf_func) (info->stream, "%s.q",
X+ vfpu_mqreg_names[vreg]);
X+ break;
X+
X+ default:
X+ /* xgettext:c-format */
X+ (*info->fprintf_func) (info->stream,
X+ _("# internal error, undefined vreg modifier(%c)"),
X+ *d);
X+ break;
X+ }
X+
X+ /* The last char is unused for disassembly. */
X+ d++;
X+ }
X+ break;
X+
X+ case 'z':
X+ (*info->fprintf_func) (info->stream, "%s",
X+ vfpu_rwb_names[(l >> OP_SH_VFPU_RWB) & OP_MASK_VFPU_RWB]);
X+ break;
X+ }
X+ break;
X+
X default:
X /* xgettext:c-format */
X (*info->fprintf_func) (info->stream,
END-of-psptoolchain-gdb/files/patch-opcodes-mips-dis.c
echo x - psptoolchain-gdb/distinfo
sed 's/^X//' >psptoolchain-gdb/distinfo << 'END-of-psptoolchain-gdb/distinfo'
XMD5 (gdb-6.4.tar.bz2) = f62c14ba0316bc88e1b4b32a4e901ffb
XSHA256 (gdb-6.4.tar.bz2) = af6777836ab72b563a9e55467f990250e07e56c292cfac98762745c1512167ef
XSIZE (gdb-6.4.tar.bz2) = 13917226
END-of-psptoolchain-gdb/distinfo
exit
--- psptoolchain-gdb.shar ends here ---
>Release-Note:
>Audit-Trail:
>Unformatted:
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