From owner-freebsd-hackers@FreeBSD.ORG Wed Jun 22 21:06:42 2011 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id DCCDE106566C for ; Wed, 22 Jun 2011 21:06:42 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from cyrus.watson.org (cyrus.watson.org [65.122.17.42]) by mx1.freebsd.org (Postfix) with ESMTP id B1B758FC13 for ; Wed, 22 Jun 2011 21:06:42 +0000 (UTC) Received: from bigwig.baldwin.cx (66.111.2.69.static.nyinternet.net [66.111.2.69]) by cyrus.watson.org (Postfix) with ESMTPSA id 65F1346B1A; Wed, 22 Jun 2011 17:06:42 -0400 (EDT) Received: from jhbbsd.localnet (unknown [209.249.190.124]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id EA1338A01F; Wed, 22 Jun 2011 17:06:41 -0400 (EDT) From: John Baldwin To: freebsd-hackers@freebsd.org Date: Wed, 22 Jun 2011 16:32:52 -0400 User-Agent: KMail/1.13.5 (FreeBSD/8.2-CBSD-20110617; KDE/4.5.5; amd64; ; ) References: <357552.99021.qm@web180003.mail.gq1.yahoo.com> In-Reply-To: <357552.99021.qm@web180003.mail.gq1.yahoo.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201106221632.52300.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (bigwig.baldwin.cx); Wed, 22 Jun 2011 17:06:42 -0400 (EDT) Cc: Sushanth Rai Subject: Re: IPI and I/O interrupts X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Jun 2011 21:06:42 -0000 On Wednesday, June 22, 2011 3:59:06 am Sushanth Rai wrote: > Hi, > > I would like to understand little bit about the FreeBSD interrupt handling on x86. > > When a cpu is processing an IPI, let's say cpu is running IPI_STOP handler, are I/O interrupts like the timer interrupt disabled ? Conversely if the cpu is holding a spinlock, which means it has disabled interrupts, can it process an IPI. My understanding is executing "cli" instruction disables the maskable interrupts. I was wondering if IPIs are part of that. Yes, IPIs generally are blocked. We do use an NMI IPI when entering the debugger (and possibly during panics), but general IPIs like TLB shootdowns, etc. are all maskable interrupts. Also, all of the IPI handlers (and the lapic timer interrupt) operate like normal device interrupt handlers using interrupt gates (which block interrupts equivalent to cli). -- John Baldwin