From owner-svn-src-head@freebsd.org Thu Feb 27 15:34:32 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 5C8F824544A; Thu, 27 Feb 2020 15:34:32 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 48SxYN13CGz3Cjs; Thu, 27 Feb 2020 15:34:32 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id D162C1AEFF; Thu, 27 Feb 2020 15:34:31 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 01RFYVcO092592; Thu, 27 Feb 2020 15:34:31 GMT (envelope-from imp@FreeBSD.org) Received: (from imp@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 01RFYVnu092589; Thu, 27 Feb 2020 15:34:31 GMT (envelope-from imp@FreeBSD.org) Message-Id: <202002271534.01RFYVnu092589@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: imp set sender to imp@FreeBSD.org using -f From: Warner Losh Date: Thu, 27 Feb 2020 15:34:31 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r358393 - in head/sys: conf riscv/include X-SVN-Group: head X-SVN-Commit-Author: imp X-SVN-Commit-Paths: in head/sys: conf riscv/include X-SVN-Commit-Revision: 358393 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Feb 2020 15:34:32 -0000 Author: imp Date: Thu Feb 27 15:34:30 2020 New Revision: 358393 URL: https://svnweb.freebsd.org/changeset/base/358393 Log: Better check for floating point type. Use __riscv_flen instead of __riscv_float_abi_soft. While the latter works for userland (and one could argue it's more correct), it fails for the kernel. We compile the kernel with -mabi=lp64 (eg soft float abi) to avoid floating point instructions in the kernel. We also compile the kernel -march=rv64imafdc for hard float kernels (eg those with options FPE), but with -march=rv64imac for softfloat kernels (eg those with FPE). Since we do this, in the kernel (as in userland) __riscv_flen will be defined for 'riscv64' and not for 'riscv64sf'. This also removes the -DMACHINE_ARCH hack now that it's no longer needed. Longer term, we should return the ABI from the sysctl hw.machine_arch like on amd64 for i386 binaries. Suggested by: mhorne@ Differential Revision: https://reviews.freebsd.org/D23813 Modified: head/sys/conf/Makefile.riscv head/sys/conf/kern.mk head/sys/riscv/include/param.h Modified: head/sys/conf/Makefile.riscv ============================================================================== --- head/sys/conf/Makefile.riscv Thu Feb 27 15:30:13 2020 (r358392) +++ head/sys/conf/Makefile.riscv Thu Feb 27 15:34:30 2020 (r358393) @@ -46,10 +46,6 @@ SYSTEM_LD= @${LD} -N -m ${LD_EMULATION} -Bdynamic -T $ CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls .endif -# Currently, the compile flags don't let the kernel know if this is a hard-float -# ABI build or a soft-float ABI build. We need to pass in this information. -CFLAGS += -DMACHINE_ARCH=\"${MACHINE_ARCH}\" - # hack because genassym.c includes sys/bus.h which includes these. genassym.o: bus_if.h device_if.h Modified: head/sys/conf/kern.mk ============================================================================== --- head/sys/conf/kern.mk Thu Feb 27 15:30:13 2020 (r358392) +++ head/sys/conf/kern.mk Thu Feb 27 15:34:30 2020 (r358393) @@ -139,14 +139,23 @@ INLINE_LIMIT?= 8000 # # For RISC-V we specify the soft-float ABI (lp64) to avoid the use of floating -# point registers within the kernel. We also specify the "medium" code model, -# which generates code suitable for a 2GiB addressing range located at any -# offset, allowing modules to be located anywhere in the 64-bit address space. -# Note that clang and GCC refer to this code model as "medium" and "medany" -# respectively. +# point registers within the kernel. However, for kernels supporting hardware +# float (FPE), we have to include that in the march so we can have limited +# floating point support in context switching needed for that. This is different +# than userland where we use a hard-float ABI (lp64d). # +# We also specify the "medium" code model, which generates code suitable for a +# 2GiB addressing range located at any offset, allowing modules to be located +# anywhere in the 64-bit address space. Note that clang and GCC refer to this +# code model as "medium" and "medany" respectively. +# .if ${MACHINE_CPUARCH} == "riscv" -CFLAGS+= -march=rv64imafdc -mabi=lp64 +.if ${MACHINE_ARCH:Mriscv*sf} +CFLAGS+= -march=rv64imac +.else +CFLAGS+= -march=rv64imafdc +.endif +CFLAGS+= -mabi=lp64 CFLAGS.clang+= -mcmodel=medium CFLAGS.gcc+= -mcmodel=medany INLINE_LIMIT?= 8000 Modified: head/sys/riscv/include/param.h ============================================================================== --- head/sys/riscv/include/param.h Thu Feb 27 15:30:13 2020 (r358392) +++ head/sys/riscv/include/param.h Thu Feb 27 15:34:30 2020 (r358393) @@ -46,10 +46,17 @@ #define MACHINE "riscv" #endif #ifndef MACHINE_ARCH -#ifdef __riscv_float_abi_soft -#define MACHINE_ARCH "riscv64sf" -#else +/* + * Check to see if we're building with hardware floating instructions + * allowed. We check this instead of hard vs soft float ABI because we build the + * kernel with soft float ABI to avoid hard float instruction generation. If + * we ever allow a 'soft ABI but with hard floats' userland, then we'll need + * to rethink this. + */ +#ifdef __riscv_flen #define MACHINE_ARCH "riscv64" +#else +#define MACHINE_ARCH "riscv64sf" #endif #endif