From owner-svn-src-stable-12@freebsd.org Tue Jan 7 20:09:58 2020 Return-Path: Delivered-To: svn-src-stable-12@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id EF3FE1F17E5; Tue, 7 Jan 2020 20:09:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 47sk4k67RCz4Ycb; Tue, 7 Jan 2020 20:09:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id CDA1F45DF; Tue, 7 Jan 2020 20:09:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 007K9wJL003959; Tue, 7 Jan 2020 20:09:58 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 007K9wnD003957; Tue, 7 Jan 2020 20:09:58 GMT (envelope-from dim@FreeBSD.org) Message-Id: <202001072009.007K9wnD003957@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Tue, 7 Jan 2020 20:09:58 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r356468 - stable/12/contrib/llvm-project/llvm/lib/Target/X86 X-SVN-Group: stable-12 X-SVN-Commit-Author: dim X-SVN-Commit-Paths: stable/12/contrib/llvm-project/llvm/lib/Target/X86 X-SVN-Commit-Revision: 356468 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-12@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for only the 12-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Jan 2020 20:09:59 -0000 Author: dim Date: Tue Jan 7 20:09:58 2020 New Revision: 356468 URL: https://svnweb.freebsd.org/changeset/base/356468 Log: MFC r356256: Merge commit 468a0cb5f from llvm git (by Craig Topper): [X86] Add X87 FCMOV support to X86FlagsCopyLowering. Fixes PR44396 Merge commit 86f48999f from llvm git (by Craig Topper): [X86] Fix typo in getCMovOpcode. The 64-bit HasMemoryOperand line was using CMOV32rm instead of CMOV64rm. Not sure how to test this. We have no test coverage that passes true for HasMemoryOperand. This fixes 'Assertion failed: (MI.findRegisterDefOperand(X86::EFLAGS) && "Expected a def of EFLAGS for this instruction!"), function runOnMachineFunction' when compiling the misc/gpsim port for i386. Reported by: yuri Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=44396 Modified: stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp Directory Properties: stable/12/ (props changed) stable/12/contrib/llvm-project/llvm/ (props changed) Modified: stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp ============================================================================== --- stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp Tue Jan 7 20:09:02 2020 (r356467) +++ stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp Tue Jan 7 20:09:58 2020 (r356468) @@ -115,6 +115,10 @@ class X86FlagsCopyLoweringPass : public MachineFunctio MachineBasicBlock::iterator TestPos, DebugLoc TestLoc, MachineInstr &CMovI, MachineOperand &FlagUse, CondRegArray &CondRegs); + void rewriteFCMov(MachineBasicBlock &TestMBB, + MachineBasicBlock::iterator TestPos, DebugLoc TestLoc, + MachineInstr &CMovI, MachineOperand &FlagUse, + CondRegArray &CondRegs); void rewriteCondJmp(MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos, DebugLoc TestLoc, MachineInstr &JmpI, CondRegArray &CondRegs); @@ -334,6 +338,28 @@ static MachineBasicBlock &splitBlock(MachineBasicBlock return NewMBB; } +static X86::CondCode getCondFromFCMOV(unsigned Opcode) { + switch (Opcode) { + default: return X86::COND_INVALID; + case X86::CMOVBE_Fp32: case X86::CMOVBE_Fp64: case X86::CMOVBE_Fp80: + return X86::COND_BE; + case X86::CMOVB_Fp32: case X86::CMOVB_Fp64: case X86::CMOVB_Fp80: + return X86::COND_B; + case X86::CMOVE_Fp32: case X86::CMOVE_Fp64: case X86::CMOVE_Fp80: + return X86::COND_E; + case X86::CMOVNBE_Fp32: case X86::CMOVNBE_Fp64: case X86::CMOVNBE_Fp80: + return X86::COND_A; + case X86::CMOVNB_Fp32: case X86::CMOVNB_Fp64: case X86::CMOVNB_Fp80: + return X86::COND_AE; + case X86::CMOVNE_Fp32: case X86::CMOVNE_Fp64: case X86::CMOVNE_Fp80: + return X86::COND_NE; + case X86::CMOVNP_Fp32: case X86::CMOVNP_Fp64: case X86::CMOVNP_Fp80: + return X86::COND_NP; + case X86::CMOVP_Fp32: case X86::CMOVP_Fp64: case X86::CMOVP_Fp80: + return X86::COND_P; + } +} + bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName() << " **********\n"); @@ -593,6 +619,8 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(Ma // Otherwise we can just rewrite in-place. if (X86::getCondFromCMov(MI) != X86::COND_INVALID) { rewriteCMov(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs); + } else if (getCondFromFCMOV(MI.getOpcode()) != X86::COND_INVALID) { + rewriteFCMov(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs); } else if (X86::getCondFromSETCC(MI) != X86::COND_INVALID) { rewriteSetCC(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs); } else if (MI.getOpcode() == TargetOpcode::COPY) { @@ -849,6 +877,51 @@ void X86FlagsCopyLoweringPass::rewriteCMov(MachineBasi .setImm(Inverted ? X86::COND_E : X86::COND_NE); FlagUse.setIsKill(true); LLVM_DEBUG(dbgs() << " fixed cmov: "; CMovI.dump()); +} + +void X86FlagsCopyLoweringPass::rewriteFCMov(MachineBasicBlock &TestMBB, + MachineBasicBlock::iterator TestPos, + DebugLoc TestLoc, + MachineInstr &CMovI, + MachineOperand &FlagUse, + CondRegArray &CondRegs) { + // First get the register containing this specific condition. + X86::CondCode Cond = getCondFromFCMOV(CMovI.getOpcode()); + unsigned CondReg; + bool Inverted; + std::tie(CondReg, Inverted) = + getCondOrInverseInReg(TestMBB, TestPos, TestLoc, Cond, CondRegs); + + MachineBasicBlock &MBB = *CMovI.getParent(); + + // Insert a direct test of the saved register. + insertTest(MBB, CMovI.getIterator(), CMovI.getDebugLoc(), CondReg); + + auto getFCMOVOpcode = [](unsigned Opcode, bool Inverted) { + switch (Opcode) { + default: llvm_unreachable("Unexpected opcode!"); + case X86::CMOVBE_Fp32: case X86::CMOVNBE_Fp32: + case X86::CMOVB_Fp32: case X86::CMOVNB_Fp32: + case X86::CMOVE_Fp32: case X86::CMOVNE_Fp32: + case X86::CMOVP_Fp32: case X86::CMOVNP_Fp32: + return Inverted ? X86::CMOVE_Fp32 : X86::CMOVNE_Fp32; + case X86::CMOVBE_Fp64: case X86::CMOVNBE_Fp64: + case X86::CMOVB_Fp64: case X86::CMOVNB_Fp64: + case X86::CMOVE_Fp64: case X86::CMOVNE_Fp64: + case X86::CMOVP_Fp64: case X86::CMOVNP_Fp64: + return Inverted ? X86::CMOVE_Fp64 : X86::CMOVNE_Fp64; + case X86::CMOVBE_Fp80: case X86::CMOVNBE_Fp80: + case X86::CMOVB_Fp80: case X86::CMOVNB_Fp80: + case X86::CMOVE_Fp80: case X86::CMOVNE_Fp80: + case X86::CMOVP_Fp80: case X86::CMOVNP_Fp80: + return Inverted ? X86::CMOVE_Fp80 : X86::CMOVNE_Fp80; + } + }; + + // Rewrite the CMov to use the !ZF flag from the test. + CMovI.setDesc(TII->get(getFCMOVOpcode(CMovI.getOpcode(), Inverted))); + FlagUse.setIsKill(true); + LLVM_DEBUG(dbgs() << " fixed fcmov: "; CMovI.dump()); } void X86FlagsCopyLoweringPass::rewriteCondJmp( Modified: stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp ============================================================================== --- stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp Tue Jan 7 20:09:02 2020 (r356467) +++ stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp Tue Jan 7 20:09:58 2020 (r356468) @@ -2198,7 +2198,7 @@ unsigned X86::getCMovOpcode(unsigned RegBytes, bool Ha default: llvm_unreachable("Illegal register size!"); case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr; case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr; - case 8: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV64rr; + case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr; } }