From owner-p4-projects@FreeBSD.ORG Fri Aug 22 14:45:24 2003 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id C360D16A4C1; Fri, 22 Aug 2003 14:45:23 -0700 (PDT) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 48BA016A4BF; Fri, 22 Aug 2003 14:45:23 -0700 (PDT) Received: from harmony.village.org (rover.bsdimp.com [204.144.255.66]) by mx1.FreeBSD.org (Postfix) with ESMTP id 5D9B943F75; Fri, 22 Aug 2003 14:45:22 -0700 (PDT) (envelope-from imp@bsdimp.com) Received: from localhost (warner@rover2.village.org [10.0.0.1]) by harmony.village.org (8.12.9/8.12.3) with ESMTP id h7MLjJFL004752; Fri, 22 Aug 2003 15:45:20 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Fri, 22 Aug 2003 15:45:15 -0600 (MDT) Message-Id: <20030822.154515.101560696.imp@bsdimp.com> To: jhb@freebsd.org From: "M. Warner Losh" In-Reply-To: References: <20030821192214.GA25805@ns1.xcllnt.net> X-Mailer: Mew version 2.2 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit cc: perforce@freebsd.org cc: marcel@xcllnt.net Subject: Re: PERFORCE change 36551 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Aug 2003 21:45:24 -0000 In message: John Baldwin writes: : : On 21-Aug-2003 Marcel Moolenaar wrote: : > On Thu, Aug 21, 2003 at 10:32:25AM -0700, Marcel Moolenaar wrote: : >> : >> > If the UART devices raise an ISA interrupt, then by my reading, : >> > the ACPI resource should specify the ISA interrupt number (0-15), : >> > and the MADT should include a source override that maps that : >> > ISA interrupt number to a global interrupt number of 66 or : >> > whatever (which maps to a SAPIC:intpin). : >> : >> This makes sense. It's however not how it is (unfortunately). : > : > The updated SPPA specification (HP's ia64 platform) has a section : > devoted to the interrupt polarity and mode of the UART. It basicly : > says this: : > o The DIG64 HCDP table [supported] or the Mcrosoft SPCR table : > [unsupported] tells whether the UART is a PCI device or not. : > o PCI UARTs have level triggered, active low interrupts. They : > are not described in ACPI then (reminder: this is SPPA). : > o Non-PCI UARTs described in the ACPI namespace have interrupt : > polarity and mode as described by _CRS in the device object! : > o Non-PCI devices that are not decribed in the ACPI namespace : > can still be mentioned in the HCDP table and we [FreeBSD] : > will use the UART as console. Interrupt polarity and mode : > should be assumed active low, level sensitive. : > Currently we will panic the moment we try to go single-user : > or multi-user because there will not be a device major number : > assigned to the console. We need to catch this case someday. : > : > So: It appears that we need to interpret the _CRS method, field : > or whatever. Especially the Interrupt Descriptor. : > : > Going to the source: in acpi_parse_resources() we need to create : > a callback to MD code to tell it about polarity and mode. This : > means tweaking the ACPI_RSTYPE_IRQ or ACPI_RSTYPE_EXT_IRQ cases. : > Better would be to create bus methods for this (see for example : > acpi_res_set_irq()). : : Yes. For i386 definitely it would make sense to have a bus method : that bubbles back up to the nexus(4) and eventually calls the : MD interrupt code. Maybe some kind of interrupt properties kobj : interface: : : INTERFACE interrupt_properties : : # : # Set the polarity to one of three values: : # - conforming (conform to the bus attached to, the bus can set : # this on the way up through the chain maybe?) : # - active high : # - active low : # : METHOD int set_polarity { : device_t dev; : device_t child; : struct resource *irq; : int polarity; : }; : : # : # Set the trigger mode to one of three values: : # - conforming (conform to the bus attached to, the bus can set : # this on the way up through the chain maybe?) : # - edge triggered : # - level triggered PC Card defines 'pulse triggered' interrupts too. : # : METHOD int set_trigger_mode { : device_t dev : device_t child; : struct resource *irq; : int trigger_mode; : }; : : Or I guess we could just add these to the bus interface. : : What do you think we should do? Something like this in the bus interface, but this brushes up against the bigger 'interrupt sharing' and 'fast interrupt sharing' problems, no? Warner