Date: Tue, 31 Jan 2012 15:39:06 +0000 (UTC) From: Grzegorz Bernacki <gber@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r230815 - projects/armv6/sys/arm/arm Message-ID: <201201311539.q0VFd6PG042430@svn.freebsd.org>
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Author: gber Date: Tue Jan 31 15:39:06 2012 New Revision: 230815 URL: http://svn.freebsd.org/changeset/base/230815 Log: armv7: Fix TTB setup, little cleanup When TTB is written to CP15 register, proper memory model must be set. Submitted by: Lukasz Plachno Obtained from: Marvell, Semihalf Modified: projects/armv6/sys/arm/arm/cpufunc_asm_armv7.S Modified: projects/armv6/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- projects/armv6/sys/arm/arm/cpufunc_asm_armv7.S Tue Jan 31 15:38:06 2012 (r230814) +++ projects/armv6/sys/arm/arm/cpufunc_asm_armv7.S Tue Jan 31 15:39:06 2012 (r230815) @@ -32,8 +32,6 @@ #include <machine/asm.h> __FBSDID("$FreeBSD$"); -#define TTB (0x59) - .Lcoherency_level: .word _C_LABEL(arm_cache_loc) .Lcache_type: @@ -50,6 +48,19 @@ ENTRY(armv7_setttb) bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */ ldmia sp!, {r0, lr} dsb +#if defined(SMP) + /* + * Settings for architecture with SMP extension: + * PT memory: inner WBWA, shareable; outer WBWA, non-shareable + */ + orr r0, r0, #106 +#else + /* + * Settings for architecture without SMP extension: + * PT memory: inner-cacheable, non-shareable; outer WB, non-shareable + */ + orr r0, r0, #25 +#endif mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ dsb
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