From owner-freebsd-hackers Mon Aug 26 10:51:57 1996 Return-Path: owner-hackers Received: (from root@localhost) by freefall.freebsd.org (8.7.5/8.7.3) id KAA27421 for hackers-outgoing; Mon, 26 Aug 1996 10:51:57 -0700 (PDT) Received: from Kitten.mcs.com (Kitten.mcs.com [192.160.127.90]) by freefall.freebsd.org (8.7.5/8.7.3) with ESMTP id KAA27413 for ; Mon, 26 Aug 1996 10:51:54 -0700 (PDT) Received: from venus.mcs.com (root@Venus.mcs.com [192.160.127.92]) by Kitten.mcs.com (8.7.5/8.7.5) with SMTP id MAA23182; Mon, 26 Aug 1996 12:51:37 -0500 (CDT) Received: by venus.mcs.com (/\==/\ Smail3.1.28.1 #28.13) id ; Mon, 26 Aug 96 12:51 CDT Message-Id: Subject: Re: [Fwd: Fastvid,NT,Pentium Pro Performance: Expanation] (fwd) To: rsnow@lgc.com (Rob Snow) Date: Mon, 26 Aug 1996 12:51:36 -0500 (CDT) From: "Lars Jonas Olsson" Cc: jonas@mcs.net, hackers@freebsd.org In-Reply-To: from "Rob Snow" at Aug 25, 96 01:10:02 pm X-Mailer: ELM [version 2.4 PL24] Content-Type: text Sender: owner-hackers@freebsd.org X-Loop: FreeBSD.org Precedence: bulk I'm also interested in maximising PCI memory copy speed. I got this mail from John Hinkley that wrote FASTVID. I'm however using Triton II chip set and am most interested in read speed from a memory mapped PCI frame grabber. Jonas >From CompuServe.COM!72466.1403 Mon Aug 26 12:20:54 1996 >Return-Path: <72466.1403@CompuServe.COM> >Received: by mailbox.mcs.com (/\==/\ Smail3.1.28.1 #28.5) > id ; Mon, 26 Aug 96 12:20 CDT >Received: by hil-img-5.compuserve.com (8.6.10/5.950515) > id NAA05839; Mon, 26 Aug 1996 13:20:48 -0400 >Date: 26 Aug 96 13:19:03 EDT >From: John Hinkley <72466.1403@CompuServe.COM> >To: "\"Lars Jonas Olsson\"" >Subject: Re: PCI to DRAM copy speed >Message-ID: <960826171903_72466.1403_EHB153-1@CompuServe.COM> >Status: OR Jonas, > Can I forward this (FASTVID code fragment) to either XFree86 > (Free X server for UNIX and OS/2) and/or FreeBSD? It's fine with me... John. >From CompuServe.COM!72466.1403 Mon Aug 12 22:33:47 1996 >Return-Path: <72466.1403@CompuServe.COM> >Received: by mailbox.mcs.com (/\==/\ Smail3.1.28.1 #28.5) > id ; Mon, 12 Aug 96 22:33 CDT >Received: by hil-img-4.compuserve.com (8.6.10/5.950515) > id XAA04478; Mon, 12 Aug 1996 23:33:46 -0400 >Date: 12 Aug 96 23:32:17 EDT >From: John Hinkley <72466.1403@CompuServe.COM> >To: "\"Lars Jonas Olsson\"" >Subject: Re: PCI to DRAM copy speed >Message-ID: <960813033216_72466.1403_EHB50-2@CompuServe.COM> >Status: OR Lars, Thanks for the interesting code fragment. Your method for optimizing the Neptune chipset looks vaguely similar to that used on the Pentium Pro -- except the Pro has moved the write combining option onto the processor rather than the chipset: setup_lfb(unsigned int base, int mb) // base = address of LFB // mb = number of megabytes VRAM { #define SVGA_PHYSBASE 0x202 #define SVGA_MASK 0x203 struct QWORD { unsigned int eax; unsigned int edx; } q; unsigned int mask; // identifies size controlled by MSR if (mb == 1) mask = base | 0xFFF00000; else if (mb == 2) mask = base | 0xFFE00000; else if (mb == 4) mask = base | 0xFFC00000; else // if (mb == 8) mask = base | 0xFF800000; // first disable the MSR pair in case it's in use q.edx = 0; q.eax = 0; write_msr(SVGA_MASK, q.eax, q.edx); // 00 = no cache // 01 = write combining // 04 = write through // 05 = write proteced // 06 = write back q.edx = 0x00000000; q.eax = base | 1; // 1 == write combining write_msr(SVGA_PHYSBASE, q.eax, q.edx); q.edx = 0x0000000f; q.eax = mask | 0x00000800; // 800 bit enables MSR write_msr(SVGA_MASK, q.eax, q.edx); } write_msr() uses the WRMSR instruction to write the contents of EDX:EAX out to the indicated MSR register. The equivalent of: mov eax,q.eax mov edx,q.edx wrmsr MSR_REG The MSR registers are used in pairs to control the properties of memory space. WRMSR is a ring-0 instruction so you can't run it from a virtual DOS session. John.