From owner-freebsd-hackers Sat Nov 8 02:44:44 1997 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id CAA29986 for hackers-outgoing; Sat, 8 Nov 1997 02:44:44 -0800 (PST) (envelope-from owner-freebsd-hackers) Received: from d198-232.uoregon.edu (d198-232.uoregon.edu [128.223.198.232]) by hub.freebsd.org (8.8.7/8.8.7) with ESMTP id CAA29981 for ; Sat, 8 Nov 1997 02:44:41 -0800 (PST) (envelope-from mini@d198-232.uoregon.edu) Received: (from mini@localhost) by d198-232.uoregon.edu (8.8.5/8.8.5) id CAA21035; Sat, 8 Nov 1997 02:44:26 -0800 (PST) Message-ID: <19971108024426.54269@micron.mini.net> Date: Sat, 8 Nov 1997 02:44:26 -0800 From: Jonathan Mini To: Mike Smith Cc: hackers@FreeBSD.ORG Subject: Re: x86 gods; advice? Suggestions? References: <19971108021451.30385@micron.mini.net> <199711081022.UAA00794@word.smith.net.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Mailer: Mutt 0.85e In-Reply-To: <199711081022.UAA00794@word.smith.net.au>; from Mike Smith on Sat, Nov 08, 1997 at 08:52:11PM +1030 X-files: The Truth is Out There Sender: owner-freebsd-hackers@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk Mike Smith stands accused of saying: > > > > - hop into the kernel, from the vm86 task. The kernel would be in > > > > a situation where it is in a ring 0 32bit TSS with a vm86 TSS which > > > > has mappings to do some basic BIOS calls for it, possibly even some > > > > complex ones. > > > > > > This isn't making a lot of sense to me. Are you implying that one > > > could be in 32-bit PM and vm86 mode at the same time? > > > > No. I am saying that the kernel has on it's hands two prepped and functional > > TSS's. One which describes a vm86 environment suitable for making BIOS calls, > > and another which is the 32bit protected mode TSS that the kernel is used to > > having. > > Uh. I am still not understanding. With these on hand, what then? How > do you swap between them in a useful fashion? When you say "TSS" do > you just mean segment descriptors, or is there more to it than this? Sorry, TSS is an Intel term. The TSS is everything that defines the task. It's LDT, IO map, and a little bit of dataspace to hold that task's state. (regs, flags, processor mode, etc) A task gate is implemented as a entry in the LDT, GDT, or IDT that you jump through. I am assuming that a TSS for the three types of kernel use, as well as a task gate for moving from one to the other would be available. Otherwise, you have to rely on some sort of fault-catcher in order to leave the processor state. (as with the vm86 code, you need to have something like an IRQ or exception to leave the task) If you like, I can dig up specifics as to how this works. -- Jonathan Mini Ingenious Productions Software Development P.O. Box 5693, Eugene, Or. 97405 "A child of five could understand this! Quick -- Fetch me a child of five."