From owner-svn-src-head@freebsd.org Sun Jul 2 21:51:33 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 7A6E1DADF52 for ; Sun, 2 Jul 2017 21:51:33 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from outbound1a.eu.mailhop.org (outbound1a.eu.mailhop.org [52.58.109.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 1537A78006 for ; Sun, 2 Jul 2017 21:51:32 +0000 (UTC) (envelope-from ian@freebsd.org) X-MHO-User: 942e0956-5f70-11e7-b2f5-7fbc454a3a22 X-Report-Abuse-To: https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information X-Originating-IP: 73.78.92.27 X-Mail-Handler: DuoCircle Outbound SMTP Received: from ilsoft.org (unknown [73.78.92.27]) by outbound1.eu.mailhop.org (Halon) with ESMTPSA id 942e0956-5f70-11e7-b2f5-7fbc454a3a22; Sun, 02 Jul 2017 21:51:19 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.15.2/8.15.2) with ESMTP id v62LpIPv006872; Sun, 2 Jul 2017 15:51:18 -0600 (MDT) (envelope-from ian@freebsd.org) Message-ID: <1499032278.86861.92.camel@freebsd.org> Subject: Re: svn commit: r320577 - head/sys/dev/sdhci From: Ian Lepore To: Marius Strobl , src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Date: Sun, 02 Jul 2017 15:51:18 -0600 In-Reply-To: <201707021913.v62JD1fh060028@repo.freebsd.org> References: <201707021913.v62JD1fh060028@repo.freebsd.org> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.18.5.1 FreeBSD GNOME Team Port Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 02 Jul 2017 21:51:33 -0000 On Sun, 2017-07-02 at 19:13 +0000, Marius Strobl wrote: > Author: marius > Date: Sun Jul  2 19:13:01 2017 > New Revision: 320577 > URL: https://svnweb.freebsd.org/changeset/base/320577 > > Log: >   Retry up to 20 ms to enable bus power as at least with some Intel >   SDHCI/eMMC controllers the first attempt after a D3 to D0 > transition, >   i. e. when the firmware has put the devices into D3 state before, >   can fail. > > Modified: >   head/sys/dev/sdhci/sdhci.c > > Modified: head/sys/dev/sdhci/sdhci.c > ===================================================================== > ========= > --- head/sys/dev/sdhci/sdhci.c Sun Jul  2 16:20:49 2017 > (r320576) > +++ head/sys/dev/sdhci/sdhci.c Sun Jul  2 19:13:01 2017 > (r320577) > @@ -366,6 +366,7 @@ sdhci_set_clock(struct sdhci_slot *slot, uint32_t > cloc >  static void >  sdhci_set_power(struct sdhci_slot *slot, u_char power) >  { > + int i; >   uint8_t pwr; >   >   if (slot->power == power) > @@ -394,9 +395,20 @@ sdhci_set_power(struct sdhci_slot *slot, u_char > power) >   break; >   } >   WR1(slot, SDHCI_POWER_CONTROL, pwr); > - /* Turn on the power. */ > + /* > +  * Turn on VDD1 power.  Note that at least some Intel > controllers can > +  * fail to enable bus power on the first try after > transiting from D3 > +  * to D0, so we give them up to 20 ms. > +  */ >   pwr |= SDHCI_POWER_ON; > - WR1(slot, SDHCI_POWER_CONTROL, pwr); > + for (i = 0; i < 20; i++) { > + WR1(slot, SDHCI_POWER_CONTROL, pwr); > + if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) > + break; > + DELAY(100); > + } The comment says 20ms, but the code says 2ms. -- Ian > + if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) > + slot_printf(slot, "Bus power failed to enable"); >   >   if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { >   WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); >