Date: Thu, 11 Mar 2021 10:19:31 +0000 From: bugzilla-noreply@freebsd.org To: x11@FreeBSD.org Subject: [Bug 254190] graphics/drm-kmod: I get corruption at the top of all of my consoles Message-ID: <bug-254190-7141-TolVUCxiTI@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-254190-7141@https.bugs.freebsd.org/bugzilla/> References: <bug-254190-7141@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D254190 --- Comment #8 from Steven Friedrich <Steven.E.Friedrich@Gmail.com> --- As an old hardware guy, I was curious when I saw this message: "unknown: memory range not supported" and this device: none0@pci0:0:20:2: class=3D0x050000 card=3D0x72708086 chip=3D0xa36f808= 6 rev=3D0x10 hdr=3D0x00 vendor =3D 'Intel Corporation' device =3D 'Cannon Lake PCH Shared SRAM' class =3D memory subclass =3D RAM I thought, what is that? Well I found a rather opaque description in an In= tel document at: https://www.intel.com/content/dam/www/public/us/en/documents/technical-spec= ifications/300-series-chipset-on-package-pch-datasheet-vol-1.pdf 21.7.2 SRAM The local SRAM is used for ISH FW code storage and to read/write operational data. The local SRAM block includes both the physical SRAM as well as the controller logic. The SRAM is a total of 640 kbytes organized into banks o= f 32 kB each and is 32-bit wide. The SRAM is shared with Intel CSME as shareable memory. To protect against memory errors, the SRAM includes ECC support. = The ECC mechanism is able to detect multi-bit errors and correct for single bit errors. The ISH firmware has the ability to put unused SRAM banks into low= er power states to reduce power consumption. That sounds to me like memory Intel uses between their OWN devices. I would hope you would contact technical support at Intel and get clarifica= tion of whether you should be ignoring this memory range and leave it untouched. --=20 You are receiving this mail because: You are the assignee for the bug.=
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