Skip site navigation (1)Skip section navigation (2)
Date:      Sat, 7 Jan 2012 04:13:25 +0000 (UTC)
From:      Adrian Chadd <adrian@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r229765 - head/sys/mips/atheros
Message-ID:  <201201070413.q074DPNR024073@svn.freebsd.org>

next in thread | raw e-mail | index | archive | help
Author: adrian
Date: Sat Jan  7 04:13:25 2012
New Revision: 229765
URL: http://svn.freebsd.org/changeset/base/229765

Log:
  Fix the ar724x shift calculation when writing to the PCI config space.
  
  This was preventing the ath driver from being loaded at runtime.
  It worked fine when compiled statically into the kernel but not when
  kldload'ed after the system booted.
  
  The root cause was that PCIR_INTLINE (register 60) was being
  overwritten by zeros when register 62 was being written to.
  A subsequent read of this register would return 0, and thus
  the rest of the PCI glue assumed an IRQ resource had already
  been allocated.  This caused the device to fail to attach at
  runtime as the device itself didn't contain any IRQ resources.
  
  TODO: go back over the ar71xx and ar724x PCI config read/write
  code and ensure it's correct.

Modified:
  head/sys/mips/atheros/ar724x_pci.c

Modified: head/sys/mips/atheros/ar724x_pci.c
==============================================================================
--- head/sys/mips/atheros/ar724x_pci.c	Sat Jan  7 03:32:47 2012	(r229764)
+++ head/sys/mips/atheros/ar724x_pci.c	Sat Jan  7 04:13:25 2012	(r229765)
@@ -93,7 +93,7 @@ ar724x_pci_write(uint32_t reg, uint32_t 
 	uint32_t val, mask, shift;
 
 	/* Register access is 32-bit aligned */
-	shift = 8 * (offset & (bytes % 4));
+	shift = (offset & 3) * 8;
 	if (bytes % 4)
 		mask = (1 << (bytes * 8)) - 1;
 	else



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201201070413.q074DPNR024073>